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Adding debug features to fifo_sync
-Ability to dump array -Error on attempt to write to fifo while full
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@ -9,7 +9,8 @@ module oh_fifo_sync #(parameter DW = 104, //FIFO width
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parameter DEPTH = 32, //FIFO depth
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parameter REG = 1, //Register fifo output
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parameter PROG_FULL = DEPTH-1, //prog_full threshold
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parameter AW = $clog2(DEPTH) //rd_count width
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parameter AW = $clog2(DEPTH), //rd_count width
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parameter DUMPVAR = 1 // dump array
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)
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(
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input clk, // clock
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@ -84,6 +85,7 @@ module oh_fifo_sync #(parameter DW = 104, //FIFO width
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oh_memory_dp
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#(.DW(DW),
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.DEPTH(DEPTH),
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.DUMPVAR(DUMPVAR),
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.REG(REG))
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mem (// read port
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.rd_dout (dout[DW-1:0]),
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@ -97,4 +99,18 @@ module oh_fifo_sync #(parameter DW = 104, //FIFO width
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.wr_addr (wr_addr[AW-1:0]),
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.wr_din (din[DW-1:0]));
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`ifdef TARGET_SIM
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assign rd_error = rd_en & empty;
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assign wr_error = wr_en & full;
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always @ (posedge rd_error)
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#1 if(rd_error)
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$display ("ERROR: Reading empty FIFO in %m at ",$time);
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always @ (posedge wr_error)
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#1 if(wr_error)
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$display ("ERROR: Writing full FIFO in %m at ",$time);
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`endif
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endmodule // oh_fifo_sync
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