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Removing delay + clock gating

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- delay could hide bad designs..
- clock gating was hard to handle from outside
This commit is contained in:
Andreas Olofsson 2016-02-25 14:41:30 -05:00
parent 8f37435d95
commit 2a22cd6ff8
2 changed files with 12 additions and 13 deletions
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2
common/hdl/oh_iddr.v
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@ -39,12 +39,10 @@ module oh_iddr (/*AUTOARG*/
// falling edge sample
always @ (negedge clk)
if(ce)
q2_sh[DW-1:0] <= din[DW-1:0];
// pipeline for alignment
always @ (posedge clk)
if(ce)
begin
q1[DW-1:0] <= q1_sl[DW-1:0];
q2[DW-1:0] <= q2_sh[DW-1:0];

7
common/hdl/oh_oddr.v
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@ -31,13 +31,14 @@ module oh_oddr (/*AUTOARG*/
//Generate different logic based on parameters
always @ (posedge clk)
if (ce)
begin
q1_sl[DW-1:0] <= #(0.1) din1[DW-1:0];
q2_sl[DW-1:0] <= #(0.1) din2[DW-1:0];
q1_sl[DW-1:0] <= din1[DW-1:0];
q2_sl[DW-1:0] <= din2[DW-1:0];
end
always @ (negedge clk)
q2_sh[DW-1:0] <= #(0.1) q2_sl[DW-1:0];
q2_sh[DW-1:0] <= q2_sl[DW-1:0];
assign out[DW-1:0] = clk ? q1_sl[DW-1:0] :
q2_sh[DW-1:0];