Fixing another bug (PS vs N)

common/hdl/oh_clockgate.v

@@ -7,7 +7,7 @@
 
 module oh_clockgate (
      input  clk, // clock input 
-     input  te, // test enable enable   
+     input  te, // test enable   
      input  en, // enable (from positive edge FF)
      output eclk // enabled clock output
      );

common/hdl/oh_datagate.v

@@ -19,7 +19,7 @@ module oh_datagate #(parameter DW = 32, // width of data inputs
    reg [N-1:0]    enable_pipe;   
    
    always @ (posedge clk)
-     enable_pipe[PS-1:0] <= {enable_pipe[PS-2:0],en};
+     enable_pipe[N-1:0] <= {enable_pipe[N-2:0],en};
    
    //Mask to 0 if no valid for last N cycles
    assign enable = en | (|enable_pipe[N-1:0]);