From 2b2c7197659889d0377182f48bea944ebb5d4584 Mon Sep 17 00:00:00 2001 From: "Andreas.Olofsson" Date: Wed, 4 Mar 2020 21:12:24 -0500 Subject: [PATCH] Fixing another bug (PS vs N) --- common/hdl/oh_clockgate.v | 2 +- common/hdl/oh_datagate.v | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/common/hdl/oh_clockgate.v b/common/hdl/oh_clockgate.v index f8c027d..dd50167 100644 --- a/common/hdl/oh_clockgate.v +++ b/common/hdl/oh_clockgate.v @@ -7,7 +7,7 @@ module oh_clockgate ( input clk, // clock input - input te, // test enable enable + input te, // test enable input en, // enable (from positive edge FF) output eclk // enabled clock output ); diff --git a/common/hdl/oh_datagate.v b/common/hdl/oh_datagate.v index 073097f..fdd2bee 100644 --- a/common/hdl/oh_datagate.v +++ b/common/hdl/oh_datagate.v @@ -19,7 +19,7 @@ module oh_datagate #(parameter DW = 32, // width of data inputs reg [N-1:0] enable_pipe; always @ (posedge clk) - enable_pipe[PS-1:0] <= {enable_pipe[PS-2:0],en}; + enable_pipe[N-1:0] <= {enable_pipe[N-2:0],en}; //Mask to 0 if no valid for last N cycles assign enable = en | (|enable_pipe[N-1:0]);