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Change to TXCFG register!

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- Made room for extra bit in ctrlmode register
This commit is contained in:
Andreas Olofsson 2016-01-11 21:35:57 -05:00
parent 34d1049bab
commit 2bbe1e11b1
3 changed files with 30 additions and 32 deletions
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43
elink/README.md
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@ -175,7 +175,7 @@ elink
## Registers
The full 32 bit physical address of an elink register is the address seen below added to the 12 bit elink ID that maps to address bits 31:20. As an example, if the elink ID is 0x810, then writing to the E_RESET register would be done to address 0x810F0200. Readback is done through the txrd channel with the source address sub field set to 810Dxxxx;
The full 32 bit physical address of an elink register is the address seen below added to the 12 bit elink ID that maps to address bits 31:20. As an example, if the elink ID is 0x810, then writing to the ELINK_RESET register would be done to address 0x810F0200. Readback is done through the txrd channel with the source address sub field set to 810Dxxxx;
REGISTER | ACCESS | ADDRESS | DESCRIPTION
-----------------|--------|---------|------------------
@ -208,8 +208,10 @@ Reset control register for the elink and Epiphany chip
FIELD | DESCRIPTION
-------- | --------------------------------------------------
[0] | 0: active
| 1: resets elink and Epiphany chip
[0] | 0: TX active
| 1: TX reset asserted
[1] | 0: RX active
| 1: RX reset asserted
-------------------------------
@ -273,8 +275,7 @@ TX configuration settings
FIELD | DESCRIPTION
-------- |---------------------------------------------------
[0] | 0: TX disabled (not implemented)
| 1: TX enabled
[0] | Not implemented (reserved for TX enable)
[1] | 0: MMU disabled
| 1: MMU enabled
[3:2] | 00: Address remapping disabled
@ -287,33 +288,31 @@ FIELD | DESCRIPTION
| 1001: Force SOUTH routing on address match (instead of "into" core)
| 1101: Force WEST routing on address match (instead of "into" core)
| 0011: Multicast routing (LABS)
[8] | Control mode select for TXRD/TXWR channels
[8] | Reservered for cltrmode[4]
[9] | Control mode select for TXRD/TXWR channels
| 0: ctrlmode field taken from incoming transmit packet
| 1: ctrlmode field taken E_TXCFG
[10:9] | 00: Normal transmit mode
| 01: GPIO direct drive mode
[11] | 0: Burst mode disabled
[10] | 0: Burst mode disabled
| 1: Burst mode enabled
[11:10] | 00: Normal transmit mode
| 01: GPIO direct drive mode
-------------------------------
## ELINK_TXSTATUS (0xF0214)
TX status register
TX status register. Sticky means once a signal goes high, it stays high until register is over written.
FIELD | DESCRIPTION
-------- |---------------------------------------------------
[0] | TXWR FIFO was full
[1] | TXRD FIFO was full
[2] | TXRR FIFO was full
[3] | TXWR stalled
[4] | TXRD stalled
[5] | TXRR stalled
[6] | WR_WAIT input pin was high
[7] | RD_WAIT input pin was high
[8] | Burst occured
[15:0] | TBD
[0] | Sticky TXWR FIFO full flag
[1] | Sticky TXRD FIFO full flag
[2] | Sticky TXRR FIFO full flag
[3] | Sticky TXWR wait flag
[4] | Sticky TXRD wait flag
[5] | Sticky TXRR wait flag
[6] | Sticky IO input WR_WAIT flag
[7] | Sticky IO input RD_WAIT flag
[8] | Sticky burst detection flag
-------------------------------

15
elink/hdl/etx_cfg.v
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@ -75,10 +75,11 @@ module etx_cfg (/*AUTOARG*/
wire [AW-1:0] srcaddr_in; // From p2e of packet2emesh.v
wire write_in; // From p2e of packet2emesh.v
// End of automatics
/*****************************/
/*ADDRESS DECODE LOGIC */
/*****************************/
//###########################
//# DECODE LOGIC
//###########################
packet2emesh #(.AW(AW))
p2e (.packet_in (etx_packet[PW-1:0]),
/*AUTOINST*/
@ -118,9 +119,9 @@ module etx_cfg (/*AUTOARG*/
assign mmu_enable = tx_cfg_reg[1];
assign remap_enable = (tx_cfg_reg[3:2]==2'b01);
assign ctrlmode[3:0] = tx_cfg_reg[7:4];
assign ctrlmode_bypass = tx_cfg_reg[8];
assign gpio_enable = (tx_cfg_reg[10:9]==2'b01);
assign burst_enable = tx_cfg_reg[11];
assign ctrlmode_bypass = tx_cfg_reg[9];
assign burst_enable = tx_cfg_reg[10];
assign gpio_enable = (tx_cfg_reg[11:10]==2'b01);
//###########################
//# STATUS REGISTER

4
elink/hdl/etx_core.v
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@ -198,12 +198,10 @@ module etx_core(/*AUTOARG*/
//# TX CONFIGURATION
//##################################################################
etx_cfg etx_cfg (.tx_status ({5'b0,
etx_cfg etx_cfg (.tx_status ({7'b0,
tx_burst,
tx_rd_wait,
tx_wr_wait,
etx_rd_wait,
etx_wr_wait,
txrr_wait,
txrd_wait,
txwr_wait,