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Fixing port declarations (thanks Verilator!)

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aolofsson 2014-12-15 16:39:28 -05:00
parent f281bf9e5d
commit 2c886c4e24
3 changed files with 11 additions and 13 deletions
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7
stubs/hdl/ISERDESE2.v
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@ -1,6 +1,6 @@
module ISERDESE2 (/*AUTOARG*/
// Outputs
O, QQ, SHIFTOUT1, SHIFTOUT2, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8,
O, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, SHIFTOUT1, SHIFTOUT2,
// Inputs
BITSLIP, CE1, CE2, CLKDIVP, CLK, CLKB, CLKDIV, OCLK, OCLKB,
DYNCLKDIVSEL, DYNCLKSEL, D, DDLY, OFB, RST, SHIFTIN1, SHIFTIN2
@ -25,9 +25,6 @@ module ISERDESE2 (/*AUTOARG*/
parameter SRVAL_Q4=0;
output O;
output QQ;
output SHIFTOUT1;
output SHIFTOUT2;
output Q1;
output Q2;
output Q3;
@ -36,6 +33,8 @@ module ISERDESE2 (/*AUTOARG*/
output Q6;
output Q7;
output Q8;
output SHIFTOUT1;
output SHIFTOUT2;
input BITSLIP;
input CE1;
input CE2;

11
stubs/hdl/PLLE2_BASE.v
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@ -1,7 +1,7 @@
module PLLE2_BASE (/*AUTOARG*/
// Outputs
CLKFB, LOCKED, CLKOUT0, CLKOUT1, CLKOUT2, CLKOUT3, CLKOUT4,
CLKOUT5, CLKFBOUT,
CLKFBOUT, LOCKED, CLKOUT0, CLKOUT1, CLKOUT2, CLKOUT3, CLKOUT4,
CLKOUT5,
// Inputs
CLKIN1, RST, PWRDWN, CLKFBIN
);
@ -43,9 +43,8 @@ module PLLE2_BASE (/*AUTOARG*/
input RST;
input PWRDWN;
input CLKFBIN;
output CLKFB;
output CLKFBOUT;
output LOCKED;
output CLKOUT0;
output CLKOUT1;
@ -53,7 +52,7 @@ module PLLE2_BASE (/*AUTOARG*/
output CLKOUT3;
output CLKOUT4;
output CLKOUT5;
output CLKFBOUT;
endmodule // PLLE2_BASE

6
stubs/hdl/fifo_64x16.v
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@ -16,9 +16,9 @@ module fifo_64x16(/*AUTOARG*/
input wr_clk;
input wr_en;
assign dout = 103'b0;
assign empty = 1'b0;
assign full = 1'b0;
assign dout = 64'b0;
assign empty = 1'b0;
assign full = 1'b0;
assign prog_full = 1'b0;
endmodule // fifo_64x16