diff --git a/edma/hdl/edma.v b/edma/hdl/edma.v
index 29232d4..5f1a7cc 100644
--- a/edma/hdl/edma.v
+++ b/edma/hdl/edma.v
@@ -35,6 +35,12 @@ module edma (/*AUTOARG*/
    output [PW-1:0]   edma_packet;
    input 	     edma_wait;
 
+
+
+   
+
+
+   
    assign edma_access=1'b0;
    assign edma_packet='d0;
    assign  mi_dout='d0;
diff --git a/elink/dv/test.memh b/elink/dv/test.memh
index 3c0bc70..3f41e8c 100644
--- a/elink/dv/test.memh
+++ b/elink/dv/test.memh
@@ -1,22 +1,8 @@
-00000000_00000000_00000000_00 //dummy
 00000000_11111111_80800000_0b //write to epiphany
-00000000_22222222_80800008_0b //write to epiphany
-00000000_33333333_80800010_0b //write to epiphany
-00000000_44444444_80800018_0b //write to epiphany
-00000000_55555555_80800020_0b //write to epiphany
+00000000_00000000_81000000_00 //END OF BURST
+00000000_00000000_81000000_00 //END OF BURST
+00000000_00000000_81000000_00 //END OF BURST
+00000000_00000000_81000000_00 //END OF BURST
+00000000_00000000_81000000_00 //END OF BURST
 810D0000_DEADBEEF_80800000_09 //read
-810D0008_DEADBEEF_80800008_09 //read
-810D0008_DEADBEEF_80800010_09 //read
-810D0018_DEADBEEF_80800018_09 //read
-810D0020_DEADBEEF_80800020_09 //read
-B7B6B5B4_B3B2B1B0_80800100_0f //write to epiphany
-C7C6C5C4_C3C2C1C0_80800108_0f //write to epiphany
-D7D6D5D4_D3D2D1D0_80800110_0f //write to epiphany
-E7E6E5E4_E3E2E1E0_80800118_0f //write to epiphany
-F7F6F5F4_F3F2F1F0_80800120_0f //write to epiphany
-810D0100_DEADBEEF_80800100_0d //read
-810D0108_DEADBEEF_80800108_0d //read
-810D0108_DEADBEEF_80800110_0d //read
-810D0118_DEADBEEF_80800118_0d //read
-810D0120_DEADBEEF_80800120_0d //read
-00000000_00000000_00000000_00 //END OF BURST
+00000000_00000000_81000000_00 //END OF BURST
diff --git a/emmu/hdl/emmu.v b/emmu/hdl/emmu.v
index baa0724..c0b671b 100644
--- a/emmu/hdl/emmu.v
+++ b/emmu/hdl/emmu.v
@@ -126,7 +126,7 @@ module emmu (/*AUTOARG*/
    //pipeline to compensate for table lookup pipeline 
    //assumes one cycle memory access!     
   
-   always @ (posedge  rd_clk or posedge reset)     
+   always @ (posedge  rd_clk)     
      if (reset)
        begin
 	  emesh_access_out         <= 1'b0;