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Making reset sync in emmu

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This commit is contained in:
Andreas Olofsson 2015-05-23 22:26:15 -04:00
parent 7b8a9cf474
commit 2cbf91b07b
3 changed files with 13 additions and 21 deletions
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6
edma/hdl/edma.v
View File

@ -35,6 +35,12 @@ module edma (/*AUTOARG*/
output [PW-1:0] edma_packet; output [PW-1:0] edma_packet;
input edma_wait; input edma_wait;
assign edma_access=1'b0; assign edma_access=1'b0;
assign edma_packet='d0; assign edma_packet='d0;
assign mi_dout='d0; assign mi_dout='d0;

26
elink/dv/test.memh
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@ -1,22 +1,8 @@
00000000_00000000_00000000_00 //dummy
00000000_11111111_80800000_0b //write to epiphany 00000000_11111111_80800000_0b //write to epiphany
00000000_22222222_80800008_0b //write to epiphany 00000000_00000000_81000000_00 //END OF BURST
00000000_33333333_80800010_0b //write to epiphany 00000000_00000000_81000000_00 //END OF BURST
00000000_44444444_80800018_0b //write to epiphany 00000000_00000000_81000000_00 //END OF BURST
00000000_55555555_80800020_0b //write to epiphany 00000000_00000000_81000000_00 //END OF BURST
00000000_00000000_81000000_00 //END OF BURST
810D0000_DEADBEEF_80800000_09 //read 810D0000_DEADBEEF_80800000_09 //read
810D0008_DEADBEEF_80800008_09 //read 00000000_00000000_81000000_00 //END OF BURST
810D0008_DEADBEEF_80800010_09 //read
810D0018_DEADBEEF_80800018_09 //read
810D0020_DEADBEEF_80800020_09 //read
B7B6B5B4_B3B2B1B0_80800100_0f //write to epiphany
C7C6C5C4_C3C2C1C0_80800108_0f //write to epiphany
D7D6D5D4_D3D2D1D0_80800110_0f //write to epiphany
E7E6E5E4_E3E2E1E0_80800118_0f //write to epiphany
F7F6F5F4_F3F2F1F0_80800120_0f //write to epiphany
810D0100_DEADBEEF_80800100_0d //read
810D0108_DEADBEEF_80800108_0d //read
810D0108_DEADBEEF_80800110_0d //read
810D0118_DEADBEEF_80800118_0d //read
810D0120_DEADBEEF_80800120_0d //read
00000000_00000000_00000000_00 //END OF BURST

2
emmu/hdl/emmu.v
View File

@ -126,7 +126,7 @@ module emmu (/*AUTOARG*/
//pipeline to compensate for table lookup pipeline //pipeline to compensate for table lookup pipeline
//assumes one cycle memory access! //assumes one cycle memory access!
always @ (posedge rd_clk or posedge reset) always @ (posedge rd_clk)
if (reset) if (reset)
begin begin
emesh_access_out <= 1'b0; emesh_access_out <= 1'b0;