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Making clock gater asic friendly
- removing reset, shouldn't be in logic - instantiating asic integrated clock gating cell - removing vectorization, shouldn't be here
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@ -5,34 +5,40 @@
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_clockgate #(parameter DW = 1, // width of data
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parameter ASIC = 0 // use ASIC lib
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module oh_clockgate # (parameter ASIC = 0, // use ASIC lib
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parameter PROJ = "E5" // project name (used for IP selection)
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)
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(
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input nrst, // active low sync reset (synced to input clk)
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input clk, // clock input
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input se, // scan enable
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input [DW-1:0] en, // enable (from positive edge FF)
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output [DW-1:0] eclk// enabled clock output
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);
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input clk, // clock input
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input te, // test enable enable
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input en, // enable (from positive edge FF)
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output eclk // enabled clock output
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);
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wire [DW-1:0] en_sh;
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wire [DW-1:0] en_sl;
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//Turn on clock if in scan mode or if enabled
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assign en_sl[DW-1:0] = en[DW-1:0] |
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{(DW){se}} |
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{(DW){~nrst}};
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//making signal stable
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oh_lat0 #(.DW(1)) lat0 (.out (en_sh[DW-1:0]),
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.in (en_sl[DW-1:0]),
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.clk (clk)
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);
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assign eclk[DW-1:0] = {(DW){clk}} & en_sh[DW-1:0];
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generate
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if(ASIC)
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begin : asic
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asic_icg #(.PROJ(PROJ))
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asic_icg (.en(en),
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.te(te),
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.clk(clk),
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.eclk(eclk));
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end
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else
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begin : generic
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wire en_sh;
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wire en_sl;
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//Stable low/valid rising edge enable
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assign en_sl = en | te;
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//Stable high enable signal
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oh_lat0 lat0 (.out (en_sh),
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.in (en_sl),
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.clk (clk));
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assign eclk = clk & en_sh;
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end
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endgenerate
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endmodule // oh_clockgate
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