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Fixing compiler warnings

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aolofsson 2021-07-25 15:16:52 -04:00
parent eb162a3bf3
commit 2dd46abdd1
3 changed files with 29 additions and 30 deletions
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23
common/hdl/oh_fifo_async.v
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@ -19,9 +19,8 @@ module oh_fifo_async
parameter PROGFULL = DEPTH-1, // programmable almost full level parameter PROGFULL = DEPTH-1, // programmable almost full level
parameter SHAPE = "square" // hard macro shape (square, tall, wide) parameter SHAPE = "square" // hard macro shape (square, tall, wide)
) )
( (//nreset
//basic interface input nreset,
input nreset, //async reset
//write port //write port
input wr_clk, input wr_clk,
input [DW-1:0] wr_din, // data to write input [DW-1:0] wr_din, // data to write
@ -53,7 +52,6 @@ module oh_fifo_async
); );
//local wires //local wires
wire [AW-1:0] wr_count; // valid entries in fifo
reg [AW:0] wr_addr; // extra bit for wraparound comparison reg [AW:0] wr_addr; // extra bit for wraparound comparison
reg [AW:0] rd_addr; reg [AW:0] rd_addr;
wire [AW:0] wr_addr_gray; wire [AW:0] wr_addr_gray;
@ -61,6 +59,9 @@ module oh_fifo_async
wire [AW:0] rd_addr_gray; wire [AW:0] rd_addr_gray;
wire [AW:0] rd_addr_gray_sync; wire [AW:0] rd_addr_gray_sync;
wire [AW:0] rd_addr_sync; wire [AW:0] rd_addr_sync;
wire fifo_write;
wire rd_nreset;
wire wr_nreset;
@ -71,13 +72,13 @@ module oh_fifo_async
oh_rsync #(.SYN(SYN), oh_rsync #(.SYN(SYN),
.SYNCPIPE(SYNCPIPE)) .SYNCPIPE(SYNCPIPE))
wr_rsync (.nrst_out (wr_nreset), wr_rsync (.nrst_out (wr_nreset),
.clk (wrclk), .clk (wr_clk),
.nrst_in (nreset)); .nrst_in (nreset));
oh_rsync #(.SYN(SYN), oh_rsync #(.SYN(SYN),
.SYNCPIPE(SYNCPIPE)) .SYNCPIPE(SYNCPIPE))
rd_rsync (.nrst_out (rd_nreset), rd_rsync (.nrst_out (rd_nreset),
.clk (rdclk), .clk (rd_clk),
.nrst_in (nreset)); .nrst_in (nreset));
//########################### //###########################
@ -118,8 +119,8 @@ module oh_fifo_async
oh_dsync #(.SYN(SYN), oh_dsync #(.SYN(SYN),
.SYNCPIPE(SYNCPIPE)) .SYNCPIPE(SYNCPIPE))
wr_sync[AW:0] (.dout (wr_addr_gray_sync[AW:0]), wr_sync[AW:0] (.dout (wr_addr_gray_sync[AW:0]),
.clk (rdclk), .clk (rd_clk),
.nreset(rd_nreset), .nreset (rd_nreset),
.din (wr_addr_gray[AW:0])); .din (wr_addr_gray[AW:0]));
//########################### //###########################
@ -134,7 +135,7 @@ module oh_fifo_async
oh_dsync #(.SYN(SYN), oh_dsync #(.SYN(SYN),
.SYNCPIPE(SYNCPIPE)) .SYNCPIPE(SYNCPIPE))
rd_sync[AW:0] (.dout (rd_addr_gray_sync[AW:0]), rd_sync[AW:0] (.dout (rd_addr_gray_sync[AW:0]),
.clk (wrclk), .clk (wr_clk),
.nreset (wr_nreset), .nreset (wr_nreset),
.din (rd_addr_gray[AW:0])); .din (rd_addr_gray[AW:0]));
@ -149,9 +150,6 @@ module oh_fifo_async
assign wr_full = (wr_addr[AW-1:0] == rd_addr_sync[AW-1:0]) & assign wr_full = (wr_addr[AW-1:0] == rd_addr_sync[AW-1:0]) &
(wr_addr[AW] != rd_addr_sync[AW]); (wr_addr[AW] != rd_addr_sync[AW]);
//########################### //###########################
//# Memory Array //# Memory Array
//########################### //###########################
@ -160,7 +158,6 @@ module oh_fifo_async
.DEPTH(DEPTH), .DEPTH(DEPTH),
.REG(REG), .REG(REG),
.SYN(SYN), .SYN(SYN),
.SYN(SYN),
.SHAPE(SHAPE)) .SHAPE(SHAPE))
oh_memory_dp(.wr_wem ({(DW){1'b1}}), oh_memory_dp(.wr_wem ({(DW){1'b1}}),
.wr_en (fifo_write), .wr_en (fifo_write),

7
common/hdl/oh_memory_dp.v
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@ -40,7 +40,7 @@ module oh_memory_dp
); );
generate generate
if(SYN=="true") begin: soft if(SYN=="true") begin
//######################################### //#########################################
// Generic RAM for synthesis // Generic RAM for synthesis
//######################################### //#########################################
@ -53,7 +53,8 @@ module oh_memory_dp
always @(posedge wr_clk) always @(posedge wr_clk)
for (i=0;i<DW;i=i+1) for (i=0;i<DW;i=i+1)
if (wr_en & wr_wem[i]) if (wr_en & wr_wem[i])
ram[wr_addr[AW-1:0]][i] <= wr_din[i]; ram[wr_addr[AW-1:0]][i] = wr_din[i];
//read port //read port
assign rdata[DW-1:0] = ram[rd_addr[AW-1:0]]; assign rdata[DW-1:0] = ram[rd_addr[AW-1:0]];
@ -67,7 +68,7 @@ module oh_memory_dp
assign rd_dout[DW-1:0] = (REG==1) ? rd_reg[DW-1:0] : assign rd_dout[DW-1:0] = (REG==1) ? rd_reg[DW-1:0] :
rdata[DW-1:0]; rdata[DW-1:0];
end // block: soft end // block: soft
else begin: hard else begin
asic_memory_dp #(.DW(DW), asic_memory_dp #(.DW(DW),
.DEPTH(DEPTH), .DEPTH(DEPTH),
.SHAPE(SHAPE), .SHAPE(SHAPE),

7
common/hdl/oh_rsync.v
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@ -16,17 +16,18 @@ module oh_rsync
); );
generate generate
if(SYN=="true") begin: soft if(SYN=="true")
begin
reg [SYNCPIPE-1:0] sync_pipe; reg [SYNCPIPE-1:0] sync_pipe;
always @ (posedge clk or negedge nrst_in) always @ (posedge clk or negedge nrst_in)
if(!nrst_in) if(!nrst_in)
sync_pipe[SYNCPIPE-1:0] <= 1'b0; sync_pipe[SYNCPIPE-1:0] <= 'b0;
else else
sync_pipe[SYNCPIPE-1:0] <= {sync_pipe[SYNCPIPE-2:0],1'b1}; sync_pipe[SYNCPIPE-1:0] <= {sync_pipe[SYNCPIPE-2:0],1'b1};
assign nrst_out = sync_pipe[SYNCPIPE-1]; assign nrst_out = sync_pipe[SYNCPIPE-1];
end end
else else
begin: hard begin
asic_rsync #(.TYPE(TYPE), asic_rsync #(.TYPE(TYPE),
.SYNCPIPE(SYNCPIPE)) .SYNCPIPE(SYNCPIPE))
asic_rsync (.clk(clk), asic_rsync (.clk(clk),