From 2de2dc3fd64d342b9aeed58226bd872d627ed3cc Mon Sep 17 00:00:00 2001
From: Andreas Olofsson <andreas@adapteva.com>
Date: Tue, 16 Feb 2016 14:25:44 -0500
Subject: [PATCH] Adding place holder for open source tools - Keep dreaming....

---
 chip/eda/README.md            |  4 ++++
 chip/eda/open/README.md       | 25 +++++++++++++++++++++++++
 chip/eda/open/yosys/README.md |  2 ++
 3 files changed, 31 insertions(+)
 create mode 100644 chip/eda/README.md
 create mode 100644 chip/eda/open/README.md
 create mode 100644 chip/eda/open/yosys/README.md

diff --git a/chip/eda/README.md b/chip/eda/README.md
new file mode 100644
index 0000000..613cae1
--- /dev/null
+++ b/chip/eda/README.md
@@ -0,0 +1,4 @@
+## CONTENTS
+* EDA specific scripts
+* Some companies don't allow sharing, in that case you probably want to have a private repo of scripts and include a symbolic link here to that repo.
+* For example "ln -s /home/synopsys ."
\ No newline at end of file
diff --git a/chip/eda/open/README.md b/chip/eda/open/README.md
new file mode 100644
index 0000000..22a5db8
--- /dev/null
+++ b/chip/eda/open/README.md
@@ -0,0 +1,25 @@
+#CONTENT
+* Various open source tools
+* front end: yosys
+* analog simulator: spice
+* verilog simulator: iverilog, verilator
+* pnr: n/a
+* lvs: n/a
+* drc: n/a
+* schmatic entry: n/a
+* polygon-push: n/a
+* analog circuit generators: n/a
+* logical equivalence : n/a
+* dft compiler : n/a
+* power compiler: n/a
+* power grid analysis: n/a
+* extraction tool: n/a
+* signal integrity: n/a
+* cell characterization: n/a
+* transistor level STA: n/a
+* signoff STA: n/a
+* scan pattern generator: n/a
+* memory compiler: n/a
+* generic standard cell library: n/a
+* generic io library: n/a
+
diff --git a/chip/eda/open/yosys/README.md b/chip/eda/open/yosys/README.md
new file mode 100644
index 0000000..a85c49b
--- /dev/null
+++ b/chip/eda/open/yosys/README.md
@@ -0,0 +1,2 @@
+## CONTENTS
+* place holder for yosys synthesis tool...
\ No newline at end of file