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Merge branch 'master' of https://github.com/parallella/oh

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This commit is contained in:
Andreas Olofsson 2015-11-04 19:20:13 -05:00
commit 2ed60c5698
3 changed files with 7 additions and 5 deletions
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4
Makefile.in
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@ -22,11 +22,11 @@ parallella-z7020: builddeps
# Temporary
package_axi_elink: builddeps
vivado -mode batch -source $(top_srcdir)/elink/scripts/xilinx/package_axi_elink.tcl
vivado -mode batch -source $(top_srcdir)/elink/projects/xilinx/package_axi_elink.tcl
# Temporary
elink: builddeps
vivado -mode batch -source $(top_srcdir)/elink/scripts/xilinx/run.tcl
vivado -mode batch -source $(top_srcdir)/elink/projects/xilinx/run.tcl
clean:
find . \( -name "vivado*.log" -or -name "vivado*.jou" \) -delete

6
elink/projects/xilinx/package_axi_elink.tcl
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@ -14,9 +14,9 @@ set elink_src_files [list \
"$top_srcdir/emailbox/hdl/emailbox.v" \
"$top_srcdir/elink/hdl" ]
set elink_constr_files [list \
"$top_srcdir/elink/scripts/xilinx/elink_clocks.xdc" \
"$top_srcdir/elink/scripts/xilinx/elink_pins.xdc" \
"$top_srcdir/elink/scripts/xilinx/elink_timing.xdc" ]
"$top_srcdir/elink/projects/xilinx/elink_clocks.xdc" \
"$top_srcdir/elink/projects/xilinx/elink_pins.xdc" \
"$top_srcdir/elink/projects/xilinx/elink_timing.xdc" ]
set elink_ip_files [concat $elink_src_files $elink_constr_files]
oh::ip::add_files axi_elink $elink_ip_files

2
elink/projects/xilinx/read_verilog.tcl
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@ -13,6 +13,7 @@ read_verilog $top_srcdir/elink/hdl/ereset.v
read_verilog $top_srcdir/elink/hdl/ecfg_elink.v
read_verilog $top_srcdir/elink/hdl/ecfg_if.v
read_verilog $top_srcdir/elink/hdl/erx.v
read_verilog $top_srcdir/elink/hdl/erx_clocks.v
read_verilog $top_srcdir/elink/hdl/erx_core.v
read_verilog $top_srcdir/elink/hdl/erx_fifo.v
read_verilog $top_srcdir/elink/hdl/erx_cfg.v
@ -22,6 +23,7 @@ read_verilog $top_srcdir/elink/hdl/erx_remap.v
read_verilog $top_srcdir/elink/hdl/erx_io.v
read_verilog $top_srcdir/elink/hdl/etx.v
read_verilog $top_srcdir/elink/hdl/etx_core.v
read_verilog $top_srcdir/elink/hdl/etx_clocks.v
read_verilog $top_srcdir/elink/hdl/etx_fifo.v
read_verilog $top_srcdir/elink/hdl/etx_cfg.v
read_verilog $top_srcdir/elink/hdl/etx_arbiter.v