Merge branch 'master' of https://github.com/parallella/oh

common/hdl/oh_arbiter.v

@@ -24,7 +24,7 @@ module oh_arbiter(/*AUTOARG*/
    genvar 	  j;     
    generate       
       if(TYPE=="FIXED")
-	begin
+	begin : arbiter_fixed
 	   assign waitmask[0]   = 1'b0;      
 	   for (j=N-1; j>=1; j=j-1) 
 	     begin : gen_arbiter     

common/hdl/oh_datagate.v

@@ -14,7 +14,8 @@ module oh_datagate (/*AUTOARG*/
    output [DW-1:0] dout;	  
 	 
    reg [PS-1:0]    enable_pipe;   
-
+   wire 	   enable;
+   
    always @ (posedge clk)
      enable_pipe[PS-1:0] <= {enable_pipe[PS-2:0],en};
    
@@ -22,5 +23,5 @@ module oh_datagate (/*AUTOARG*/
 
    assign dout[DW-1:0] =  {(DW){enable}} & din[DW-1:0];
    
-   
+  
 endmodule // oh_datagate

common/hdl/oh_mux4.v

@@ -33,8 +33,10 @@ module oh_mux4(/*AUTOARG*/
    assign error = (sel0 | sel1 | sel2 | sel3) &
    		  ~(sel0 ^ sel1 ^ sel2 ^ sel3);
 
+`ifdef TARGET_SIM
    always @ (posedge error)
      $display ("ERROR at in oh_mux4 %m at ",$time);
+`endif
    			
 endmodule // oh_mux4
 

common/hdl/oh_rsync.v

@@ -23,12 +23,15 @@ module oh_rsync (/*AUTOARG*/
    
    genvar 	i;
    genvar 	j;   
+
+   //TODO: simplify logic
    generate          
       for(i=0;i<PS;i=i+1)
+	begin : stage
 	if(i==0)
 	  begin : first_stage
 	     for(j=0;j<DW;j=j+1)		 
-	       begin
+	       begin : first_stage_in
 		  always @ (posedge clk or negedge nrst_in[j])		 
 		    if(!nrst_in[j])
 		      sync_pipe[0][j] <= 1'b0;
@@ -39,7 +42,7 @@ module oh_rsync (/*AUTOARG*/
 	else
 	  begin : second_stage
 	     for(j=0;j<DW;j=j+1)		 
-	       begin
+	       begin : second_stage_in
 		  always @ (posedge clk or negedge nrst_in[j])		 
 		    if(!nrst_in[j])
 		      sync_pipe[i][j] <= 1'b0;
@@ -47,6 +50,7 @@ module oh_rsync (/*AUTOARG*/
 		      sync_pipe[i][j] <=  sync_pipe[i-1][j]; 
 	       end
 	  end	  	 
+	end
    endgenerate
    
    assign nrst_out[DW-1:0] = sync_pipe[PS-1][DW-1:0];

emesh/hdl/emesh2packet.v

@@ -46,7 +46,7 @@ module emesh2packet(/*AUTOARG*/
      
    generate   
       if(AW==64)
-	begin
+	begin : packet64
 	   assign packet_out[39:8]    = dstaddr_out[AW/2-1:0];
 	   assign packet_out[71:40]   = data_out[AW/2-1:0];
 	   assign packet_out[103:72]  = srcaddr_out[AW/2-1:0];   
@@ -54,7 +54,7 @@ module emesh2packet(/*AUTOARG*/
 	   assign packet_out[167:136] = dstaddr_out[AW-1:AW/2];
 	end
       else
-	begin	  
+	begin : packet32
 	   assign packet_out[39:8]    = dstaddr_out[AW-1:0];
 	   assign packet_out[71:40]   = data_out[AW-1:0];
 	   assign packet_out[103:72]  = srcaddr_out[AW-1:0];

emesh/hdl/emesh_mux.v

@@ -41,7 +41,7 @@ module emesh_mux (/*AUTOARG*/
    //arbiter
    generate
       if(CFG=="STATIC")		
-	begin
+	begin : arbiter_static
 	   oh_arbiter #(.N(N))
 	   arbiter(// Outputs
 		   .grants   (grants[N-1:0]),
@@ -50,9 +50,11 @@ module emesh_mux (/*AUTOARG*/
 		   );      
 	end
       else if (CFG=="DYNAMIC")
-	begin
+	begin : arbiter_dynamic
+`ifdef TARGET_SIM
 	   initial
 	     $display("ROUND ROBIN ARBITER NOT IMPLEMENTED\n");	   
+`endif
 	end
    endgenerate
    

emesh/hdl/packet2emesh.v

@@ -62,8 +62,10 @@ module packet2emesh(/*AUTOARG*/
 	end
       else
 	begin : unknown
+`ifdef TARGET_SIM
 	   initial
 	     $display ("packet width=%ds not supported",  PW);
+`endif
 	end
    endgenerate