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Merge branch 'master' of https://github.com/parallella/oh

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This commit is contained in:
Andreas Olofsson 2016-02-13 14:17:24 -05:00
commit 317b0bb7b4
7 changed files with 20 additions and 9 deletions
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2
common/hdl/oh_arbiter.v
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@ -24,7 +24,7 @@ module oh_arbiter(/*AUTOARG*/
genvar j; genvar j;
generate generate
if(TYPE=="FIXED") if(TYPE=="FIXED")
begin begin : arbiter_fixed
assign waitmask[0] = 1'b0; assign waitmask[0] = 1'b0;
for (j=N-1; j>=1; j=j-1) for (j=N-1; j>=1; j=j-1)
begin : gen_arbiter begin : gen_arbiter

5
common/hdl/oh_datagate.v
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@ -14,7 +14,8 @@ module oh_datagate (/*AUTOARG*/
output [DW-1:0] dout; output [DW-1:0] dout;
reg [PS-1:0] enable_pipe; reg [PS-1:0] enable_pipe;
wire enable;
always @ (posedge clk) always @ (posedge clk)
enable_pipe[PS-1:0] <= {enable_pipe[PS-2:0],en}; enable_pipe[PS-1:0] <= {enable_pipe[PS-2:0],en};
@ -22,5 +23,5 @@ module oh_datagate (/*AUTOARG*/
assign dout[DW-1:0] = {(DW){enable}} & din[DW-1:0]; assign dout[DW-1:0] = {(DW){enable}} & din[DW-1:0];
endmodule // oh_datagate endmodule // oh_datagate

2
common/hdl/oh_mux4.v
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@ -33,8 +33,10 @@ module oh_mux4(/*AUTOARG*/
assign error = (sel0 | sel1 | sel2 | sel3) & assign error = (sel0 | sel1 | sel2 | sel3) &
~(sel0 ^ sel1 ^ sel2 ^ sel3); ~(sel0 ^ sel1 ^ sel2 ^ sel3);
`ifdef TARGET_SIM
always @ (posedge error) always @ (posedge error)
$display ("ERROR at in oh_mux4 %m at ",$time); $display ("ERROR at in oh_mux4 %m at ",$time);
`endif
endmodule // oh_mux4 endmodule // oh_mux4

8
common/hdl/oh_rsync.v
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@ -23,12 +23,15 @@ module oh_rsync (/*AUTOARG*/
genvar i; genvar i;
genvar j; genvar j;
//TODO: simplify logic
generate generate
for(i=0;i<PS;i=i+1) for(i=0;i<PS;i=i+1)
begin : stage
if(i==0) if(i==0)
begin : first_stage begin : first_stage
for(j=0;j<DW;j=j+1) for(j=0;j<DW;j=j+1)
begin begin : first_stage_in
always @ (posedge clk or negedge nrst_in[j]) always @ (posedge clk or negedge nrst_in[j])
if(!nrst_in[j]) if(!nrst_in[j])
sync_pipe[0][j] <= 1'b0; sync_pipe[0][j] <= 1'b0;
@ -39,7 +42,7 @@ module oh_rsync (/*AUTOARG*/
else else
begin : second_stage begin : second_stage
for(j=0;j<DW;j=j+1) for(j=0;j<DW;j=j+1)
begin begin : second_stage_in
always @ (posedge clk or negedge nrst_in[j]) always @ (posedge clk or negedge nrst_in[j])
if(!nrst_in[j]) if(!nrst_in[j])
sync_pipe[i][j] <= 1'b0; sync_pipe[i][j] <= 1'b0;
@ -47,6 +50,7 @@ module oh_rsync (/*AUTOARG*/
sync_pipe[i][j] <= sync_pipe[i-1][j]; sync_pipe[i][j] <= sync_pipe[i-1][j];
end end
end end
end
endgenerate endgenerate
assign nrst_out[DW-1:0] = sync_pipe[PS-1][DW-1:0]; assign nrst_out[DW-1:0] = sync_pipe[PS-1][DW-1:0];

4
emesh/hdl/emesh2packet.v
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@ -46,7 +46,7 @@ module emesh2packet(/*AUTOARG*/
generate generate
if(AW==64) if(AW==64)
begin begin : packet64
assign packet_out[39:8] = dstaddr_out[AW/2-1:0]; assign packet_out[39:8] = dstaddr_out[AW/2-1:0];
assign packet_out[71:40] = data_out[AW/2-1:0]; assign packet_out[71:40] = data_out[AW/2-1:0];
assign packet_out[103:72] = srcaddr_out[AW/2-1:0]; assign packet_out[103:72] = srcaddr_out[AW/2-1:0];
@ -54,7 +54,7 @@ module emesh2packet(/*AUTOARG*/
assign packet_out[167:136] = dstaddr_out[AW-1:AW/2]; assign packet_out[167:136] = dstaddr_out[AW-1:AW/2];
end end
else else
begin begin : packet32
assign packet_out[39:8] = dstaddr_out[AW-1:0]; assign packet_out[39:8] = dstaddr_out[AW-1:0];
assign packet_out[71:40] = data_out[AW-1:0]; assign packet_out[71:40] = data_out[AW-1:0];
assign packet_out[103:72] = srcaddr_out[AW-1:0]; assign packet_out[103:72] = srcaddr_out[AW-1:0];

6
emesh/hdl/emesh_mux.v
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@ -41,7 +41,7 @@ module emesh_mux (/*AUTOARG*/
//arbiter //arbiter
generate generate
if(CFG=="STATIC") if(CFG=="STATIC")
begin begin : arbiter_static
oh_arbiter #(.N(N)) oh_arbiter #(.N(N))
arbiter(// Outputs arbiter(// Outputs
.grants (grants[N-1:0]), .grants (grants[N-1:0]),
@ -50,9 +50,11 @@ module emesh_mux (/*AUTOARG*/
); );
end end
else if (CFG=="DYNAMIC") else if (CFG=="DYNAMIC")
begin begin : arbiter_dynamic
`ifdef TARGET_SIM
initial initial
$display("ROUND ROBIN ARBITER NOT IMPLEMENTED\n"); $display("ROUND ROBIN ARBITER NOT IMPLEMENTED\n");
`endif
end end
endgenerate endgenerate

2
emesh/hdl/packet2emesh.v
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@ -62,8 +62,10 @@ module packet2emesh(/*AUTOARG*/
end end
else else
begin : unknown begin : unknown
`ifdef TARGET_SIM
initial initial
$display ("packet width=%ds not supported", PW); $display ("packet width=%ds not supported", PW);
`endif
end end
endgenerate endgenerate