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Cleanup

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This commit is contained in:
Andreas Olofsson 2016-01-10 15:58:28 -05:00
parent 5f16bd672e
commit 32522280e6
12 changed files with 93 additions and 461 deletions
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50
axi/hdl/esaxi.v
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@ -15,12 +15,12 @@ module esaxi (/*autoarg*/
s_axi_wstrb, s_axi_wvalid
);
parameter ID = 12'h999;
parameter S_IDW = 12;
parameter PW = 104;
parameter [15:0] RETURN_ADDR = {ID,`EGROUP_RR};
parameter AW = 32;
parameter DW = 32;
parameter ID = 12'h999;
parameter S_IDW = 12;
parameter PW = 104;
parameter [AW-1:0] RETURN_ADDR = {ID,20'h0};
parameter AW = 32;
parameter DW = 32;
`ifdef TARGET_SIM
parameter TW = 8; //timeout counter width
@ -172,12 +172,12 @@ module esaxi (/*autoarg*/
// Outputs
.packet_out (txwr_packet[PW-1:0]),
// Inputs
.write_in (1'b1),
.datamode_in (txwr_datamode[1:0]),
.ctrlmode_in (4'b0),
.dstaddr_in (txwr_dstaddr[AW-1:0]),
.data_in (txwr_data[DW-1:0]),
.srcaddr_in (32'b0)//only 32b slave write supported
.write_out (1'b1),
.datamode_out (txwr_datamode[1:0]),
.ctrlmode_out (5'b0),
.dstaddr_out (txwr_dstaddr[AW-1:0]),
.data_out (txwr_data[DW-1:0]),
.srcaddr_out (32'b0)//only 32b slave write supported
);
//TXRD
@ -185,22 +185,22 @@ module esaxi (/*autoarg*/
// Outputs
.packet_out (txrd_packet[PW-1:0]),
// Inputs
.write_in (1'b0),
.datamode_in (txrd_datamode[1:0]),
.ctrlmode_in (4'b0),
.dstaddr_in (txrd_dstaddr[AW-1:0]),
.data_in (32'b0),
.srcaddr_in (txrd_srcaddr[AW-1:0])
.write_out (1'b0),
.datamode_out (txrd_datamode[1:0]),
.ctrlmode_out (5'b0),
.dstaddr_out (txrd_dstaddr[AW-1:0]),
.data_out (32'b0),
.srcaddr_out (txrd_srcaddr[AW-1:0])
);
//RXRR
packet2emesh p2e_rxrr (
// Outputs
.write_out (),
.datamode_out (),
.ctrlmode_out (),
.dstaddr_out (),
.data_out (rxrr_data[DW-1:0]),
.srcaddr_out (),
.write_in (),
.datamode_in (),
.ctrlmode_in (),
.dstaddr_in (),
.data_in (rxrr_data[DW-1:0]),
.srcaddr_in (),
// Inputs
.packet_in (rxrr_packet[PW-1:0])
);
@ -446,7 +446,7 @@ module esaxi (/*autoarg*/
txrd_access <= ( ~ractive_reg & read_active ) | rnext;
txrd_datamode[1:0] <= axi_arsize[1:0];
txrd_dstaddr[31:0] <= axi_araddr[31:0];
txrd_srcaddr[31:0] <= {RETURN_ADDR, 16'd0};
txrd_srcaddr[31:0] <= RETURN_ADDR;
//TODO: use arid+srcaddr for out of order ?
end

24
common/dv/dv_ctrl.v
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@ -7,7 +7,7 @@ module dv_ctrl(/*AUTOARG*/
parameter CLK_PERIOD = 10;
parameter CLK_PHASE = CLK_PERIOD/2;
parameter TIMEOUT = 100000;
parameter TIMEOUT = 1000;
output nreset; // async active low reset
output clk; // main clock
@ -22,39 +22,37 @@ module dv_ctrl(/*AUTOARG*/
reg clk = 1'b0;
reg start;
//init
//RESET
initial
begin
#(CLK_PERIOD*20) //hold reset for 20 cycles
nreset = 'b1;
nreset = 'b1;
end
//START TEST
always @ (posedge clk or negedge nreset)
if(!nreset)
start = 1'b0;
else if(dut_active)
start = 1'b1;
//STOP SIMULATION
always @ (posedge clk)
if(stim_done & test_done)
#(TIMEOUT) $finish;
//Clock generator
//CLOCK GENERATOR
always
#(CLK_PHASE) clk = ~clk;
//Waveform dump
//WAVEFORM DUMP
//Better solution?
`ifdef NOVCD
`else
initial
begin
$dumpfile("waveform.vcd");
$dumpvars(0, dv_top);
$dumpfile("waveform.vcd");
//$dumpvars(0, dv_top);
end
`endif
endmodule // dv_ctrl

0
common/hdl/oh_8b10b_dec.v → common/hdl/oh_8b10b_decoder.v
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3
common/hdl/oh_8b10b_enc.v
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@ -1,3 +0,0 @@
module oh_pll (/*AUTOINST*/);
endmodule // oh_pll

25
common/hdl/oh_8b10b_encoder.v Normal file
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@ -0,0 +1,25 @@
module oh_8b10b_enc (/*AUTOARG*/
// Outputs
data_out,
// Inputs
clk, nreset, data_in
);
//#####################################################################
//# INTERFACE
//#####################################################################
//clk/reset
input clk;
input nreset;
//Data
input data_in[7:0];
output data_out[9:0];
endmodule // oh_8b10b_enc

169
common/hdl/oh_csa34to2.v
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@ -1,169 +0,0 @@
//CSA34:2 Compressor
module oh_csa34to2 (/*AUTOARG*/
// Outputs
s, c, cout0, cout1, cout2, cout3, cout4, cout5, cout6, cout7,
cout8, cout9, cout10, cout11, cout12, cout13, cout14, cout15,
cout16, cout17, cout18, cout19, cout20, cout21, cout22, cout23,
cout24, cout25, cout26, cout27, cout28, cout29, cout30,
// Inputs
in0, in1, in2, in3, in4, in5, in6, in7, in8, in9, in10, in11, in12,
in13, in14, in15, in16, in17, in18, in19, in20, in21, in22, in23,
in24, in25, in26, in27, in28, in29, in30, in31, in32, in33, cin0,
cin1, cin2, cin3, cin4, cin5, cin6, cin7, cin8, cin9, cin10, cin11,
cin12, cin13, cin14, cin15, cin16, cin17, cin18, cin19, cin20,
cin21, cin22, cin23, cin24, cin25, cin26, cin27, cin28, cin29,
cin30
);
input in0;
input in1;
input in2;
input in3;
input in4;
input in5;
input in6;
input in7;
input in8;
input in9;
input in10;
input in11;
input in12;
input in13;
input in14;
input in15;
input in16;
input in17;
input in18;
input in19;
input in20;
input in21;
input in22;
input in23;
input in24;
input in25;
input in26;
input in27;
input in28;
input in29;
input in30;
input in31;
input in32;
input in33;
input cin0;
input cin1;
input cin2;
input cin3;
input cin4;
input cin5;
input cin6;
input cin7;
input cin8;
input cin9;
input cin10;
input cin11;
input cin12;
input cin13;
input cin14;
input cin15;
input cin16;
input cin17;
input cin18;
input cin19;
input cin20;
input cin21;
input cin22;
input cin23;
input cin24;
input cin25;
input cin26;
input cin27;
input cin28;
input cin29;
input cin30;
output s;
output c;
output cout0;
output cout1;
output cout2;
output cout3;
output cout4;
output cout5;
output cout6;
output cout7;
output cout8;
output cout9;
output cout10;
output cout11;
output cout12;
output cout13;
output cout14;
output cout15;
output cout16;
output cout17;
output cout18;
output cout19;
output cout20;
output cout21;
output cout22;
output cout23;
output cout24;
output cout25;
output cout26;
output cout27;
output cout28;
output cout29;
output cout30;
wire s_int0;
wire s_int1;
wire s_int2;
wire s_int3;
oh_csa92 csa92_00 (.in0(in0), .in1(in1), .in2(in2),
.in3(in3), .in4(in4), .in5(in5),
.in6(in6), .in7(in7), .in8(in8),
.cin0(cin0), .cin1(cin1), .cin2(cin2),
.cin3(cin3), .cin4(cin4), .cin5(cin5),
.cout0(cout0),.cout1(cout1),.cout2(cout2),
.cout3(cout3),.cout4(cout4),.cout5(cout5),
.c(cout21), .s(s_int0));
oh_csa92 csa92_01 (.in0(in9), .in1(in10), .in2(in11),
.in3(in12), .in4(in13), .in5(in14),
.in6(in15), .in7(in16), .in8(in17),
.cin0(cin6), .cin1(cin7), .cin2(cin8),
.cin3(cin9), .cin4(cin10), .cin5(cin11),
.cout0(cout6),.cout1(cout7), .cout2(cout8),
.cout3(cout9),.cout4(cout10),.cout5(cout11),
.c(cout22), .s(s_int1));
oh_csa92 csa92_02 (.in0(in18), .in1(in19), .in2(in20),
.in3(in21), .in4(in22), .in5(in23),
.in6(in24), .in7(in25), .in8(in26),
.cin0(cin12), .cin1(cin13), .cin2(cin14),
.cin3(cin15), .cin4(cin16), .cin5(cin17),
.cout0(cout12),.cout1(cout13),.cout2(cout14),
.cout3(cout15),.cout4(cout16),.cout5(cout17),
.c(cout23), .s(s_int2));
oh_csa62 csa62_03 (.in0(in27), .in1(in28), .in2(in29),
.in3(in30), .in4(in31), .in5(in32),
.cin0(cin18), .cin1(cin19), .cin2(cin20),
.cout0(cout18),.cout1(cout19),.cout2(cout20),
.c(cout24),.s(s_int3));
oh_csa92 csa92_10 (.in0(in33), .in1(s_int0), .in2(s_int1),
.in3(s_int2), .in4(s_int3), .in5(cin21),
.in6(cin22), .in7(cin23), .in8(cin24),
.cin0(cin25), .cin1(cin26), .cin2(cin27),
.cin3(cin28), .cin4(cin29), .cin5(cin30),
.cout0(cout25),.cout1(cout26),.cout2(cout27),
.cout3(cout28),.cout4(cout29),.cout5(cout30),
.c(c), .s(s));
endmodule // oh_csa34to2

5
common/hdl/oh_ecc_write.v
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@ -1,5 +0,0 @@
module oh_ecc_write (/*AUTOARG*/);
endmodule // oh_ecc_write

11
common/hdl/oh_hamming_encoder.v Normal file
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@ -0,0 +1,11 @@
module oh_hamming_enc (/*AUTOARG*/
// Outputs
out,
// Inputs
in, reset
);
endmodule // oh_hamming_enc

17
elink/hdl/ecfg_if.v
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@ -1,8 +1,3 @@
/*
########################################################################
########################################################################
*/
`include "elink_regmap.v"
module ecfg_if (/*AUTOARG*/
// Outputs
@ -76,7 +71,7 @@ module ecfg_if (/*AUTOARG*/
wire [31:0] data_out;
wire write;
wire mi_match;
wire mi_rx_en;
wire mi_rx_sel;
//parameter didn't seem to work
//this module used in rx and tx, parameter used to make address decode work out
@ -121,7 +116,7 @@ module ecfg_if (/*AUTOARG*/
assign mi_we = write & mi_en;
//signal to carry transaction from ETX to ERX block through fifo_cdc
assign mi_rx_en = mi_match &
assign mi_rx_sel = mi_match &
~mi_en &
((dstaddr[19:16]==`EGROUP_RR) |
(dstaddr[19:16]==`EGROUP_MMR) |
@ -143,7 +138,7 @@ module ecfg_if (/*AUTOARG*/
//Access out packet
assign access_forward = (mi_rx_en | mi_rd);
assign access_forward = (mi_rx_sel | mi_rd);
always @ (posedge clk or negedge nreset)
if(!nreset)
@ -155,12 +150,12 @@ module ecfg_if (/*AUTOARG*/
if(~wait_in)
begin
readback_reg <= mi_rd;
write_reg <= (mi_rx_en & write) | mi_rd;
write_reg <= (mi_rx_sel & write) | mi_rd;
datamode_reg[1:0] <= datamode[1:0];
ctrlmode_reg[3:0] <= ctrlmode[3:0];
dstaddr_reg[31:0] <= mi_rx_en ? dstaddr[31:0] : srcaddr[31:0];
dstaddr_reg[31:0] <= mi_rx_sel ? dstaddr[31:0] : srcaddr[31:0];
data_reg[31:0] <= data[31:0];
srcaddr_reg[31:0] <= mi_rx_en ? srcaddr[31:0] : mi_dout_mux[63:32];
srcaddr_reg[31:0] <= mi_rx_sel ? srcaddr[31:0] : mi_dout_mux[63:32];
end
assign data_out[31:0] = readback_reg ? mi_dout_mux[31:0] : data_reg[31:0];

31
emailbox/hdl/emailbox.v
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@ -65,22 +65,19 @@ module emailbox (/*AUTOARG*/
/*****************************/
/*REGISTERS */
/*****************************/
reg mi_rd_reg;
reg [RFAW+1:2] mi_addr_reg;
reg read_hi;
reg read_status;
/*****************************/
/*WIRES */
/*****************************/
wire mi_rd;
wire [31:0] emesh_addr;
wire [63:0] emesh_din;
wire emesh_write;
wire mailbox_read;
wire mailbox_write;
wire [MW-1:0] mailbox_data;
wire mailbox_empty;
reg mi_rd_reg;
reg [RFAW+1:2] mi_addr_reg;
reg read_hi;
reg read_status;
wire mi_rd;
wire [31:0] emesh_addr;
wire [63:0] emesh_din;
wire emesh_write;
wire mailbox_read;
wire mailbox_write;
wire [MW-1:0] mailbox_data;
wire mailbox_empty;
/*****************************/
/*WRITE TO FIFO */
/*****************************/
@ -113,9 +110,11 @@ module emailbox (/*AUTOARG*/
read_hi <= mi_rd & (mi_addr[RFAW+1:2]==`E_MAILBOXHI);
read_status <= mi_rd & (mi_addr[RFAW+1:2]==`E_MAILBOXSTAT);
end
assign mi_dout[31:0] = read_status ? {30'b0,mailbox_full, mailbox_not_empty} :
read_hi ? mailbox_data[63:32] :
mailbox_data[31:0];
assign mi_dout[63:32] = mailbox_data[63:32];
/*****************************/

219
emesh/dv/ememory.v
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@ -1,219 +0,0 @@
module ememory(/*AUTOARG*/
// Outputs
wait_out, access_out, packet_out,
// Inputs
clk, nreset, coreid, access_in, packet_in, wait_in
);
parameter PW = 104;
parameter IDW = 12;
parameter DW = 32;
parameter AW = 32;
parameter DEPTH = 65536;
parameter MAW = $clog2(DEPTH);
parameter NAME = "emem";
parameter WAIT = 0; //turns on random wait circuit
//Basic Interface
input clk;
input nreset;
input [IDW-1:0] coreid;
//incoming read/write
input access_in;
input [PW-1:0] packet_in;
output wait_out; //pushback
//back to mesh (readback data)
output access_out;
output [PW-1:0] packet_out;
input wait_in; //pushback
wire [MAW-1:0] addr;
wire [63:0] din;
wire [63:0] dout;
wire en;
wire mem_rd;
reg [7:0] wen;
//State
reg access_out;
reg write_out;
reg [1:0] datamode_out;
reg [4:0] ctrlmode_out;
reg [AW-1:0] dstaddr_out;
wire [AW-1:0] srcaddr_out;
wire [AW-1:0] data_out;
reg [2:0] align_addr;
wire write_in;
wire [1:0] datamode_in;
wire [3:0] ctrlmode_in;
wire [AW-1:0] dstaddr_in;
wire [DW-1:0] data_in;
wire [AW-1:0] srcaddr_in;
wire [DW-1:0] din_aligned;
wire [DW-1:0] dout_aligned;
wire wait_random; //TODO: make random
wire wait_all;
packet2emesh #(.PW(PW))
p2e (
.write_out (write_in),
.datamode_out (datamode_in[1:0] ),
.ctrlmode_out (ctrlmode_in[3:0]),
.dstaddr_out (dstaddr_in[AW-1:0]),
.data_out (data_in[DW-1:0]),
.srcaddr_out (srcaddr_in[AW-1:0]),
.packet_in (packet_in[PW-1:0])
);
//Access-in
assign en = access_in & ~wait_all & ~wait_all;
assign mem_rd = (access_in & ~write_in & ~wait_all);
//Pushback Circuit (pass through problems?)
assign wait_all = (wait_random | wait_in);
assign wait_out = wait_all;// & access_in
//Address-in (shifted by three bits, 64 bit wide memory)
assign addr[MAW-1:0] = dstaddr_in[MAW+2:3];
//Shift up
assign din_aligned[DW-1:0] = (datamode_in[1:0]==2'b00) ? {(4){data_in[7:0]}} :
(datamode_in[1:0]==2'b01) ? {(2){data_in[15:0]}} :
data_in[31:0];
//Data-in (hardoded width)
assign din[63:0] =(datamode_in[1:0]==2'b11) ? {srcaddr_in[31:0],din_aligned[31:0]}:
{din_aligned[31:0],din_aligned[31:0]};
//Write mask
always@*
casez({write_in, datamode_in[1:0],dstaddr_in[2:0]})
//Byte
6'b100000 : wen[7:0] = 8'b00000001;
6'b100001 : wen[7:0] = 8'b00000010;
6'b100010 : wen[7:0] = 8'b00000100;
6'b100011 : wen[7:0] = 8'b00001000;
6'b100100 : wen[7:0] = 8'b00010000;
6'b100101 : wen[7:0] = 8'b00100000;
6'b100110 : wen[7:0] = 8'b01000000;
6'b100111 : wen[7:0] = 8'b10000000;
//Short
6'b10100? : wen[7:0] = 8'b00000011;
6'b10101? : wen[7:0] = 8'b00001100;
6'b10110? : wen[7:0] = 8'b00110000;
6'b10111? : wen[7:0] = 8'b11000000;
//Word
6'b1100?? : wen[7:0] = 8'b00001111;
6'b1101?? : wen[7:0] = 8'b11110000;
//Double
6'b111??? : wen[7:0] = 8'b11111111;
default : wen[7:0] = 8'b00000000;
endcase // casez ({write, datamode_in[1:0],addr_in[2:0]})
//Single ported memory
defparam mem.DW=2*DW;
defparam mem.DEPTH=DEPTH;
oh_memory_sp mem(
// Inputs
.clk (clk),
.en (en),
.we (write_in),
.wem ({
{(8){wen[7]}},
{(8){wen[6]}},
{(8){wen[5]}},
{(8){wen[4]}},
{(8){wen[3]}},
{(8){wen[2]}},
{(8){wen[1]}},
{(8){wen[0]}}
}
),
.addr (addr[MAW-1:0]),
.din (din[63:0]),
.dout (dout[63:0])
);
//Outgoing transaction
always @ (posedge clk or negedge nreset)
if(!nreset)
access_out <=1'b0;
else
begin
access_out <= mem_rd;
write_out <= 1'b1;
align_addr[2:0] <= dstaddr_in[2:0];
datamode_out[1:0] <= datamode_in[1:0];
ctrlmode_out[4:0] <= ctrlmode_in[3:0];
dstaddr_out[AW-1:0] <= srcaddr_in[AW-1:0];
end
//Data alignment for readback
emesh_rdalign emesh_rdalign (// Outputs
.data_out (dout_aligned[DW-1:0]),
// Inputs
.datamode (datamode_out[1:0]),
.addr (align_addr[2:0]),
.data_in (dout[2*DW-1:0]));
assign srcaddr_out[AW-1:0] = (datamode_out[1:0]==2'b11) ? dout[63:32] : 32'b0;
assign data_out[DW-1:0] = dout_aligned[31:0];
//Concatenate
emesh2packet #(.PW(PW))
e2p (.packet_out (packet_out[PW-1:0]),
.write_in (write_out),
.datamode_in (datamode_out[1:0]),
.ctrlmode_in (ctrlmode_out[3:0]),
.dstaddr_in (dstaddr_out[AW-1:0]),
.data_in (data_out[DW-1:0]),
.srcaddr_in (srcaddr_out[AW-1:0])
);
//Write monitor
emesh_monitor
#(.PW(PW),
.INDEX(1),
.NAME(NAME)
)
emesh_monitor (.dut_access (access_in & write_in),
.dut_packet (packet_in[PW-1:0]),
.wait_in (wait_random),
/*AUTOINST*/
// Inputs
.clk (clk),
.nreset (nreset),
.coreid (coreid[IDW-1:0]));
//Random wait generator
//TODO: make this a module
generate
if(WAIT)
begin
reg [8:0] wait_counter;
always @ (posedge clk or negedge nreset)
if(!nreset)
wait_counter[8:0] <= 'b0;
else
wait_counter[8:0] <= wait_counter+1'b1;
assign wait_random = (|wait_counter[5:0]);//(|wait_counter[3:0]);//1'b0;
end
else
begin
assign wait_random = 1'b0;
end // else: !if(WAIT)
endgenerate
endmodule // emesh_memory
// Local Variables:
// verilog-library-directories:("." "../hdl" )
// End:

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