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Instance renaming
Will help with FPGA synthesis reports (uniqueness needed sometimes)
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@ -149,9 +149,40 @@ has the following bit ordering.
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srcaddr[31:0] | [103:72]| Return address for read-request, upper data for write
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srcaddr[31:0] | [103:72]| Return address for read-request, upper data for write
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###INTERNAL STRUCTURE
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###INTERNAL STRUCTURE
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```
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elink
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|----ereset
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|----ecfg_clocks
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|----eclocks
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|----ecfg_cdc
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|----erx
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| |----erx_io (chip level I/O interface
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| |----erx_protocol (elink protocol-->emesh packet converter)
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| |----erx_remap (simple dstaddr remapping)
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| |----erx_mmu (advanced dstaddr mapping)
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| |----erx_cfgif (configuration interface)
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| |----erx_cfg (basic rx config registers)
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| |----erx_mailbox (fifo mailbox)
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| |----erx_dma (DMA master)
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| |----erx_disty (sends rx transaction to WR/RD/RR fifo)
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| |----rxwr_fifo (write fifo)
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| |----rxrd_fifo (read request fifo)
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| |----rxrr_fifo (read response fifo)
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|----etx
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| |----etx_io (chip level I/O interface)
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| |----etx_protocol (emesh-->elink protocol converter)
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| |----etx_remap (simple dstaddr remapping)
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| |----etx_mmu (advanced dstaddr mapping)
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| |----etx_cfgif (configuration interface)
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| |----etx_cfg (basic rx config registers)
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| |----etx_dma (DMA master)
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| |----etx_arbiter (sends rx transaction to WR/RD/RR fifo)
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| |----txwr_fifo (write fifo)
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| |----txrd_fifo (read request fifo)
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| |----txrr_fifo (read response fifo)
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|--------------------------------------------------------------------
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```
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(link to picture)
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###REGISTER MAP
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###REGISTER MAP
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The full 32 bit physical address of an elink register is the address seen below
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The full 32 bit physical address of an elink register is the address seen below
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@ -268,7 +268,7 @@ module elink(/*AUTOARG*/
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.reset (elink_reset),
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.reset (elink_reset),
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);
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);
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*/
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*/
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fifo_cdc fifo_cdc (/*AUTOINST*/
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fifo_cdc ecfg_cdc (/*AUTOINST*/
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// Outputs
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// Outputs
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.wait_in (etx_cfg_wait), // Templated
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.wait_in (etx_cfg_wait), // Templated
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.access_out (erx_cfg_access), // Templated
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.access_out (erx_cfg_access), // Templated
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@ -205,7 +205,7 @@ module erx (/*AUTOARG*/
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);
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);
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*/
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*/
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emmu emmu (
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emmu erx_mmu (
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/*AUTOINST*/
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/*AUTOINST*/
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// Outputs
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// Outputs
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.mi_dout (mi_mmu_dout[DW-1:0]), // Templated
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.mi_dout (mi_mmu_dout[DW-1:0]), // Templated
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@ -241,8 +241,8 @@ module erx (/*AUTOARG*/
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);
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);
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*/
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*/
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defparam ecfg_if.RX=1;
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defparam erx_cfgif.RX=1;
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ecfg_if ecfg_if (/*AUTOINST*/
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ecfg_if erx_cfgif (/*AUTOINST*/
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// Outputs
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// Outputs
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.wait_out (), // Templated
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.wait_out (), // Templated
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.mi_mmu_en (mi_mmu_en),
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.mi_mmu_en (mi_mmu_en),
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@ -293,7 +293,7 @@ module erx (/*AUTOARG*/
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ecfg_rx ecfg_rx (.rx_status (rx_status[15:0]),
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ecfg_rx erx_cfg (.rx_status (rx_status[15:0]),
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.timer_cfg (),
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.timer_cfg (),
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/*AUTOINST*/
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/*AUTOINST*/
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// Outputs
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// Outputs
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@ -329,7 +329,7 @@ module erx (/*AUTOARG*/
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*/
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*/
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//shares register space with ecfg_rx
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//shares register space with ecfg_rx
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emailbox emailbox(.mi_en (mi_cfg_en),
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emailbox erx_mailbox(.mi_en (mi_cfg_en),
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/*AUTOINST*/
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/*AUTOINST*/
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// Outputs
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// Outputs
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.mi_dout (mi_mailbox_dout[31:0]), // Templated
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.mi_dout (mi_mailbox_dout[31:0]), // Templated
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@ -355,7 +355,7 @@ module erx (/*AUTOARG*/
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);
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);
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*/
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*/
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edma edma(/*AUTOINST*/
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edma erx_dma(/*AUTOINST*/
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// Outputs
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// Outputs
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.mi_dout (mi_dma_dout[DW-1:0]), // Templated
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.mi_dout (mi_dma_dout[DW-1:0]), // Templated
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.edma_access (edma_access), // Templated
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.edma_access (edma_access), // Templated
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@ -209,7 +209,7 @@ module etx(/*AUTOARG*/
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);
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);
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*/
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*/
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edma edma (/*AUTOINST*/
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edma etx_dma (/*AUTOINST*/
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// Outputs
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// Outputs
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.mi_dout (mi_dma_dout[DW-1:0]), // Templated
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.mi_dout (mi_dma_dout[DW-1:0]), // Templated
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.edma_access (edma_access), // Templated
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.edma_access (edma_access), // Templated
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@ -268,8 +268,8 @@ module etx(/*AUTOARG*/
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);
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);
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*/
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*/
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defparam ecfg_if.RX =0;
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defparam etx_cfgif.RX =0;
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ecfg_if ecfg_if (.mi_dout3 (64'b0),
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ecfg_if etx_cfgif (.mi_dout3 (64'b0),
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/*AUTOINST*/
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/*AUTOINST*/
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// Outputs
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// Outputs
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.wait_out (etx_cfg_wait), // Templated
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.wait_out (etx_cfg_wait), // Templated
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@ -317,7 +317,7 @@ module etx(/*AUTOARG*/
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txwr_fifo_full //0
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txwr_fifo_full //0
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};
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};
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ecfg_tx ecfg_tx (
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ecfg_tx etx_cfg (
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/*AUTOINST*/
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/*AUTOINST*/
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// Outputs
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// Outputs
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.mi_dout (mi_cfg_dout[DW-1:0]), // Templated
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.mi_dout (mi_cfg_dout[DW-1:0]), // Templated
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@ -384,7 +384,7 @@ module etx(/*AUTOARG*/
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);
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);
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*/
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*/
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emmu emmu (
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emmu etx_mmu (
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/*AUTOINST*/
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/*AUTOINST*/
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// Outputs
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// Outputs
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.mi_dout (mi_mmu_dout[DW-1:0]), // Templated
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.mi_dout (mi_mmu_dout[DW-1:0]), // Templated
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