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Instance renaming

Will help with FPGA synthesis reports (uniqueness needed sometimes)
This commit is contained in:
Andreas Olofsson 2015-05-01 18:19:36 -04:00
parent 8461277ab1
commit 340d99cab1
4 changed files with 45 additions and 14 deletions

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@ -149,9 +149,40 @@ has the following bit ordering.
srcaddr[31:0] | [103:72]| Return address for read-request, upper data for write srcaddr[31:0] | [103:72]| Return address for read-request, upper data for write
###INTERNAL STRUCTURE ###INTERNAL STRUCTURE
```
elink
|----ereset
|----ecfg_clocks
|----eclocks
|----ecfg_cdc
|----erx
| |----erx_io (chip level I/O interface
| |----erx_protocol (elink protocol-->emesh packet converter)
| |----erx_remap (simple dstaddr remapping)
| |----erx_mmu (advanced dstaddr mapping)
| |----erx_cfgif (configuration interface)
| |----erx_cfg (basic rx config registers)
| |----erx_mailbox (fifo mailbox)
| |----erx_dma (DMA master)
| |----erx_disty (sends rx transaction to WR/RD/RR fifo)
| |----rxwr_fifo (write fifo)
| |----rxrd_fifo (read request fifo)
| |----rxrr_fifo (read response fifo)
|----etx
| |----etx_io (chip level I/O interface)
| |----etx_protocol (emesh-->elink protocol converter)
| |----etx_remap (simple dstaddr remapping)
| |----etx_mmu (advanced dstaddr mapping)
| |----etx_cfgif (configuration interface)
| |----etx_cfg (basic rx config registers)
| |----etx_dma (DMA master)
| |----etx_arbiter (sends rx transaction to WR/RD/RR fifo)
| |----txwr_fifo (write fifo)
| |----txrd_fifo (read request fifo)
| |----txrr_fifo (read response fifo)
|--------------------------------------------------------------------
```
(link to picture)
###REGISTER MAP ###REGISTER MAP
The full 32 bit physical address of an elink register is the address seen below The full 32 bit physical address of an elink register is the address seen below

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@ -268,7 +268,7 @@ module elink(/*AUTOARG*/
.reset (elink_reset), .reset (elink_reset),
); );
*/ */
fifo_cdc fifo_cdc (/*AUTOINST*/ fifo_cdc ecfg_cdc (/*AUTOINST*/
// Outputs // Outputs
.wait_in (etx_cfg_wait), // Templated .wait_in (etx_cfg_wait), // Templated
.access_out (erx_cfg_access), // Templated .access_out (erx_cfg_access), // Templated

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@ -205,7 +205,7 @@ module erx (/*AUTOARG*/
); );
*/ */
emmu emmu ( emmu erx_mmu (
/*AUTOINST*/ /*AUTOINST*/
// Outputs // Outputs
.mi_dout (mi_mmu_dout[DW-1:0]), // Templated .mi_dout (mi_mmu_dout[DW-1:0]), // Templated
@ -241,8 +241,8 @@ module erx (/*AUTOARG*/
); );
*/ */
defparam ecfg_if.RX=1; defparam erx_cfgif.RX=1;
ecfg_if ecfg_if (/*AUTOINST*/ ecfg_if erx_cfgif (/*AUTOINST*/
// Outputs // Outputs
.wait_out (), // Templated .wait_out (), // Templated
.mi_mmu_en (mi_mmu_en), .mi_mmu_en (mi_mmu_en),
@ -293,7 +293,7 @@ module erx (/*AUTOARG*/
ecfg_rx ecfg_rx (.rx_status (rx_status[15:0]), ecfg_rx erx_cfg (.rx_status (rx_status[15:0]),
.timer_cfg (), .timer_cfg (),
/*AUTOINST*/ /*AUTOINST*/
// Outputs // Outputs
@ -329,7 +329,7 @@ module erx (/*AUTOARG*/
*/ */
//shares register space with ecfg_rx //shares register space with ecfg_rx
emailbox emailbox(.mi_en (mi_cfg_en), emailbox erx_mailbox(.mi_en (mi_cfg_en),
/*AUTOINST*/ /*AUTOINST*/
// Outputs // Outputs
.mi_dout (mi_mailbox_dout[31:0]), // Templated .mi_dout (mi_mailbox_dout[31:0]), // Templated
@ -355,7 +355,7 @@ module erx (/*AUTOARG*/
); );
*/ */
edma edma(/*AUTOINST*/ edma erx_dma(/*AUTOINST*/
// Outputs // Outputs
.mi_dout (mi_dma_dout[DW-1:0]), // Templated .mi_dout (mi_dma_dout[DW-1:0]), // Templated
.edma_access (edma_access), // Templated .edma_access (edma_access), // Templated

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@ -209,7 +209,7 @@ module etx(/*AUTOARG*/
); );
*/ */
edma edma (/*AUTOINST*/ edma etx_dma (/*AUTOINST*/
// Outputs // Outputs
.mi_dout (mi_dma_dout[DW-1:0]), // Templated .mi_dout (mi_dma_dout[DW-1:0]), // Templated
.edma_access (edma_access), // Templated .edma_access (edma_access), // Templated
@ -268,8 +268,8 @@ module etx(/*AUTOARG*/
); );
*/ */
defparam ecfg_if.RX =0; defparam etx_cfgif.RX =0;
ecfg_if ecfg_if (.mi_dout3 (64'b0), ecfg_if etx_cfgif (.mi_dout3 (64'b0),
/*AUTOINST*/ /*AUTOINST*/
// Outputs // Outputs
.wait_out (etx_cfg_wait), // Templated .wait_out (etx_cfg_wait), // Templated
@ -317,7 +317,7 @@ module etx(/*AUTOARG*/
txwr_fifo_full //0 txwr_fifo_full //0
}; };
ecfg_tx ecfg_tx ( ecfg_tx etx_cfg (
/*AUTOINST*/ /*AUTOINST*/
// Outputs // Outputs
.mi_dout (mi_cfg_dout[DW-1:0]), // Templated .mi_dout (mi_cfg_dout[DW-1:0]), // Templated
@ -384,7 +384,7 @@ module etx(/*AUTOARG*/
); );
*/ */
emmu emmu ( emmu etx_mmu (
/*AUTOINST*/ /*AUTOINST*/
// Outputs // Outputs
.mi_dout (mi_mmu_dout[DW-1:0]), // Templated .mi_dout (mi_mmu_dout[DW-1:0]), // Templated