mirror of
https://github.com/aolofsson/oh.git
synced 2025-01-30 02:32:53 +08:00
Adding new "simpler" test infrastruture
- build elink with one command - place all tests in tests/ directory - new stimulus format followed - dut_elink.v created
This commit is contained in:
Andreas Olofsson
parent
af6bebe18a
commit
34d379ecb9
7
elink/dv/build.sh
Executable file
7
elink/dv/build.sh
Executable file
@ -0,0 +1,7 @@
|
||||
#!/bin/bash
|
||||
dut="elink"
|
||||
top="../../common/dv/dv_top.v"
|
||||
iverilog -g2005 -DTARGET_SIMPLE=1 -DTARGET_XILINX=1 $top dut_${dut}.v -f ../../common/dv/libs.cmd -o ${dut}.vvp
|
||||
|
||||
#-Wall
|
||||
|
||||
368
elink/dv/dut_elink.v
Normal file
368
elink/dv/dut_elink.v
Normal file
@ -0,0 +1,368 @@
|
||||
`define CFG_FAKECLK 1 /*stupid verilator doesn't get clock gating*/
|
||||
`define CFG_MDW 32 /*Width of mesh network*/
|
||||
`define CFG_DW 32 /*Width of datapath*/
|
||||
`define CFG_AW 32 /*Width of address space*/
|
||||
`define CFG_LW 8 /*Link port width*/
|
||||
|
||||
module dut(/*AUTOARG*/
|
||||
// Outputs
|
||||
dut_active, wait_out, access_out, packet_out,
|
||||
// Inputs
|
||||
clk, nreset, vdd, vss, access_in, packet_in, wait_in
|
||||
);
|
||||
|
||||
parameter AW = 32;
|
||||
parameter DW = 32;
|
||||
parameter CW = 2;
|
||||
parameter IDW = 12;
|
||||
parameter M_IDW = 6;
|
||||
parameter S_IDW = 12;
|
||||
parameter PW = 104;
|
||||
parameter N = 1;
|
||||
|
||||
//#######################################
|
||||
//# CLOCK AND RESET
|
||||
//#######################################
|
||||
input clk;
|
||||
input nreset;
|
||||
input [N*N-1:0] vdd;
|
||||
input vss;
|
||||
output dut_active;
|
||||
|
||||
//#######################################
|
||||
//#EMESH INTERFACE
|
||||
//#######################################
|
||||
|
||||
//Stimulus Driven Transaction
|
||||
input [N-1:0] access_in;
|
||||
input [N*PW-1:0] packet_in;
|
||||
output [N-1:0] wait_out;
|
||||
|
||||
//DUT driven transactoin
|
||||
output [N-1:0] access_out;
|
||||
output [N*PW-1:0] packet_out;
|
||||
input [N-1:0] wait_in;
|
||||
|
||||
/*AUTOINPUT*/
|
||||
|
||||
//floating wires
|
||||
wire elink0_cclk_n; // From elink0 of elink.v
|
||||
wire elink0_cclk_p; // From elink0 of elink.v
|
||||
wire elink0_chip_resetb; // From elink0 of elink.v
|
||||
wire [11:0] elink0_chipid; // From elink0 of elink.v
|
||||
wire elink0_mailbox_full; // From elink0 of elink.v
|
||||
wire elink0_mailbox_not_empty;// From elink0 of elink.v
|
||||
wire elink0_timeout; // From elink0 of elink.v
|
||||
wire elink1_cclk_n; // From elink1 of elink.v
|
||||
wire elink1_cclk_p; // From elink1 of elink.v
|
||||
wire elink1_chip_resetb; // From elink1 of elink.v
|
||||
wire [11:0] elink1_chipid; // From elink1 of elink.v
|
||||
wire elink1_mailbox_full; // From elink1 of elink.v
|
||||
wire elink1_mailbox_not_empty;// From elink1 of elink.v
|
||||
wire elink1_rxrd_access; // From elink1 of elink.v
|
||||
wire [PW-1:0] elink1_rxrd_packet; // From elink1 of elink.v
|
||||
wire elink1_rxrr_access; // From elink1 of elink.v
|
||||
wire [PW-1:0] elink1_rxrr_packet; // From elink1 of elink.v
|
||||
wire elink1_rxwr_access; // From elink1 of elink.v
|
||||
wire [PW-1:0] elink1_rxwr_packet; // From elink1 of elink.v
|
||||
wire elink1_timeout; // From elink1 of elink.v
|
||||
wire elink1_txrd_wait; // From elink1 of elink.v
|
||||
wire elink1_txrr_access; // From emem of ememory.v
|
||||
wire [PW-1:0] elink1_txrr_packet; // From emem of ememory.v
|
||||
wire elink1_txrr_wait; // From elink1 of elink.v
|
||||
wire elink1_txwr_wait; // From elink1 of elink.v
|
||||
|
||||
//memory wires
|
||||
wire emem_access;
|
||||
wire [PW-1:0] emem_packet;
|
||||
wire elink1_rxrd_wait;
|
||||
wire elink1_rxwr_wait;
|
||||
|
||||
// Beginning of automatic outputs (from unused autoinst outputs)
|
||||
|
||||
// End of automatics
|
||||
|
||||
/*AUTOWIRE*/
|
||||
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
||||
wire elink0_rxo_rd_wait_n; // From elink0 of elink.v
|
||||
wire elink0_rxo_rd_wait_p; // From elink0 of elink.v
|
||||
wire elink0_rxo_wr_wait_n; // From elink0 of elink.v
|
||||
wire elink0_rxo_wr_wait_p; // From elink0 of elink.v
|
||||
wire elink0_rxrr_access; // From elink0 of elink.v
|
||||
wire [PW-1:0] elink0_rxrr_packet; // From elink0 of elink.v
|
||||
wire [7:0] elink0_txo_data_n; // From elink0 of elink.v
|
||||
wire [7:0] elink0_txo_data_p; // From elink0 of elink.v
|
||||
wire elink0_txo_frame_n; // From elink0 of elink.v
|
||||
wire elink0_txo_frame_p; // From elink0 of elink.v
|
||||
wire elink0_txo_lclk_n; // From elink0 of elink.v
|
||||
wire elink0_txo_lclk_p; // From elink0 of elink.v
|
||||
wire elink0_txrd_access; // From emesh_if of emesh_if.v
|
||||
wire [PW-1:0] elink0_txrd_packet; // From emesh_if of emesh_if.v
|
||||
wire elink0_txrd_wait; // From elink0 of elink.v
|
||||
wire elink0_txwr_access; // From emesh_if of emesh_if.v
|
||||
wire [PW-1:0] elink0_txwr_packet; // From emesh_if of emesh_if.v
|
||||
wire elink0_txwr_wait; // From elink0 of elink.v
|
||||
wire elink1_elink_active; // From elink1 of elink.v
|
||||
wire elink1_rxo_rd_wait_n; // From elink1 of elink.v
|
||||
wire elink1_rxo_rd_wait_p; // From elink1 of elink.v
|
||||
wire elink1_rxo_wr_wait_n; // From elink1 of elink.v
|
||||
wire elink1_rxo_wr_wait_p; // From elink1 of elink.v
|
||||
wire [7:0] elink1_txo_data_n; // From elink1 of elink.v
|
||||
wire [7:0] elink1_txo_data_p; // From elink1 of elink.v
|
||||
wire elink1_txo_frame_n; // From elink1 of elink.v
|
||||
wire elink1_txo_frame_p; // From elink1 of elink.v
|
||||
wire elink1_txo_lclk_n; // From elink1 of elink.v
|
||||
wire elink1_txo_lclk_p; // From elink1 of elink.v
|
||||
// End of automatics
|
||||
|
||||
|
||||
//######################################################################
|
||||
//EMESH INTERFACE
|
||||
//######################################################################
|
||||
|
||||
/*emesh_if AUTO_TEMPLATE (//Stimulus
|
||||
.e2c_emesh_\(.*\)_in(\1_in[]),
|
||||
.e2c_emesh_\(.*\)_out(\1_out[]),
|
||||
//Response
|
||||
.c2e_emesh_\(.*\)_out(\1_out[]),
|
||||
.c2e_emesh_\(.*\)_in(\1_in[]),
|
||||
.c2e_cmesh_\(.*\)_in(elink0_rxrr_\1[]),
|
||||
//Link side transaction outgoing
|
||||
.e2c_cmesh_\(.*\)_out(elink0_txwr_\1[]),
|
||||
.e2c_cmesh_wait_in(elink0_txwr_wait),
|
||||
.e2c_rmesh_\(.*\)_out(elink0_txrd_\1[]),
|
||||
.e2c_rmesh_wait_in(elink0_txrd_wait),
|
||||
.c2e_\(.*\)_wait_out(),
|
||||
);
|
||||
*/
|
||||
|
||||
|
||||
|
||||
emesh_if #(.PW(PW)) emesh_if (.c2e_rmesh_access_in(1'b0),
|
||||
.c2e_rmesh_packet_in({(PW){1'b0}}),
|
||||
.c2e_xmesh_access_in(1'b0),
|
||||
.c2e_xmesh_packet_in({(PW){1'b0}}),
|
||||
.e2c_xmesh_wait_in(1'b0),
|
||||
.e2c_xmesh_access_out(),
|
||||
.e2c_xmesh_packet_out(),
|
||||
/*AUTOINST*/
|
||||
// Outputs
|
||||
.c2e_cmesh_wait_out (), // Templated
|
||||
.e2c_cmesh_access_out (elink0_txwr_access), // Templated
|
||||
.e2c_cmesh_packet_out (elink0_txwr_packet[PW-1:0]), // Templated
|
||||
.c2e_rmesh_wait_out (), // Templated
|
||||
.e2c_rmesh_access_out (elink0_txrd_access), // Templated
|
||||
.e2c_rmesh_packet_out (elink0_txrd_packet[PW-1:0]), // Templated
|
||||
.c2e_xmesh_wait_out (), // Templated
|
||||
.e2c_emesh_wait_out (wait_out), // Templated
|
||||
.c2e_emesh_access_out (access_out), // Templated
|
||||
.c2e_emesh_packet_out (packet_out[PW-1:0]), // Templated
|
||||
// Inputs
|
||||
.c2e_cmesh_access_in (elink0_rxrr_access), // Templated
|
||||
.c2e_cmesh_packet_in (elink0_rxrr_packet[PW-1:0]), // Templated
|
||||
.e2c_cmesh_wait_in (elink0_txwr_wait), // Templated
|
||||
.e2c_rmesh_wait_in (elink0_txrd_wait), // Templated
|
||||
.e2c_emesh_access_in (access_in), // Templated
|
||||
.e2c_emesh_packet_in (packet_in[PW-1:0]), // Templated
|
||||
.c2e_emesh_wait_in (wait_in)); // Templated
|
||||
|
||||
|
||||
|
||||
//######################################################################
|
||||
//1ST ELINK
|
||||
//######################################################################
|
||||
|
||||
|
||||
/*elink AUTO_TEMPLATE (
|
||||
// Outputs
|
||||
.sys_clk (clk),
|
||||
.sys_reset (~nreset),
|
||||
.rxi_\(.*\) (elink1_txo_\1[]),
|
||||
.txi_\(.*\) (elink1_rxo_\1[]),
|
||||
.\(.*\) (@"(substring vl-cell-name 0 6)"_\1[]),
|
||||
|
||||
);
|
||||
*/
|
||||
defparam elink0.ID = 12'h810;
|
||||
defparam elink0.ETYPE = 0;
|
||||
elink elink0 (.elink_active (dut_active),
|
||||
.txrr_access (1'b0),//not tested
|
||||
.txrr_packet ({(PW){1'b0}}),
|
||||
.txrr_wait (), //not tested
|
||||
.rxwr_access (),
|
||||
.rxwr_packet (),
|
||||
.rxrd_access (),
|
||||
.rxrd_packet (),
|
||||
.rxwr_wait (1'b0),//not tested
|
||||
.rxrd_wait (1'b0),//not tested
|
||||
.rxrr_wait (1'b0),//not tested
|
||||
/*AUTOINST*/
|
||||
// Outputs
|
||||
.rxo_wr_wait_p (elink0_rxo_wr_wait_p), // Templated
|
||||
.rxo_wr_wait_n (elink0_rxo_wr_wait_n), // Templated
|
||||
.rxo_rd_wait_p (elink0_rxo_rd_wait_p), // Templated
|
||||
.rxo_rd_wait_n (elink0_rxo_rd_wait_n), // Templated
|
||||
.txo_lclk_p (elink0_txo_lclk_p), // Templated
|
||||
.txo_lclk_n (elink0_txo_lclk_n), // Templated
|
||||
.txo_frame_p (elink0_txo_frame_p), // Templated
|
||||
.txo_frame_n (elink0_txo_frame_n), // Templated
|
||||
.txo_data_p (elink0_txo_data_p[7:0]), // Templated
|
||||
.txo_data_n (elink0_txo_data_n[7:0]), // Templated
|
||||
.chipid (elink0_chipid[11:0]), // Templated
|
||||
.cclk_p (elink0_cclk_p), // Templated
|
||||
.cclk_n (elink0_cclk_n), // Templated
|
||||
.chip_resetb (elink0_chip_resetb), // Templated
|
||||
.mailbox_not_empty (elink0_mailbox_not_empty), // Templated
|
||||
.mailbox_full (elink0_mailbox_full), // Templated
|
||||
.timeout (elink0_timeout), // Templated
|
||||
.rxrr_access (elink0_rxrr_access), // Templated
|
||||
.rxrr_packet (elink0_rxrr_packet[PW-1:0]), // Templated
|
||||
.txwr_wait (elink0_txwr_wait), // Templated
|
||||
.txrd_wait (elink0_txrd_wait), // Templated
|
||||
// Inputs
|
||||
.sys_reset (~nreset), // Templated
|
||||
.sys_clk (clk), // Templated
|
||||
.rxi_lclk_p (elink1_txo_lclk_p), // Templated
|
||||
.rxi_lclk_n (elink1_txo_lclk_n), // Templated
|
||||
.rxi_frame_p (elink1_txo_frame_p), // Templated
|
||||
.rxi_frame_n (elink1_txo_frame_n), // Templated
|
||||
.rxi_data_p (elink1_txo_data_p[7:0]), // Templated
|
||||
.rxi_data_n (elink1_txo_data_n[7:0]), // Templated
|
||||
.txi_wr_wait_p (elink1_rxo_wr_wait_p), // Templated
|
||||
.txi_wr_wait_n (elink1_rxo_wr_wait_n), // Templated
|
||||
.txi_rd_wait_p (elink1_rxo_rd_wait_p), // Templated
|
||||
.txi_rd_wait_n (elink1_rxo_rd_wait_n), // Templated
|
||||
.txwr_access (elink0_txwr_access), // Templated
|
||||
.txwr_packet (elink0_txwr_packet[PW-1:0]), // Templated
|
||||
.txrd_access (elink0_txrd_access), // Templated
|
||||
.txrd_packet (elink0_txrd_packet[PW-1:0])); // Templated
|
||||
|
||||
|
||||
//######################################################################
|
||||
//2ND ELINK (WITH EPIPHANY MEMORY)
|
||||
//######################################################################
|
||||
/*elink AUTO_TEMPLATE (
|
||||
// Outputs
|
||||
.sys_clk (clk),
|
||||
.sys_reset (~nreset),
|
||||
.rxi_\(.*\) (elink0_txo_\1[]),
|
||||
.txi_\(.*\) (elink0_rxo_\1[]),
|
||||
.\(.*\) (@"(substring vl-cell-name 0 6)"_\1[]),
|
||||
|
||||
);
|
||||
*/
|
||||
//No read/write from elink1 (for now)
|
||||
assign elink1_txrd_access = 1'b0;
|
||||
assign elink1_txrd_packet = 'b0;
|
||||
assign elink1_txwr_access = 1'b0;
|
||||
assign elink1_txwr_packet = 'b0;
|
||||
assign elink1_rxrr_wait = 1'b0;
|
||||
|
||||
defparam elink1.ID = 12'h820;
|
||||
defparam elink1.ETYPE = 0;
|
||||
|
||||
elink elink1 (.rxrr_wait (1'b0),
|
||||
.txwr_access (1'b0),
|
||||
.txwr_packet ({(PW){1'b0}}),
|
||||
.txrd_access (1'b0),
|
||||
.txrd_packet ({(PW){1'b0}}),
|
||||
.txrr_access (elink1_txrr_access),
|
||||
.txrr_packet (elink1_txrr_packet[PW-1:0]),
|
||||
/*AUTOINST*/
|
||||
// Outputs
|
||||
.elink_active (elink1_elink_active), // Templated
|
||||
.rxo_wr_wait_p (elink1_rxo_wr_wait_p), // Templated
|
||||
.rxo_wr_wait_n (elink1_rxo_wr_wait_n), // Templated
|
||||
.rxo_rd_wait_p (elink1_rxo_rd_wait_p), // Templated
|
||||
.rxo_rd_wait_n (elink1_rxo_rd_wait_n), // Templated
|
||||
.txo_lclk_p (elink1_txo_lclk_p), // Templated
|
||||
.txo_lclk_n (elink1_txo_lclk_n), // Templated
|
||||
.txo_frame_p (elink1_txo_frame_p), // Templated
|
||||
.txo_frame_n (elink1_txo_frame_n), // Templated
|
||||
.txo_data_p (elink1_txo_data_p[7:0]), // Templated
|
||||
.txo_data_n (elink1_txo_data_n[7:0]), // Templated
|
||||
.chipid (elink1_chipid[11:0]), // Templated
|
||||
.cclk_p (elink1_cclk_p), // Templated
|
||||
.cclk_n (elink1_cclk_n), // Templated
|
||||
.chip_resetb (elink1_chip_resetb), // Templated
|
||||
.mailbox_not_empty (elink1_mailbox_not_empty), // Templated
|
||||
.mailbox_full (elink1_mailbox_full), // Templated
|
||||
.timeout (elink1_timeout), // Templated
|
||||
.rxwr_access (elink1_rxwr_access), // Templated
|
||||
.rxwr_packet (elink1_rxwr_packet[PW-1:0]), // Templated
|
||||
.rxrd_access (elink1_rxrd_access), // Templated
|
||||
.rxrd_packet (elink1_rxrd_packet[PW-1:0]), // Templated
|
||||
.rxrr_access (elink1_rxrr_access), // Templated
|
||||
.rxrr_packet (elink1_rxrr_packet[PW-1:0]), // Templated
|
||||
.txwr_wait (elink1_txwr_wait), // Templated
|
||||
.txrd_wait (elink1_txrd_wait), // Templated
|
||||
.txrr_wait (elink1_txrr_wait), // Templated
|
||||
// Inputs
|
||||
.sys_reset (~nreset), // Templated
|
||||
.sys_clk (clk), // Templated
|
||||
.rxi_lclk_p (elink0_txo_lclk_p), // Templated
|
||||
.rxi_lclk_n (elink0_txo_lclk_n), // Templated
|
||||
.rxi_frame_p (elink0_txo_frame_p), // Templated
|
||||
.rxi_frame_n (elink0_txo_frame_n), // Templated
|
||||
.rxi_data_p (elink0_txo_data_p[7:0]), // Templated
|
||||
.rxi_data_n (elink0_txo_data_n[7:0]), // Templated
|
||||
.txi_wr_wait_p (elink0_rxo_wr_wait_p), // Templated
|
||||
.txi_wr_wait_n (elink0_rxo_wr_wait_n), // Templated
|
||||
.txi_rd_wait_p (elink0_rxo_rd_wait_p), // Templated
|
||||
.txi_rd_wait_n (elink0_rxo_rd_wait_n), // Templated
|
||||
.rxwr_wait (elink1_rxwr_wait), // Templated
|
||||
.rxrd_wait (elink1_rxrd_wait)); // Templated
|
||||
|
||||
|
||||
//"Arbitration" between read/write transaction
|
||||
assign emem_access = elink1_rxwr_access | elink1_rxrd_access;
|
||||
|
||||
assign emem_packet[PW-1:0] = elink1_rxwr_access ? elink1_rxwr_packet[PW-1:0]:
|
||||
elink1_rxrd_packet[PW-1:0];
|
||||
|
||||
assign elink1_rxrd_wait = emem_wait | elink1_rxwr_access;
|
||||
assign elink1_rxwr_wait = 1'b0;//TODO: elink1_random_wait
|
||||
|
||||
/*ememory AUTO_TEMPLATE (
|
||||
// Outputs
|
||||
.\(.*\)_out (elink1_txrr_\1[]),
|
||||
.\(.*\)_in (emem_\1[]),
|
||||
.wait_out (emem_wait),
|
||||
.reset (~nreset),
|
||||
);
|
||||
*/
|
||||
|
||||
ememory emem (.wait_in (elink1_txrr_wait),//pushback on reads
|
||||
.clk (clk),
|
||||
.wait_out (emem_wait),
|
||||
.coreid (12'h0),
|
||||
/*AUTOINST*/
|
||||
// Outputs
|
||||
.access_out (elink1_txrr_access), // Templated
|
||||
.packet_out (elink1_txrr_packet[PW-1:0]), // Templated
|
||||
// Inputs
|
||||
.nreset (nreset),
|
||||
.access_in (emem_access), // Templated
|
||||
.packet_in (emem_packet[PW-1:0])); // Templated
|
||||
|
||||
|
||||
endmodule // dv_elink
|
||||
// Local Variables:
|
||||
// verilog-library-directories:("." "../hdl" "../../memory/hdl" "../../emesh/hdl")
|
||||
// End:
|
||||
|
||||
/*
|
||||
Copyright (C) 2014 Adapteva, Inc.
|
||||
Contributed by Andreas Olofsson <andreas@adapteva.com>
|
||||
|
||||
This program is free software: you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation, either version 3 of the License, or
|
||||
(at your option) any later version.This program is distributed in the hope
|
||||
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
|
||||
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details. You should have received a copy
|
||||
of the GNU General Public License along with this program (see the file
|
||||
COPYING). If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
@ -1,57 +0,0 @@
|
||||
/* verilator lint_off WIDTH */
|
||||
module emesh_monitor(/*AUTOARG*/
|
||||
// Inputs
|
||||
clk, reset, itrace, etime, emesh_access, emesh_packet, emesh_wait
|
||||
);
|
||||
parameter AW = 32;
|
||||
parameter DW = 32;
|
||||
parameter NAME = "cpu";
|
||||
parameter PW = 104;
|
||||
|
||||
|
||||
//BASIC INTERFACE
|
||||
input clk;
|
||||
input reset;
|
||||
input itrace;
|
||||
input [31:0] etime;
|
||||
|
||||
//MESH TRANSCTION
|
||||
input emesh_access;
|
||||
input [PW-1:0] emesh_packet;
|
||||
input emesh_wait;
|
||||
|
||||
//core name for trace
|
||||
reg [63:0] name=NAME;
|
||||
reg [31:0] ftrace;
|
||||
|
||||
initial
|
||||
begin
|
||||
ftrace = $fopen({NAME,".trace"}, "w");
|
||||
end
|
||||
|
||||
always @ (posedge clk)
|
||||
if(itrace & ~reset & emesh_access & ~emesh_wait)
|
||||
begin
|
||||
//$fwrite(ftrace, "TIME=%h\n",etime[31:0]);
|
||||
$fwrite(ftrace, "%h_%h_%h_%h\n",emesh_packet[103:72], emesh_packet[71:40],emesh_packet[39:8],
|
||||
{emesh_packet[7:4],emesh_packet[3:2],emesh_packet[1],emesh_access});
|
||||
end
|
||||
endmodule // emesh_monitor
|
||||
|
||||
|
||||
/*
|
||||
Copyright (C) 2014 Adapteva, Inc.
|
||||
Contributed by Andreas Olofsson <andreas@adapteva.com>
|
||||
|
||||
This program is free software: you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation, either version 3 of the License, or
|
||||
(at your option) any later version.This program is distributed in the hope
|
||||
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
|
||||
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details. You should have received a copy
|
||||
of the GNU General Public License along with this program (see the file
|
||||
COPYING). If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
|
||||
@ -1,14 +1,7 @@
|
||||
#!/bin/bash
|
||||
|
||||
#Linting in Verilator
|
||||
#verilator --lint-only -F elink.cmd -DTARGET_VERILATOR dv_elink.v
|
||||
|
||||
#a sorry hack, too tired to get it right, please fix...
|
||||
TRANS=$(wc -l test.memh)
|
||||
TRANS=${TRANS:0:3}
|
||||
#RANDOM TEST
|
||||
iverilog -I../hdl -I../../emailbox/hdl -f elink.cmd -DMANUAL -DTRANS=$TRANS -DTESTNAME=test.memh -DTARGET_XILINX -DSIM
|
||||
#iverilog -f elink.cmd -DAUTO
|
||||
|
||||
#Running sim
|
||||
./a.out
|
||||
if [ ! -e "test_0.memh" ]
|
||||
then
|
||||
rm test_0.memh
|
||||
fi
|
||||
cp $1 test_0.memh
|
||||
./elink.vvp
|
||||
|
||||
41
elink/dv/tests/test_basic.memh
Normal file
41
elink/dv/tests/test_basic.memh
Normal file
@ -0,0 +1,41 @@
|
||||
00000000_11111111_80800000_0a_0000 //32-bit write sequence
|
||||
00000000_22222222_80800008_0a_0000 //
|
||||
00000000_33333333_80800010_0a_0000 //
|
||||
00000000_44444444_80800018_0a_0000 //
|
||||
00000000_55555555_80800020_0a_0000 //
|
||||
00000000_66666666_80800028_0a_0000 //
|
||||
00000000_77777777_80800030_0a_0000 //
|
||||
00000000_88888888_80800038_0a_0000 //
|
||||
00000000_99999999_80800040_0a_0000 //
|
||||
00000000_aaaaaaaa_80800048_0a_0000 //
|
||||
00000000_bbbbbbbb_80800050_0a_0000 //
|
||||
00000000_cccccccc_80800058_0a_0000 //
|
||||
00000000_dddddddd_80800060_0a_0000 //
|
||||
00000000_eeeeeeee_80800068_0a_0000 //
|
||||
00000000_ffffffff_80800070_0a_0000 //
|
||||
810D0000_DEADBEEF_80800000_08_0000 //32-bit read sequence
|
||||
810D0008_DEADBEEF_80800008_08_0000 //
|
||||
810D0010_DEADBEEF_80800010_08_0000 //
|
||||
810D0018_DEADBEEF_80800018_08_0000 //
|
||||
810D0020_DEADBEEF_80800020_08_0000 //
|
||||
810D0028_DEADBEEF_80800028_08_0000 //
|
||||
810D0030_DEADBEEF_80800030_08_0000 //
|
||||
810D0038_DEADBEEF_80800038_08_0000 //
|
||||
810D0040_DEADBEEF_80800040_08_0000 //
|
||||
810D0048_DEADBEEF_80800048_08_0000 //
|
||||
810D0050_DEADBEEF_80800050_08_0000 //
|
||||
810D0058_DEADBEEF_80800059_08_0000 //
|
||||
810D0060_DEADBEEF_80800060_08_0000 //
|
||||
810D0068_DEADBEEF_80800068_08_0000 //
|
||||
810D0070_DEADBEEF_80800070_08_0000 //
|
||||
B7B6B5B4_B3B2B1B0_80800100_0e_0000 //64-bit write burst
|
||||
C7C6C5C4_C3C2C1C0_80800108_0e_0000 //
|
||||
D7D6D5D4_D3D2D1D0_80800110_0e_0000 //
|
||||
E7E6E5E4_E3E2E1E0_80800118_0e_0000 //
|
||||
F7F6F5F4_F3F2F1F0_80800120_0e_0000 //
|
||||
810D0100_DEADBEEF_80800100_0c_0000 //reading back burst
|
||||
810D0108_DEADBEEF_80800108_0c_0000 //
|
||||
810D0110_DEADBEEF_80800110_0c_0000 //
|
||||
810D0118_DEADBEEF_80800118_0c_0000 //
|
||||
810D0120_DEADBEEF_80800120_0c_0000 //
|
||||
|
||||
5
elink/dv/tests/test_burst.memh
Normal file
5
elink/dv/tests/test_burst.memh
Normal file
@ -0,0 +1,5 @@
|
||||
B7B6B5B4_B3B2B2B0_80800000_0e //write to epiphany
|
||||
C7C6C5C4_C3C2C2C0_80800008_0e //
|
||||
D7D6D5D4_D3D2D2D0_80800010_0e //
|
||||
E7E6E5E4_E3E2E2E0_80800018_0e //
|
||||
F7F6F5F4_F3F2F2F0_80800020_0e //
|
||||
39
elink/dv/tests/test_regs.memh
Normal file
39
elink/dv/tests/test_regs.memh
Normal file
@ -0,0 +1,39 @@
|
||||
00000000_00000000_00000000_00 //***START OF TX REGS***
|
||||
00000000_00000001_810f0200_0b //E_RESET
|
||||
00000000_00000000_00000000_00 //wait
|
||||
00000000_00000000_00000000_00 //wait
|
||||
00000000_00000000_00000000_00 //wait
|
||||
00000000_00000000_00000000_00 //wait
|
||||
00000000_00000000_00000000_00 //wait
|
||||
00000000_00000000_810f0200_0b //E_RESET
|
||||
00000000_00000333_810f0204_0b //E_CLK
|
||||
00000000_AAAAAAAA_810f0208_0b //E_CHIPID
|
||||
810D0000_00000000_810f0208_09 //E_CHIPID
|
||||
00000000_BBBBBBBB_810f020c_0b //E_VERSION
|
||||
810D0001_00000000_810f020c_09 //E_VERSION
|
||||
00000000_00000001_810f0210_0b //ETX_CFG
|
||||
810D0002_00000000_810f0210_09 //ETX_CFG
|
||||
810D0003_00000000_810f0214_09 //ETX_STATUS
|
||||
00000000_CCCCCCCC_810f0218_0b //ETX_GPIO
|
||||
00000000_DDDDDDDD_810f0500_0b //ETX_DMACFG
|
||||
810D0004_FFFFFFFF_810f0500_09 //ETX_DMACFG
|
||||
00000000_FFFFFFFF_810e0000_0b //ETX_MMU
|
||||
00000000_00000000_00000000_00 //WAIT
|
||||
00000000_00000000_00000000_00 //WAIT
|
||||
00000000_00000000_00000000_00 //WAIT
|
||||
00000000_00000000_00000000_00 //WAIT
|
||||
00000000_00000000_00000000_00 //WAIT
|
||||
00000000_00000000_00000000_00 //WAIT
|
||||
00000000_00000000_00000000_00 //WAIT
|
||||
00000000_00000000_00000000_00 //WAIT
|
||||
00000000_00000000_00000000_00 //WAIT
|
||||
00000000_00000000_00000000_00 //WAIT
|
||||
00000000_00000000_00000000_00 //***END OF TX REGS***
|
||||
00000000_00000001_810f0300_0b //ERX_CFG
|
||||
810D0005_00000000_810f0300_09 //ERX_CFG
|
||||
810D0006_00000000_810f0304_09 //ERX_STATUS
|
||||
810D0007_00000000_810f0308_09 //ERX_GPIO
|
||||
00000000_CCCCCCCC_810f0310_0b //ERX_OFFSET
|
||||
810D0008_00000000_810f0310_09 //ERX_OFFSET
|
||||
810D0009_DDDDDDDD_810f0314_09 //E_MAILBOXLO
|
||||
810D000A_EEEEEEEE_810f0318_09 //E_MAILBOXHI
|
||||
Loading…
x
Reference in New Issue
Block a user