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zcu102: zcu102: Use Petalinux 2016.4 design as base
Change partname to: xczu9eg-ffvb1156-1-i-es2 Don't set BOARD_PART. Remove si570 pl component. Full path: petalinux-bsp/xilinx-zcu102-zu9-es2-rev1.0-2016.4/hardware/xilinx-zcu102-zu9-es2-rev1.0-2016.4/ Signed-off-by: Ola Jeppsson <ola@adapteva.com>
This commit is contained in:
Ola Jeppsson
parent
02955c09a5
commit
37a38ab486
@ -43,8 +43,7 @@ if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
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set list_projs [get_projects -quiet]
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if { $list_projs eq "" } {
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create_project project_1 myproj -part xczu9eg-ffvb1156-2-i-es2
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set_property BOARD_PART xilinx.com:zcu102:part0:2.0 [current_project]
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create_project project_1 myproj -part xczu9eg-ffvb1156-1-i-es2
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}
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@ -121,73 +120,6 @@ if { $nRet != 0 } {
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##################################################################
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# Hierarchical cell: si570_clk
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proc create_hier_cell_si570_clk { parentCell nameHier } {
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variable script_folder
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if { $parentCell eq "" || $nameHier eq "" } {
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catch {common::send_msg_id "BD_TCL-102" "ERROR" create_hier_cell_si570_clk() - Empty argument(s)!"}
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return
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}
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# Get object for parentCell
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set parentObj [get_bd_cells $parentCell]
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if { $parentObj == "" } {
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catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
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return
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}
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# Make sure parentObj is hier blk
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set parentType [get_property TYPE $parentObj]
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if { $parentType ne "hier" } {
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catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
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return
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}
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# Save current instance; Restore later
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set oldCurInst [current_bd_instance .]
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# Set parent object as current
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current_bd_instance $parentObj
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# Create cell and set as current instance
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set hier_obj [create_bd_cell -type hier $nameHier]
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current_bd_instance $hier_obj
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# Create interface pins
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create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 CLK_IN_D
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# Create pins
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create_bd_pin -dir O -from 0 -to 0 BUFG_O
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# Create instance: util_ds_buf_0, and set properties
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set util_ds_buf_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.1 util_ds_buf_0 ]
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set_property -dict [ list \
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CONFIG.C_BUF_TYPE {IBUFDSGTE} \
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] $util_ds_buf_0
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# Create instance: util_ds_buf_1, and set properties
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set util_ds_buf_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.1 util_ds_buf_1 ]
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set_property -dict [ list \
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CONFIG.C_BUF_TYPE {BUFG_GT} \
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] $util_ds_buf_1
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# Create instance: xlconstant_vcc, and set properties
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set xlconstant_vcc [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_vcc ]
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# Create interface connections
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connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins CLK_IN_D] [get_bd_intf_pins util_ds_buf_0/CLK_IN_D]
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# Create port connections
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connect_bd_net -net util_ds_buf_0_IBUF_DS_ODIV2 [get_bd_pins util_ds_buf_0/IBUF_DS_ODIV2] [get_bd_pins util_ds_buf_1/BUFG_GT_I]
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connect_bd_net -net util_ds_buf_1_BUFG_GT_O [get_bd_pins BUFG_O] [get_bd_pins util_ds_buf_1/BUFG_GT_O]
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connect_bd_net -net xlconstant_0_dout [get_bd_pins util_ds_buf_1/BUFG_GT_CE] [get_bd_pins xlconstant_vcc/dout]
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# Restore current instance
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current_bd_instance $oldCurInst
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}
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# Procedure to create entire design; Provide argument to make
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# procedure reusable. If parentCell is "", will use root.
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@ -221,7 +153,6 @@ proc create_root_design { parentCell } {
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# Create interface ports
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set si570 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 si570 ]
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# Create ports
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set cclk0_n [ create_bd_port -dir O cclk0_n ]
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@ -262,9 +193,6 @@ CONFIG.NUM_MI {1} \
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# Create instance: proc_sys_reset_0, and set properties
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set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ]
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# Create instance: si570_clk
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create_hier_cell_si570_clk [current_bd_instance .] si570_clk
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# Create instance: sys_concat_intc, and set properties
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set sys_concat_intc [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc ]
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set_property -dict [ list \
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@ -387,22 +315,22 @@ CONFIG.PSU_MIO_25_DRIVE_STRENGTH {12} \
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CONFIG.PSU_MIO_25_INPUT_TYPE {schmitt} \
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CONFIG.PSU_MIO_25_PULLUPDOWN {pullup} \
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CONFIG.PSU_MIO_25_SLEW {slow} \
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CONFIG.PSU_MIO_26_DIRECTION {in} \
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CONFIG.PSU_MIO_26_DIRECTION {inout} \
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CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \
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CONFIG.PSU_MIO_26_INPUT_TYPE {schmitt} \
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CONFIG.PSU_MIO_26_PULLUPDOWN {pullup} \
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CONFIG.PSU_MIO_26_SLEW {slow} \
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CONFIG.PSU_MIO_27_DIRECTION {out} \
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CONFIG.PSU_MIO_27_DIRECTION {inout} \
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CONFIG.PSU_MIO_27_DRIVE_STRENGTH {12} \
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CONFIG.PSU_MIO_27_INPUT_TYPE {schmitt} \
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CONFIG.PSU_MIO_27_PULLUPDOWN {pullup} \
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CONFIG.PSU_MIO_27_SLEW {slow} \
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CONFIG.PSU_MIO_28_DIRECTION {in} \
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CONFIG.PSU_MIO_28_DIRECTION {inout} \
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CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \
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CONFIG.PSU_MIO_28_INPUT_TYPE {schmitt} \
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CONFIG.PSU_MIO_28_PULLUPDOWN {pullup} \
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CONFIG.PSU_MIO_28_SLEW {slow} \
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CONFIG.PSU_MIO_29_DIRECTION {out} \
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CONFIG.PSU_MIO_29_DIRECTION {inout} \
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CONFIG.PSU_MIO_29_DRIVE_STRENGTH {12} \
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CONFIG.PSU_MIO_29_INPUT_TYPE {schmitt} \
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CONFIG.PSU_MIO_29_PULLUPDOWN {pullup} \
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@ -412,12 +340,12 @@ CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \
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CONFIG.PSU_MIO_2_INPUT_TYPE {schmitt} \
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CONFIG.PSU_MIO_2_PULLUPDOWN {pullup} \
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CONFIG.PSU_MIO_2_SLEW {slow} \
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CONFIG.PSU_MIO_30_DIRECTION {in} \
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CONFIG.PSU_MIO_30_DIRECTION {inout} \
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CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \
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CONFIG.PSU_MIO_30_INPUT_TYPE {schmitt} \
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CONFIG.PSU_MIO_30_PULLUPDOWN {pullup} \
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CONFIG.PSU_MIO_30_SLEW {slow} \
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CONFIG.PSU_MIO_31_DIRECTION {inout} \
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CONFIG.PSU_MIO_31_DIRECTION {out} \
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CONFIG.PSU_MIO_31_DRIVE_STRENGTH {12} \
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CONFIG.PSU_MIO_31_INPUT_TYPE {schmitt} \
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CONFIG.PSU_MIO_31_PULLUPDOWN {pullup} \
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@ -687,8 +615,8 @@ CONFIG.PSU_MIO_9_DRIVE_STRENGTH {12} \
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CONFIG.PSU_MIO_9_INPUT_TYPE {schmitt} \
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CONFIG.PSU_MIO_9_PULLUPDOWN {pullup} \
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CONFIG.PSU_MIO_9_SLEW {slow} \
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CONFIG.PSU_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Feedback Clk#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO0 MIO#I2C 0#I2C 0#I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1#GPIO0 MIO#GPIO0 MIO#CAN 1#CAN 1#PMU GPI 0#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#PMU GPO 0#PMU GPO 1#PMU GPO 2#PMU GPO 3#PMU GPO 4#PMU GPO 5#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO 3} \
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CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#so_mo1#mo2#mo3#si_mi0#n_ss_out#clk_for_lpbk#n_ss_out_upper#mo_upper[0]#mo_upper[1]#mo_upper[2]#mo_upper[3]#sclk_out_upper#gpio0[13]#scl_out#sda_out#scl_out#sda_out#rxd#txd#txd#rxd#gpio0[22]#gpio0[23]#phy_tx#phy_rx#gpi[0]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#gpo[0]#gpo[1]#gpo[2]#gpo[3]#gpo[4]#gpo[5]#gpio1[38]#sdio1_data_out[4]#sdio1_data_out[5]#sdio1_data_out[6]#sdio1_data_out[7]#sdio1_bus_pow#sdio1_wp#sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out} \
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CONFIG.PSU_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Feedback Clk#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO0 MIO#I2C 0#I2C 0#I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1#GPIO0 MIO#GPIO0 MIO#CAN 1#CAN 1#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#PCIE#PMU GPO 0#PMU GPO 1#PMU GPO 2#PMU GPO 3#PMU GPO 4#PMU GPO 5#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO 3} \
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CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#so_mo1#mo2#mo3#si_mi0#n_ss_out#clk_for_lpbk#n_ss_out_upper#mo_upper[0]#mo_upper[1]#mo_upper[2]#mo_upper[3]#sclk_out_upper#gpio0[13]#scl_out#sda_out#scl_out#sda_out#rxd#txd#txd#rxd#gpio0[22]#gpio0[23]#phy_tx#phy_rx#gpio1[26]#gpio1[27]#gpio1[28]#gpio1[29]#gpio1[30]#reset_n#gpo[0]#gpo[1]#gpo[2]#gpo[3]#gpo[4]#gpo[5]#gpio1[38]#sdio1_data_out[4]#sdio1_data_out[5]#sdio1_data_out[6]#sdio1_data_out[7]#sdio1_bus_pow#sdio1_wp#sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out} \
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CONFIG.PSU_UIPARAM_GENERATE_SUMMARY {<Select>} \
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CONFIG.PSU__ACPU0__POWER__ON {1} \
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CONFIG.PSU__ACPU1__POWER__ON {1} \
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@ -705,7 +633,7 @@ CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
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CONFIG.PSU__CAN1__GRP_CLK__IO {<Select>} \
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CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {1} \
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CONFIG.PSU__CAN1__PERIPHERAL__IO {MIO 24 .. 25} \
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CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1199.988037} \
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CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1199.988} \
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CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \
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CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \
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CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
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@ -741,7 +669,7 @@ CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL {DPLL} \
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CONFIG.PSU__CRF_APB__AFI5_REF__ENABLE {0} \
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CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \
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CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \
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CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0.000} \
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CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0.000000} \
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CONFIG.PSU__CRF_APB__APLL_CTRL__FRACFREQ {27.138} \
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CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
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CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \
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@ -750,80 +678,80 @@ CONFIG.PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ {1} \
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CONFIG.PSU__CRF_APB__APM_CTRL__DIVISOR0 {1} \
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CONFIG.PSU__CRF_APB__APM_CTRL__FREQMHZ {1} \
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CONFIG.PSU__CRF_APB__APM_CTRL__SRCSEL {<Select>} \
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CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {249.997498} \
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CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {249.997} \
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CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \
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CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \
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CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
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CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ {250} \
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CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {2} \
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CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {5} \
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CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \
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CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
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CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {249.997498} \
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CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {249.997} \
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CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \
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CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \
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CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
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CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {533.328003} \
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CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {533.328} \
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CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {2} \
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CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1067} \
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CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
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CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {599.994019} \
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CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {599.994} \
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CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \
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CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \
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CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
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CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
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CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {64} \
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CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0.000} \
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CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0.000000} \
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CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACFREQ {27.138} \
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CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
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CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \
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CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {3} \
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CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {24.575823} \
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CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {39} \
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CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {2} \
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CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {25} \
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CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {64} \
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CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \
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CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ {25} \
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CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {VPLL} \
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CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {23.529177} \
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CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {17} \
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CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \
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CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {27} \
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CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {6} \
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CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {10} \
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CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ {27} \
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CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
|
||||
CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {133.332001} \
|
||||
CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {3} \
|
||||
CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {320} \
|
||||
CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {5} \
|
||||
CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \
|
||||
CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ {320} \
|
||||
CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {RPLL} \
|
||||
CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {599.994019} \
|
||||
CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {599.994} \
|
||||
CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \
|
||||
CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \
|
||||
CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
|
||||
CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {499.994995} \
|
||||
CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {499.995} \
|
||||
CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {1} \
|
||||
CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {600} \
|
||||
CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
|
||||
CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ {250} \
|
||||
CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ {249.997} \
|
||||
CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {2} \
|
||||
CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ {250} \
|
||||
CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \
|
||||
CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {249.997498} \
|
||||
CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {249.997} \
|
||||
CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \
|
||||
CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \
|
||||
CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
|
||||
CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {99.998999} \
|
||||
CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {99.999} \
|
||||
CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \
|
||||
CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \
|
||||
CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
|
||||
CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {479.228546} \
|
||||
CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \
|
||||
CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {497.530} \
|
||||
CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {3} \
|
||||
CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.33} \
|
||||
CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {VPLL} \
|
||||
CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \
|
||||
CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {57} \
|
||||
CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.508} \
|
||||
CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {89} \
|
||||
CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.556290} \
|
||||
CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {27.138} \
|
||||
CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
|
||||
CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {1} \
|
||||
CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \
|
||||
CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {499.994995} \
|
||||
CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {499.995} \
|
||||
CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \
|
||||
CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \
|
||||
CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
|
||||
@ -832,7 +760,7 @@ CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \
|
||||
CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ {500} \
|
||||
CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL {IOPLL} \
|
||||
CONFIG.PSU__CRL_APB__AFI6__ENABLE {0} \
|
||||
CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {51.723620} \
|
||||
CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {51.724} \
|
||||
CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {29} \
|
||||
CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \
|
||||
CONFIG.PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ {52} \
|
||||
@ -842,12 +770,12 @@ CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \
|
||||
CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \
|
||||
CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ {100} \
|
||||
CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \
|
||||
CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {99.998999} \
|
||||
CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {99.999} \
|
||||
CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \
|
||||
CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \
|
||||
CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \
|
||||
CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
|
||||
CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {499.994995} \
|
||||
CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {499.995} \
|
||||
CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
|
||||
CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \
|
||||
CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
|
||||
@ -855,7 +783,7 @@ CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {500} \
|
||||
CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {3} \
|
||||
CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {400} \
|
||||
CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {RPLL} \
|
||||
CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {249.997498} \
|
||||
CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {249.997} \
|
||||
CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \
|
||||
CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \
|
||||
CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
|
||||
@ -881,42 +809,42 @@ CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \
|
||||
CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \
|
||||
CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ {125} \
|
||||
CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \
|
||||
CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {124.998749} \
|
||||
CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {124.999} \
|
||||
CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \
|
||||
CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \
|
||||
CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \
|
||||
CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
|
||||
CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {250} \
|
||||
CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \
|
||||
CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {4} \
|
||||
CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \
|
||||
CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ {250} \
|
||||
CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \
|
||||
CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {99.998999} \
|
||||
CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {99.999} \
|
||||
CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \
|
||||
CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \
|
||||
CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \
|
||||
CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
|
||||
CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {99.998999} \
|
||||
CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {99.999} \
|
||||
CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \
|
||||
CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \
|
||||
CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \
|
||||
CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
|
||||
CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {0} \
|
||||
CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {45} \
|
||||
CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0.000} \
|
||||
CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {1} \
|
||||
CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {90} \
|
||||
CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0.000000} \
|
||||
CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACFREQ {27.138} \
|
||||
CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
|
||||
CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \
|
||||
CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \
|
||||
CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {249.997498} \
|
||||
CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {249.997} \
|
||||
CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \
|
||||
CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {267} \
|
||||
CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
|
||||
CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {99.998999} \
|
||||
CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {99.999} \
|
||||
CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \
|
||||
CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \
|
||||
CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
|
||||
CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {499.994995} \
|
||||
CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {499.995} \
|
||||
CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \
|
||||
CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \
|
||||
CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
|
||||
@ -929,77 +857,77 @@ CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ {500} \
|
||||
CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0 {3} \
|
||||
CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ {500} \
|
||||
CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL {IOPLL} \
|
||||
CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {199.998006} \
|
||||
CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {166.665} \
|
||||
CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {6} \
|
||||
CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {167} \
|
||||
CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {RPLL} \
|
||||
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {99.998999} \
|
||||
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {99.999} \
|
||||
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \
|
||||
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \
|
||||
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {100} \
|
||||
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
|
||||
CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {24.999750} \
|
||||
CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {99.999} \
|
||||
CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {15} \
|
||||
CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {4} \
|
||||
CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {1} \
|
||||
CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {100} \
|
||||
CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {IOPLL} \
|
||||
CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {299.997009} \
|
||||
CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {4} \
|
||||
CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {99.999} \
|
||||
CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {10} \
|
||||
CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \
|
||||
CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {300} \
|
||||
CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {100} \
|
||||
CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {RPLL} \
|
||||
CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {399.996012} \
|
||||
CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {3} \
|
||||
CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {99.999} \
|
||||
CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {10} \
|
||||
CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \
|
||||
CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {100} \
|
||||
CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {RPLL} \
|
||||
CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {124.998749} \
|
||||
CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \
|
||||
CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {299.997} \
|
||||
CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {5} \
|
||||
CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \
|
||||
CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {300} \
|
||||
CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
|
||||
CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \
|
||||
CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {72} \
|
||||
CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.000} \
|
||||
CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {60} \
|
||||
CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.000000} \
|
||||
CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {27.138} \
|
||||
CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
|
||||
CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {0} \
|
||||
CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {3} \
|
||||
CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {2} \
|
||||
CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {200} \
|
||||
CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {6} \
|
||||
CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {7} \
|
||||
CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \
|
||||
CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ {200} \
|
||||
CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {RPLL} \
|
||||
CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {199.998006} \
|
||||
CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {6} \
|
||||
CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {199.998} \
|
||||
CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {5} \
|
||||
CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \
|
||||
CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \
|
||||
CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {RPLL} \
|
||||
CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {214} \
|
||||
CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {6} \
|
||||
CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {7} \
|
||||
CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \
|
||||
CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ {200} \
|
||||
CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {RPLL} \
|
||||
CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {214} \
|
||||
CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {6} \
|
||||
CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {7} \
|
||||
CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \
|
||||
CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ {200} \
|
||||
CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {RPLL} \
|
||||
CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {99.998999} \
|
||||
CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \
|
||||
CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {33.333000} \
|
||||
CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {1} \
|
||||
CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \
|
||||
CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \
|
||||
CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {99.998999} \
|
||||
CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {PSS_REF_CLK} \
|
||||
CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {99.999} \
|
||||
CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \
|
||||
CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \
|
||||
CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \
|
||||
CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
|
||||
CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {99.998999} \
|
||||
CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {99.999} \
|
||||
CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \
|
||||
CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \
|
||||
CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \
|
||||
CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
|
||||
CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {249.997498} \
|
||||
CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {249.997} \
|
||||
CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \
|
||||
CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \
|
||||
CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \
|
||||
@ -1009,9 +937,9 @@ CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \
|
||||
CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \
|
||||
CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ {250} \
|
||||
CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \
|
||||
CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {19.999800} \
|
||||
CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {5} \
|
||||
CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {15} \
|
||||
CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000} \
|
||||
CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {25} \
|
||||
CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {3} \
|
||||
CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \
|
||||
CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
|
||||
CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
|
||||
@ -1103,9 +1031,9 @@ CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
|
||||
CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
|
||||
CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
|
||||
CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
|
||||
CONFIG.PSU__DDRC__T_FAW {21.0} \
|
||||
CONFIG.PSU__DDRC__T_FAW {30.0} \
|
||||
CONFIG.PSU__DDRC__T_RAS_MIN {33} \
|
||||
CONFIG.PSU__DDRC__T_RC {46.5} \
|
||||
CONFIG.PSU__DDRC__T_RC {47.06} \
|
||||
CONFIG.PSU__DDRC__T_RCD {15} \
|
||||
CONFIG.PSU__DDRC__T_RP {15} \
|
||||
CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \
|
||||
@ -1114,16 +1042,16 @@ CONFIG.PSU__DDRC__VREF {1} \
|
||||
CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {1} \
|
||||
CONFIG.PSU__DDR__INTERFACE__FREQMHZ {533.500} \
|
||||
CONFIG.PSU__DEVICE_TYPE {EG} \
|
||||
CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \
|
||||
CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \
|
||||
CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \
|
||||
CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \
|
||||
CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \
|
||||
CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \
|
||||
CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \
|
||||
CONFIG.PSU__DP__LANE_SEL {Dual Lower} \
|
||||
CONFIG.PSU__DP__REF_CLK_FREQ {27} \
|
||||
CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk3} \
|
||||
CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {0} \
|
||||
CONFIG.PSU__DISPLAYPORT__LANE0__IO {<Select>} \
|
||||
CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {0} \
|
||||
CONFIG.PSU__DISPLAYPORT__LANE1__IO {<Select>} \
|
||||
CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {0} \
|
||||
CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {0} \
|
||||
CONFIG.PSU__DPAUX__PERIPHERAL__IO {<Select>} \
|
||||
CONFIG.PSU__DP__LANE_SEL {<Select>} \
|
||||
CONFIG.PSU__DP__REF_CLK_FREQ {<Select>} \
|
||||
CONFIG.PSU__DP__REF_CLK_SEL {<Select>} \
|
||||
CONFIG.PSU__ENET0__GRP_MDIO__ENABLE {0} \
|
||||
CONFIG.PSU__ENET0__GRP_MDIO__IO {<Select>} \
|
||||
CONFIG.PSU__ENET0__PERIPHERAL__ENABLE {0} \
|
||||
@ -1140,8 +1068,8 @@ CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \
|
||||
CONFIG.PSU__ENET3__GRP_MDIO__IO {MIO 76 .. 77} \
|
||||
CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \
|
||||
CONFIG.PSU__ENET3__PERIPHERAL__IO {MIO 64 .. 75} \
|
||||
CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100} \
|
||||
CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {100} \
|
||||
CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {99.999001} \
|
||||
CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {99.999001} \
|
||||
CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \
|
||||
CONFIG.PSU__FPGA_PL0_ENABLE {1} \
|
||||
CONFIG.PSU__FPGA_PL1_ENABLE {1} \
|
||||
@ -1175,16 +1103,13 @@ CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \
|
||||
CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \
|
||||
CONFIG.PSU__GPIO2_MIO__IO {<Select>} \
|
||||
CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {0} \
|
||||
CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {1} \
|
||||
CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {0} \
|
||||
CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO {<Select>} \
|
||||
CONFIG.PSU__GPIO_EMIO__WIDTH {[94:0]} \
|
||||
CONFIG.PSU__GPU_PP0__POWER__ON {1} \
|
||||
CONFIG.PSU__GPU_PP1__POWER__ON {1} \
|
||||
CONFIG.PSU__GT_REF_CLK__FREQMHZ {33.333} \
|
||||
CONFIG.PSU__GT__LINK_SPEED {HBR} \
|
||||
CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \
|
||||
CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \
|
||||
CONFIG.PSU__HIGH_ADDRESS__ENABLE {1} \
|
||||
CONFIG.PSU__GT__LINK_SPEED {<Select>} \
|
||||
CONFIG.PSU__I2C0_LOOP_I2C1__ENABLE {0} \
|
||||
CONFIG.PSU__I2C0__GRP_INT__ENABLE {0} \
|
||||
CONFIG.PSU__I2C0__GRP_INT__IO {<Select>} \
|
||||
@ -1200,12 +1125,12 @@ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \
|
||||
CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \
|
||||
CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \
|
||||
CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100.000000} \
|
||||
CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100} \
|
||||
CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100} \
|
||||
CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100} \
|
||||
CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100} \
|
||||
CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100} \
|
||||
CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100} \
|
||||
CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \
|
||||
CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100.000000} \
|
||||
CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \
|
||||
CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100.000000} \
|
||||
CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \
|
||||
CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100.000000} \
|
||||
CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {99.999001} \
|
||||
CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {99.999001} \
|
||||
CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \
|
||||
@ -1222,7 +1147,7 @@ CONFIG.PSU__OCM_BANK0__POWER__ON {1} \
|
||||
CONFIG.PSU__OCM_BANK1__POWER__ON {1} \
|
||||
CONFIG.PSU__OCM_BANK2__POWER__ON {1} \
|
||||
CONFIG.PSU__OCM_BANK3__POWER__ON {1} \
|
||||
CONFIG.PSU__OVERRIDE__BASIC_CLOCK {1} \
|
||||
CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \
|
||||
CONFIG.PSU__PCIE__ACS_VIOLATION {0} \
|
||||
CONFIG.PSU__PCIE__AER_CAPABILITY {0} \
|
||||
CONFIG.PSU__PCIE__ATOMICOP_EGRESS_BLOCKED {0} \
|
||||
@ -1232,68 +1157,80 @@ CONFIG.PSU__PCIE__BAR0_PREFETCHABLE {0} \
|
||||
CONFIG.PSU__PCIE__BAR0_SCALE {<Select>} \
|
||||
CONFIG.PSU__PCIE__BAR0_SIZE {<Select>} \
|
||||
CONFIG.PSU__PCIE__BAR0_TYPE {<Select>} \
|
||||
CONFIG.PSU__PCIE__BAR0_VAL {0x0} \
|
||||
CONFIG.PSU__PCIE__BAR1_64BIT {0} \
|
||||
CONFIG.PSU__PCIE__BAR1_ENABLE {0} \
|
||||
CONFIG.PSU__PCIE__BAR1_PREFETCHABLE {0} \
|
||||
CONFIG.PSU__PCIE__BAR1_SCALE {<Select>} \
|
||||
CONFIG.PSU__PCIE__BAR1_SIZE {<Select>} \
|
||||
CONFIG.PSU__PCIE__BAR1_TYPE {<Select>} \
|
||||
CONFIG.PSU__PCIE__BAR1_VAL {0x0} \
|
||||
CONFIG.PSU__PCIE__BAR2_64BIT {0} \
|
||||
CONFIG.PSU__PCIE__BAR2_ENABLE {0} \
|
||||
CONFIG.PSU__PCIE__BAR2_PREFETCHABLE {0} \
|
||||
CONFIG.PSU__PCIE__BAR2_SCALE {<Select>} \
|
||||
CONFIG.PSU__PCIE__BAR2_SIZE {<Select>} \
|
||||
CONFIG.PSU__PCIE__BAR2_TYPE {<Select>} \
|
||||
CONFIG.PSU__PCIE__BAR2_VAL {0x0} \
|
||||
CONFIG.PSU__PCIE__BAR3_64BIT {0} \
|
||||
CONFIG.PSU__PCIE__BAR3_ENABLE {0} \
|
||||
CONFIG.PSU__PCIE__BAR3_PREFETCHABLE {0} \
|
||||
CONFIG.PSU__PCIE__BAR3_SCALE {<Select>} \
|
||||
CONFIG.PSU__PCIE__BAR3_SIZE {<Select>} \
|
||||
CONFIG.PSU__PCIE__BAR3_TYPE {<Select>} \
|
||||
CONFIG.PSU__PCIE__BAR3_VAL {0x0} \
|
||||
CONFIG.PSU__PCIE__BAR4_64BIT {0} \
|
||||
CONFIG.PSU__PCIE__BAR4_ENABLE {0} \
|
||||
CONFIG.PSU__PCIE__BAR4_PREFETCHABLE {0} \
|
||||
CONFIG.PSU__PCIE__BAR4_SCALE {<Select>} \
|
||||
CONFIG.PSU__PCIE__BAR4_SIZE {<Select>} \
|
||||
CONFIG.PSU__PCIE__BAR4_TYPE {<Select>} \
|
||||
CONFIG.PSU__PCIE__BAR4_VAL {0x0} \
|
||||
CONFIG.PSU__PCIE__BAR5_64BIT {0} \
|
||||
CONFIG.PSU__PCIE__BAR5_ENABLE {0} \
|
||||
CONFIG.PSU__PCIE__BAR5_PREFETCHABLE {0} \
|
||||
CONFIG.PSU__PCIE__BAR5_SCALE {<Select>} \
|
||||
CONFIG.PSU__PCIE__BAR5_SIZE {<Select>} \
|
||||
CONFIG.PSU__PCIE__BAR5_TYPE {<Select>} \
|
||||
CONFIG.PSU__PCIE__BAR5_VAL {0x0} \
|
||||
CONFIG.PSU__PCIE__BASE_CLASS_MENU {<Select>} \
|
||||
CONFIG.PSU__PCIE__BRIDGE_BAR_INDICATOR {<Select>} \
|
||||
CONFIG.PSU__PCIE__CAP_SLOT_IMPLEMENTED {<Select>} \
|
||||
CONFIG.PSU__PCIE__CLASS_CODE_BASE {0x06} \
|
||||
CONFIG.PSU__PCIE__CLASS_CODE_INTERFACE {0x0} \
|
||||
CONFIG.PSU__PCIE__CLASS_CODE_SUB {0x4} \
|
||||
CONFIG.PSU__PCIE__CLASS_CODE_VALUE {0x60400} \
|
||||
CONFIG.PSU__PCIE__COMPLETER_ABORT {0} \
|
||||
CONFIG.PSU__PCIE__COMPLTION_TIMEOUT {0} \
|
||||
CONFIG.PSU__PCIE__CORRECTABLE_INT_ERR {0} \
|
||||
CONFIG.PSU__PCIE__CRS_SW_VISIBILITY {0} \
|
||||
CONFIG.PSU__PCIE__DEVICE_PORT_TYPE {<Select>} \
|
||||
CONFIG.PSU__PCIE__CRS_SW_VISIBILITY {1} \
|
||||
CONFIG.PSU__PCIE__DEVICE_ID {0xD022} \
|
||||
CONFIG.PSU__PCIE__DEVICE_PORT_TYPE {Root Port} \
|
||||
CONFIG.PSU__PCIE__ECRC_CHECK {0} \
|
||||
CONFIG.PSU__PCIE__ECRC_ERR {0} \
|
||||
CONFIG.PSU__PCIE__ECRC_GEN {0} \
|
||||
CONFIG.PSU__PCIE__EROM_ENABLE {0} \
|
||||
CONFIG.PSU__PCIE__EROM_SCALE {<Select>} \
|
||||
CONFIG.PSU__PCIE__EROM_SIZE {<Select>} \
|
||||
CONFIG.PSU__PCIE__EROM_VAL {0x0} \
|
||||
CONFIG.PSU__PCIE__FLOW_CONTROL_ERR {0} \
|
||||
CONFIG.PSU__PCIE__FLOW_CONTROL_PROTOCOL_ERR {0} \
|
||||
CONFIG.PSU__PCIE__HEADER_LOG_OVERFLOW {0} \
|
||||
CONFIG.PSU__PCIE__INTERFACE_WIDTH {<Select>} \
|
||||
CONFIG.PSU__PCIE__INTX_GENERATION {0} \
|
||||
CONFIG.PSU__PCIE__INTX_PIN {<Select>} \
|
||||
CONFIG.PSU__PCIE__LANE0__ENABLE {0} \
|
||||
CONFIG.PSU__PCIE__LANE0__IO {<Select>} \
|
||||
CONFIG.PSU__PCIE__LANE1__ENABLE {0} \
|
||||
CONFIG.PSU__PCIE__LANE1__IO {<Select>} \
|
||||
CONFIG.PSU__PCIE__LANE0__ENABLE {1} \
|
||||
CONFIG.PSU__PCIE__LANE0__IO {GT Lane0} \
|
||||
CONFIG.PSU__PCIE__LANE1__ENABLE {1} \
|
||||
CONFIG.PSU__PCIE__LANE1__IO {GT Lane1} \
|
||||
CONFIG.PSU__PCIE__LANE2__ENABLE {0} \
|
||||
CONFIG.PSU__PCIE__LANE2__IO {<Select>} \
|
||||
CONFIG.PSU__PCIE__LANE3__ENABLE {0} \
|
||||
CONFIG.PSU__PCIE__LANE3__IO {<Select>} \
|
||||
CONFIG.PSU__PCIE__LEGACY_INTERRUPT {<Select>} \
|
||||
CONFIG.PSU__PCIE__LINK_SPEED {<Select>} \
|
||||
CONFIG.PSU__PCIE__MAXIMUM_LINK_WIDTH {<Select>} \
|
||||
CONFIG.PSU__PCIE__MAX_PAYLOAD_SIZE {<Select>} \
|
||||
CONFIG.PSU__PCIE__LINK_SPEED {5.0 Gb/s} \
|
||||
CONFIG.PSU__PCIE__MAXIMUM_LINK_WIDTH {x2} \
|
||||
CONFIG.PSU__PCIE__MAX_PAYLOAD_SIZE {256 bytes} \
|
||||
CONFIG.PSU__PCIE__MC_BLOCKED_TLP {0} \
|
||||
CONFIG.PSU__PCIE__MSIX_CAPABILITY {0} \
|
||||
CONFIG.PSU__PCIE__MSIX_PBA_OFFSET {0} \
|
||||
@ -1303,21 +1240,25 @@ CONFIG.PSU__PCIE__MSI_64BIT_ADDR_CAPABLE {0} \
|
||||
CONFIG.PSU__PCIE__MSI_CAPABILITY {0} \
|
||||
CONFIG.PSU__PCIE__MSI_MULTIPLE_MSG_CAPABLE {<Select>} \
|
||||
CONFIG.PSU__PCIE__MULTIHEADER {0} \
|
||||
CONFIG.PSU__PCIE__PERIPHERAL__ENABLE {0} \
|
||||
CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE {1} \
|
||||
CONFIG.PSU__PCIE__PERIPHERAL__ENABLE {1} \
|
||||
CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE {0} \
|
||||
CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_IO {<Select>} \
|
||||
CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE {0} \
|
||||
CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_IO {<Select>} \
|
||||
CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE {1} \
|
||||
CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_IO {MIO 31} \
|
||||
CONFIG.PSU__PCIE__PERM_ROOT_ERR_UPDATE {0} \
|
||||
CONFIG.PSU__PCIE__RECEIVER_ERR {0} \
|
||||
CONFIG.PSU__PCIE__RECEIVER_OVERFLOW {0} \
|
||||
CONFIG.PSU__PCIE__REF_CLK_FREQ {<Select>} \
|
||||
CONFIG.PSU__PCIE__REF_CLK_SEL {<Select>} \
|
||||
CONFIG.PSU__PCIE__REF_CLK_FREQ {100} \
|
||||
CONFIG.PSU__PCIE__REF_CLK_SEL {Ref Clk0} \
|
||||
CONFIG.PSU__PCIE__REVISION_ID {0x0} \
|
||||
CONFIG.PSU__PCIE__SUBSYSTEM_ID {0x7} \
|
||||
CONFIG.PSU__PCIE__SUBSYSTEM_VENDOR_ID {0x10EE} \
|
||||
CONFIG.PSU__PCIE__SUB_CLASS_INTERFACE_MENU {<Select>} \
|
||||
CONFIG.PSU__PCIE__SURPRISE_DOWN {0} \
|
||||
CONFIG.PSU__PCIE__TLP_PREFIX_BLOCKED {0} \
|
||||
CONFIG.PSU__PCIE__UNCORRECTABL_INT_ERR {0} \
|
||||
CONFIG.PSU__PCIE__USE_CLASS_CODE_LOOKUP_ASSISTANT {<Select>} \
|
||||
CONFIG.PSU__PCIE__VENDOR_ID {0x10EE} \
|
||||
CONFIG.PSU__PJTAG__PERIPHERAL__ENABLE {0} \
|
||||
CONFIG.PSU__PJTAG__PERIPHERAL__IO {<Select>} \
|
||||
CONFIG.PSU__PL_CLK0_BUF {TRUE} \
|
||||
@ -1327,8 +1268,8 @@ CONFIG.PSU__PL_CLK3_BUF {TRUE} \
|
||||
CONFIG.PSU__PL__POWER__ON {1} \
|
||||
CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \
|
||||
CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \
|
||||
CONFIG.PSU__PMU__GPI0__ENABLE {1} \
|
||||
CONFIG.PSU__PMU__GPI0__IO {MIO 26} \
|
||||
CONFIG.PSU__PMU__GPI0__ENABLE {0} \
|
||||
CONFIG.PSU__PMU__GPI0__IO {<Select>} \
|
||||
CONFIG.PSU__PMU__GPI1__ENABLE {0} \
|
||||
CONFIG.PSU__PMU__GPI1__IO {<Select>} \
|
||||
CONFIG.PSU__PMU__GPI2__ENABLE {0} \
|
||||
@ -1354,8 +1295,8 @@ CONFIG.PSU__PMU__GPO5__IO {MIO 37} \
|
||||
CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \
|
||||
CONFIG.PSU__PMU__PERIPHERAL__IO {<Select>} \
|
||||
CONFIG.PSU__PROTECTION__DEBUG {1} \
|
||||
CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;1|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:Secure;1|SD0:Secure;0|SATA1:NonSecure;1|SATA0:NonSecure;1|RPU1:Secure;1|RPU0:Secure;1|QSPI:Secure;1|PMU:NA;1|PCIe:NonSecure;0|NAND:Secure;0|LDMA:NA;1|GPU:Secure;1|GEM3:Secure;1|GEM2:Secure;0|GEM1:Secure;0|GEM0:Secure;0|FDMA:NA;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \
|
||||
CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;0|LPD;TTC2;FF130000;FF13FFFF;0|LPD;TTC1;FF120000;FF12FFFF;0|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;0|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;1|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|FPD;RCPU_GIC;F9000000;F900FFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PUF;FFC30000;FFC3FFFF;1|LPD;PMU_RAM;FFDC0000;FFDFFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LDMA_7;FFAF0000;FFAFFFFF;1|LPD;LDMA_6;FFAE0000;FFAEFFFF;1|LPD;LDMA_5;FFAD0000;FFADFFFF;1|LPD;LDMA_4;FFAC0000;FFACFFFF;1|LPD;LDMA_3;FFAB0000;FFABFFFF;1|LPD;LDMA_2;FFAA0000;FFAAFFFF;1|LPD;LDMA_1;FFA90000;FFA9FFFF;1|LPD;LDMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;GDMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_GPV;FD700000;FD7FFFFF;1|FPD;FDMA_CH6;FD560000;FD56FFFF;1|FPD;FDMA_CH5;FD550000;FD55FFFF;1|FPD;FDMA_CH4;FD540000;FD54FFFF;1|FPD;FDMA_CH3;FD530000;FD53FFFF;1|FPD;FDMA_CH2;FD520000;FD52FFFF;1|FPD;FDMA_CH1;FD510000;FD51FFFF;1|FPD;FDMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;87FFFFFFF;1|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_WDT;FFCB0000;FFCBFFFF;1|LPD;CSU_ROM;FFC00000;FFC1FFFF;1|LPD;CSU_RAM;FFC40000;FFC5FFFF;1|LPD;CSU_LOCAL;FFC20000;FFC2FFFF;1|LPD;CSU_IOMODULE;FFC60000;FFC7FFFF;1|LPD;CSUDMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;0|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|FPD;CCI_GPV;FD6E0000;FD6EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;1|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9000000;F907FFFF;1} \
|
||||
CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;1|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:Secure;1|SD0:Secure;0|SATA1:NonSecure;1|SATA0:NonSecure;1|RPU1:Secure;1|RPU0:Secure;1|QSPI:Secure;1|PMU:NA;1|PCIe:NonSecure;1|NAND:Secure;0|LDMA:NA;1|GPU:Secure;1|GEM3:Secure;1|GEM2:Secure;0|GEM1:Secure;0|GEM0:Secure;0|FDMA:NA;1|DP:NonSecure;0|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \
|
||||
CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;1|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|FPD;RCPU_GIC;F9000000;F900FFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PUF;FFC30000;FFC3FFFF;1|LPD;PMU_RAM;FFDC0000;FFDFFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;1|FPD;PCIE_LOW;E0000000;EFFFFFFF;1|FPD;PCIE_HIGH;600000000;7FFFFFFFF;1|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;1|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LDMA_7;FFAF0000;FFAFFFFF;1|LPD;LDMA_6;FFAE0000;FFAEFFFF;1|LPD;LDMA_5;FFAD0000;FFADFFFF;1|LPD;LDMA_4;FFAC0000;FFACFFFF;1|LPD;LDMA_3;FFAB0000;FFABFFFF;1|LPD;LDMA_2;FFAA0000;FFAAFFFF;1|LPD;LDMA_1;FFA90000;FFA9FFFF;1|LPD;LDMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;GDMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_GPV;FD700000;FD7FFFFF;1|FPD;FDMA_CH6;FD560000;FD56FFFF;1|FPD;FDMA_CH5;FD550000;FD55FFFF;1|FPD;FDMA_CH4;FD540000;FD54FFFF;1|FPD;FDMA_CH3;FD530000;FD53FFFF;1|FPD;FDMA_CH2;FD520000;FD52FFFF;1|FPD;FDMA_CH1;FD510000;FD51FFFF;1|FPD;FDMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;0|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;87FFFFFFF;1|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_WDT;FFCB0000;FFCBFFFF;1|LPD;CSU_ROM;FFC00000;FFC1FFFF;1|LPD;CSU_RAM;FFC40000;FFC5FFFF;1|LPD;CSU_LOCAL;FFC20000;FFC2FFFF;1|LPD;CSU_IOMODULE;FFC60000;FFC7FFFF;1|LPD;CSUDMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;0|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|FPD;CCI_GPV;FD6E0000;FD6EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;1|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9000000;F907FFFF;1} \
|
||||
CONFIG.PSU__PSS_ALT_REF_CLK__ENABLE {0} \
|
||||
CONFIG.PSU__PSS_ALT_REF_CLK__FREQMHZ {33.333} \
|
||||
CONFIG.PSU__PSS_ALT_REF_CLK__IO {<Select>} \
|
||||
@ -1372,7 +1313,7 @@ CONFIG.PSU__SATA__LANE0__IO {<Select>} \
|
||||
CONFIG.PSU__SATA__LANE1__ENABLE {1} \
|
||||
CONFIG.PSU__SATA__LANE1__IO {GT Lane3} \
|
||||
CONFIG.PSU__SATA__PERIPHERAL__ENABLE {1} \
|
||||
CONFIG.PSU__SATA__REF_CLK_FREQ {150} \
|
||||
CONFIG.PSU__SATA__REF_CLK_FREQ {125} \
|
||||
CONFIG.PSU__SATA__REF_CLK_SEL {Ref Clk1} \
|
||||
CONFIG.PSU__SD0__DATA_TRANSFER_MODE {<Select>} \
|
||||
CONFIG.PSU__SD0__GRP_CD__ENABLE {0} \
|
||||
@ -1421,7 +1362,8 @@ CONFIG.PSU__SWDT0__RESET__ENABLE {0} \
|
||||
CONFIG.PSU__SWDT0__RESET__IO {<Select>} \
|
||||
CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \
|
||||
CONFIG.PSU__SWDT1__CLOCK__IO {<Select>} \
|
||||
CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {0} \
|
||||
CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
|
||||
CONFIG.PSU__SWDT1__PERIPHERAL__IO {EMIO} \
|
||||
CONFIG.PSU__SWDT1__RESET__ENABLE {0} \
|
||||
CONFIG.PSU__SWDT1__RESET__IO {<Select>} \
|
||||
CONFIG.PSU__TCM0A__POWER__ON {1} \
|
||||
@ -1440,17 +1382,20 @@ CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \
|
||||
CONFIG.PSU__TTC0__WAVEOUT__IO {<Select>} \
|
||||
CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \
|
||||
CONFIG.PSU__TTC1__CLOCK__IO {<Select>} \
|
||||
CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {0} \
|
||||
CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
|
||||
CONFIG.PSU__TTC1__PERIPHERAL__IO {EMIO} \
|
||||
CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \
|
||||
CONFIG.PSU__TTC1__WAVEOUT__IO {<Select>} \
|
||||
CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \
|
||||
CONFIG.PSU__TTC2__CLOCK__IO {<Select>} \
|
||||
CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {0} \
|
||||
CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
|
||||
CONFIG.PSU__TTC2__PERIPHERAL__IO {EMIO} \
|
||||
CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \
|
||||
CONFIG.PSU__TTC2__WAVEOUT__IO {<Select>} \
|
||||
CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \
|
||||
CONFIG.PSU__TTC3__CLOCK__IO {<Select>} \
|
||||
CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {0} \
|
||||
CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
|
||||
CONFIG.PSU__TTC3__PERIPHERAL__IO {EMIO} \
|
||||
CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \
|
||||
CONFIG.PSU__TTC3__WAVEOUT__IO {<Select>} \
|
||||
CONFIG.PSU__UART0_LOOP_UART1__ENABLE {0} \
|
||||
@ -1954,6 +1899,7 @@ CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA.VALUE_SRC {DEFAULT} \
|
||||
@ -2040,6 +1986,7 @@ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
|
||||
@ -2121,6 +2068,11 @@ CONFIG.PSU__DDRC__PARTNO.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__DDRC__PLL_BYPASS.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__DDRC__PWR_DOWN_EN.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__DDRC__SB_TARGET.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__DDRC__T_FAW.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__DDRC__T_RAS_MIN.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__DDRC__T_RC.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__DDRC__T_RCD.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__DDRC__T_RP.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__DDRC__VENDOR_PART.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__DDRC__VIDEO_BUFFER_SIZE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE.VALUE_SRC {DEFAULT} \
|
||||
@ -2130,6 +2082,12 @@ CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__DISPLAYPORT__LANE0__IO.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__DISPLAYPORT__LANE1__IO.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__DPAUX__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__DP__LANE_SEL.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__DP__REF_CLK_FREQ.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__DP__REF_CLK_SEL.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__ENET0__GRP_MDIO__ENABLE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__ENET0__GRP_MDIO__IO.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__ENET0__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
|
||||
@ -2169,14 +2127,13 @@ CONFIG.PSU__GEN_IPI_8__MASTER.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__GEN_IPI_9__MASTER.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__GPIO2_MIO__IO.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__GPIO_EMIO__WIDTH.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__GPU_PP0__POWER__ON.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__GPU_PP1__POWER__ON.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__GT_REF_CLK__FREQMHZ.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__GT__LINK_SPEED.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__GT__PRE_EMPH_LVL_4.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__GT__VLT_SWNG_LVL_4.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__I2C0_LOOP_I2C1__ENABLE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__I2C0__GRP_INT__ENABLE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__I2C0__GRP_INT__IO.VALUE_SRC {DEFAULT} \
|
||||
@ -2210,76 +2167,77 @@ CONFIG.PSU__OCM_BANK0__POWER__ON.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__OCM_BANK1__POWER__ON.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__OCM_BANK2__POWER__ON.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__OCM_BANK3__POWER__ON.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__OVERRIDE__BASIC_CLOCK.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__ACS_VIOLATION.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__AER_CAPABILITY.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__ATOMICOP_EGRESS_BLOCKED.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__BAR0_64BIT.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__BAR0_ENABLE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__BAR0_PREFETCHABLE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__BAR0_SCALE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__BAR0_SIZE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__BAR0_TYPE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__BAR0_VAL.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__BAR1_64BIT.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__BAR1_ENABLE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__BAR1_PREFETCHABLE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__BAR1_SCALE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__BAR1_SIZE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__BAR1_TYPE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__BAR1_VAL.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__BAR2_64BIT.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__BAR2_ENABLE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__BAR2_PREFETCHABLE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__BAR2_SCALE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__BAR2_SIZE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__BAR2_TYPE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__BAR2_VAL.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__BAR3_64BIT.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__BAR3_ENABLE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__BAR3_PREFETCHABLE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__BAR3_SCALE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__BAR3_SIZE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__BAR3_TYPE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__BAR3_VAL.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__BAR4_64BIT.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__BAR4_ENABLE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__BAR4_PREFETCHABLE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__BAR4_SCALE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__BAR4_SIZE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__BAR4_TYPE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__BAR4_VAL.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__BAR5_64BIT.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__BAR5_ENABLE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__BAR5_PREFETCHABLE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__BAR5_SCALE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__BAR5_SIZE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__BAR5_TYPE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__BAR5_VAL.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__BASE_CLASS_MENU.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__BRIDGE_BAR_INDICATOR.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__CAP_SLOT_IMPLEMENTED.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__CLASS_CODE_INTERFACE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__CLASS_CODE_VALUE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__COMPLETER_ABORT.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__COMPLTION_TIMEOUT.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__CORRECTABLE_INT_ERR.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__CRS_SW_VISIBILITY.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__DEVICE_PORT_TYPE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__ECRC_CHECK.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__ECRC_ERR.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__ECRC_GEN.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__EROM_ENABLE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__EROM_SCALE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__EROM_SIZE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__EROM_VAL.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__FLOW_CONTROL_ERR.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__FLOW_CONTROL_PROTOCOL_ERR.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__HEADER_LOG_OVERFLOW.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__INTERFACE_WIDTH.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__INTX_GENERATION.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__INTX_PIN.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__LANE0__ENABLE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__LANE0__IO.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__LANE1__ENABLE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__LANE1__IO.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__LANE2__ENABLE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__LANE2__IO.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__LANE3__ENABLE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__LANE3__IO.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__LEGACY_INTERRUPT.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__LINK_SPEED.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__MAXIMUM_LINK_WIDTH.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__MAX_PAYLOAD_SIZE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__MC_BLOCKED_TLP.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__MSIX_CAPABILITY.VALUE_SRC {DEFAULT} \
|
||||
@ -2290,21 +2248,21 @@ CONFIG.PSU__PCIE__MSI_64BIT_ADDR_CAPABLE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__MSI_CAPABILITY.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__MSI_MULTIPLE_MSG_CAPABLE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__MULTIHEADER.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_IO.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_IO.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__PERM_ROOT_ERR_UPDATE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__RECEIVER_ERR.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__RECEIVER_OVERFLOW.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__REF_CLK_FREQ.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__REF_CLK_SEL.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__REVISION_ID.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__SUBSYSTEM_ID.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__SUBSYSTEM_VENDOR_ID.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__SUB_CLASS_INTERFACE_MENU.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__SURPRISE_DOWN.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__TLP_PREFIX_BLOCKED.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__UNCORRECTABL_INT_ERR.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__USE_CLASS_CODE_LOOKUP_ASSISTANT.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PCIE__VENDOR_ID.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PJTAG__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PJTAG__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__PL_CLK0_BUF.VALUE_SRC {DEFAULT} \
|
||||
@ -2359,7 +2317,6 @@ CONFIG.PSU__SWDT0__RESET__ENABLE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__SWDT0__RESET__IO.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__SWDT1__CLOCK__ENABLE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__SWDT1__CLOCK__IO.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__SWDT1__RESET__ENABLE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__SWDT1__RESET__IO.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__TCM0A__POWER__ON.VALUE_SRC {DEFAULT} \
|
||||
@ -2376,17 +2333,14 @@ CONFIG.PSU__TTC0__WAVEOUT__ENABLE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__TTC0__WAVEOUT__IO.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__TTC1__CLOCK__ENABLE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__TTC1__CLOCK__IO.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__TTC1__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__TTC1__WAVEOUT__ENABLE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__TTC1__WAVEOUT__IO.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__TTC2__CLOCK__ENABLE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__TTC2__CLOCK__IO.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__TTC2__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__TTC2__WAVEOUT__ENABLE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__TTC2__WAVEOUT__IO.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__TTC3__CLOCK__ENABLE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__TTC3__CLOCK__IO.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__TTC3__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__TTC3__WAVEOUT__ENABLE.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__TTC3__WAVEOUT__IO.VALUE_SRC {DEFAULT} \
|
||||
CONFIG.PSU__UART0_LOOP_UART1__ENABLE.VALUE_SRC {DEFAULT} \
|
||||
@ -2417,7 +2371,6 @@ CONFIG.NUM_MI {1} \
|
||||
] $zynq_ultra_ps_e_0_axi_periph
|
||||
|
||||
# Create interface connections
|
||||
connect_bd_intf_net -intf_net CLK_IN_D_1 [get_bd_intf_ports si570] [get_bd_intf_pins si570_clk/CLK_IN_D]
|
||||
connect_bd_intf_net -intf_net axi_mem_intercon_M00_AXI [get_bd_intf_pins axi_mem_intercon/M00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP1_FPD]
|
||||
connect_bd_intf_net -intf_net zcu102_base_0_m_axi [get_bd_intf_pins axi_mem_intercon/S00_AXI] [get_bd_intf_pins zcu102_base_0/m_axi]
|
||||
connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM1_FPD [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM1_FPD] [get_bd_intf_pins zynq_ultra_ps_e_0_axi_periph/S00_AXI]
|
||||
@ -2441,7 +2394,6 @@ CONFIG.NUM_MI {1} \
|
||||
connect_bd_net -net txi_rd_wait_p_1 [get_bd_ports txi_rd_wait_p] [get_bd_pins zcu102_base_0/txi_rd_wait_p]
|
||||
connect_bd_net -net txi_wr_wait_n_1 [get_bd_ports txi_wr_wait_n] [get_bd_pins zcu102_base_0/txi_wr_wait_n]
|
||||
connect_bd_net -net txi_wr_wait_p_1 [get_bd_ports txi_wr_wait_p] [get_bd_pins zcu102_base_0/txi_wr_wait_p]
|
||||
connect_bd_net -net video_clk_1 [get_bd_pins si570_clk/BUFG_O] [get_bd_pins zynq_ultra_ps_e_0/dp_video_in_clk]
|
||||
connect_bd_net -net zcu102_base_0_cclk0_n [get_bd_ports cclk0_n] [get_bd_pins zcu102_base_0/cclk_n]
|
||||
connect_bd_net -net zcu102_base_0_cclk0_p [get_bd_ports cclk0_p] [get_bd_pins zcu102_base_0/cclk_p]
|
||||
connect_bd_net -net zcu102_base_0_chip_resetb [get_bd_ports chip_nreset] [get_bd_ports clkpd_1p8v] [get_bd_pins zcu102_base_0/chip_nreset]
|
||||
|
||||
@ -7,8 +7,9 @@ set projdir ./
|
||||
#Device name
|
||||
#set partname "xczu9eg-ffvb1156-2L-e-es1"
|
||||
#set partname "xczu9eg-ffvb1156-2L-e-es2"
|
||||
set partname "xczu9eg-ffvb1156-2-i-es2"
|
||||
set board_part "xilinx.com:zcu102:part0:2.0"
|
||||
#set partname "xczu9eg-ffvb1156-2-i-es2"
|
||||
set partname "xczu9eg-ffvb1156-1-i-es2"
|
||||
#set board_part "xilinx.com:zcu102:part0:2.0"
|
||||
|
||||
#Paths to all IP blocks to use in Vivado "system.bd"
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user