diff --git a/elink/dv/dv_elink.v b/elink/dv/dv_elink.v index 792d897..1eb7e50 100644 --- a/elink/dv/dv_elink.v +++ b/elink/dv/dv_elink.v @@ -20,7 +20,7 @@ module dv_elink(/*AUTOARG*/ //Basic - input [CW-1:0] clk; // clocks + input clk; // system clock input reset; // Reset output dut_passed; // Indicates passing test output dut_failed; // Indicates failing test @@ -153,7 +153,7 @@ module dv_elink(/*AUTOARG*/ //Clocks - wire clkin = clk[0]; //for pll-->cclk, rxclk, txclk + wire clkin = clk; //for pll-->cclk, rxclk, txclk @@ -186,7 +186,7 @@ module dv_elink(/*AUTOARG*/ // Outputs .pll_bypass ({clkin,clkin,clkin,clkin}), .pll_clkin (clkin), - .sys_clk (clk[0]), + .sys_clk (clk), .\(.*\) (@"(substring vl-cell-name 0 6)"_\1[]), ); */ @@ -236,7 +236,7 @@ module dv_elink(/*AUTOARG*/ // Inputs .reset (reset), // Templated .pll_clkin (clkin), // Templated - .sys_clk (clk[0]), // Templated + .sys_clk (clk), // Templated .rxwr_wait (elink0_rxwr_wait), // Templated .rxrd_wait (elink0_rxrd_wait), // Templated .rxrr_wait (elink0_rxrr_wait), // Templated @@ -301,7 +301,7 @@ module dv_elink(/*AUTOARG*/ // Inputs .reset (reset), // Templated .pll_clkin (clkin), // Templated - .sys_clk (clk[0]), // Templated + .sys_clk (clk), // Templated .rxwr_wait (elink1_rxwr_wait), // Templated .rxrd_wait (elink1_rxrd_wait), // Templated .rxrr_wait (elink1_rxrr_wait), // Templated @@ -316,20 +316,21 @@ module dv_elink(/*AUTOARG*/ wire elink2_access; wire [PW-1:0] elink2_packet; - fifo_cdc #(.DW(104), .AW(7)) model_fifo( - // Outputs - .wait_out (), - .access_out (elink2_access), - .packet_out (elink2_packet[PW-1:0]), - // Inputs - .clk_in (clk[0]), - .clk_out (clk[0]), - .reset (reset), - .access_in (ext_access), - .packet_in (ext_packet[PW-1:0]), - .wait_in (elink2_wait_out) - ); - + defparam model_fifo.WIDTH=104; + defparam model_fifo.DEPTH=16; + fifo_cdc model_fifo( + // Outputs + .wait_out (), + .access_out (elink2_access), + .packet_out (elink2_packet[PW-1:0]), + // Inputs + .clk_in (clk), + .clk_out (clk), + .reset (reset), + .access_in (ext_access), + .packet_in (ext_packet[PW-1:0]), + .wait_in (elink2_wait_out) + ); elink_e16 elink2 ( // Outputs .rxi_rd_wait (), @@ -348,10 +349,10 @@ module dv_elink(/*AUTOARG*/ .c0_mesh_wait_out (elink2_wait_out), // Inputs .reset (reset), - .c0_clk_in (clk[0]), - .c1_clk_in (clk[0]), - .c2_clk_in (clk[0]), - .c3_clk_in (clk[0]), + .c0_clk_in (clk), + .c1_clk_in (clk), + .c2_clk_in (clk), + .c3_clk_in (clk), .rxi_data (elink0_txo_data_p[7:0]), .rxi_lclk (elink0_txo_lclk_p), .rxi_frame (elink0_txo_frame_p), @@ -367,9 +368,6 @@ module dv_elink(/*AUTOARG*/ ); - - - assign emem_access = (elink1_rxwr_access & ~(elink1_rxwr_packet[39:28]==elink1.ID)) | (elink1_rxrd_access & ~(elink1_rxrd_packet[39:28]==elink1.ID)); @@ -388,7 +386,7 @@ module dv_elink(/*AUTOARG*/ */ ememory emem (.wait_in (1'b0), //only one read at a time, set to zero for no1 - .clk (clk[0]), + .clk (clk), .wait_out (emem_wait), /*AUTOINST*/ // Outputs @@ -415,7 +413,7 @@ module dv_elink(/*AUTOARG*/ emesh_monitor #(.NAME("stimulus")) ext_monitor (.emesh_wait ((dut_rd_wait | dut_wr_wait)),//TODO:fix collisions - .clk (clk[0]), + .clk (clk), /*AUTOINST*/ // Inputs .reset (reset), @@ -425,7 +423,7 @@ module dv_elink(/*AUTOARG*/ .emesh_packet (ext_packet[PW-1:0])); // Templated emesh_monitor #(.NAME("dut")) dut_monitor (.emesh_wait (1'b0), - .clk (clk[0]), + .clk (clk), /*AUTOINST*/ // Inputs .reset (reset), @@ -435,7 +433,7 @@ module dv_elink(/*AUTOARG*/ .emesh_packet (dut_packet[PW-1:0])); // Templated emesh_monitor #(.NAME("emem")) mem_monitor (.emesh_wait (1'b0), - .clk (clk[0]), + .clk (clk), .emesh_access (emem_access), .emesh_packet (emem_packet[PW-1:0]), /*AUTOINST*/ @@ -449,7 +447,7 @@ module dv_elink(/*AUTOARG*/ // Outputs .txopll_bypass ({clkin,clkin,clkin,clkin}), .clkin (clkin), - .sys_clk (clk[0]), + .sys_clk (clk), .\(.*\) (@"(substring vl-cell-name 0 6)"_\1[]), ); */ @@ -462,7 +460,7 @@ module dv_elink(/*AUTOARG*/ .cclk_p (), .cclk_n (), .start (ext_access), - .clk (clk[0]), + .clk (clk), .rxi_lclk_p (txo_lclk_p), .rxi_lclk_n (txo_lclk_n), .rxi_frame_p (txo_frame_p), diff --git a/elink/dv/dv_elink_tb.v b/elink/dv/dv_elink_tb.v index 76f3f74..5ee5e5e 100644 --- a/elink/dv/dv_elink_tb.v +++ b/elink/dv/dv_elink_tb.v @@ -13,7 +13,7 @@ module dv_elink_tb(); /* verilator lint_off STMTDLY */ /* verilator lint_off UNOPTFLAT */ //REGS - reg [1:0] clk; + reg clk; reg reset; reg go; reg [1:0] datamode; @@ -32,7 +32,10 @@ module dv_elink_tb(); reg [MW-1:0] stimarray[MD-1:0]; reg [MW-1:0] transaction; reg [MAW-1:0] stim_addr; - + reg [1:0] state; + reg [31:0] count; + reg start; + integer i; `ifdef MANUAL @@ -48,19 +51,17 @@ module dv_elink_tb(); //Forever clock always - #1 clk[0] = ~clk[0]; //fast clock - always - #50 clk[1] = ~clk[1]; //slow clock - - wire clkstim = clk[1]; + #1 clk = ~clk; //fast clock + + wire clkstim = clk; //Reset initial begin #0 reset = 1'b1; // reset is active - go = 1'b0; - clk[1:0] = 2'b0; + start = 1'b0; + clk = 1'b0; #1000 `ifdef AUTO @@ -73,21 +74,31 @@ module dv_elink_tb(); `endif reset = 1'b0; // at time 100 release reset #4000 - go = 1'b1; - #10000 -`ifdef AUTO - go = 1'b0; -`endif + start = 1'b1; #20000 $finish; end - //Notes:The testbench connects a 64 bit master to a 32 bit slave + +`define IDLE 2'b00 +`define DONE 2'b10 +`define GO 2'b01 + + always @ (posedge clk or posedge reset) + if(reset) + state[1:0] <= `IDLE;//not started + else if(start & (state[1:0]==`IDLE)) + state[1:0] <= `GO;//going + else if( ~(|count) & (state[1:0]==`GO)) + state[1:0] <= `DONE;//gone + + //Notes:The testbench + // connects a 64 bit master to a 32 bit slave //To make this work, we limit the addresses to 64 bit aligned - +//Stimulus Driver always @ (posedge clkstim) - if(reset | ~go) + if(reset) begin ext_access <= 1'b0; //empty ext_write <= 1'b0; @@ -100,10 +111,10 @@ always @ (posedge clkstim) ext_wr_wait <= 1'b0; stim_addr[MAW-1:0] <= 'd0; transaction[MW-1:0] <= 'd0; + count <= `TRANS; end - else if (go & ~(dut_wr_wait|dut_rd_wait)) + else if ((state[1:0]==`GO) & ~(dut_wr_wait|dut_rd_wait)) begin -`ifdef MANUAL transaction[MW-1:0] <= stimarray[stim_addr]; ext_access <= transaction[0]; ext_write <= transaction[1]; @@ -113,13 +124,11 @@ always @ (posedge clkstim) ext_data[31:0] <= transaction[71:40]; ext_srcaddr[31:0] <= transaction[103:72]; stim_addr[MAW-1:0] <= stim_addr[MAW-1:0] + 1'b1; -`else - ext_access <= |(transaction[103:0]); - ext_data[31:0] <= ext_data[31:0] + 32'b1; - ext_dstaddr[31:0] <= ext_dstaddr[31:0] + 32'd8;//(32'b1<