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Clock cleanup

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-Moving to single clock
-Unifying the timescale (1ns period)
-Stopping access when done with stimulus file
This commit is contained in:
Andreas Olofsson 2015-05-07 23:46:32 -04:00
parent 1f6c18a764
commit 38d7fe1af9
3 changed files with 71 additions and 60 deletions
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62
elink/dv/dv_elink.v
View File

@ -20,7 +20,7 @@ module dv_elink(/*AUTOARG*/
//Basic //Basic
input [CW-1:0] clk; // clocks input clk; // system clock
input reset; // Reset input reset; // Reset
output dut_passed; // Indicates passing test output dut_passed; // Indicates passing test
output dut_failed; // Indicates failing test output dut_failed; // Indicates failing test
@ -153,7 +153,7 @@ module dv_elink(/*AUTOARG*/
//Clocks //Clocks
wire clkin = clk[0]; //for pll-->cclk, rxclk, txclk wire clkin = clk; //for pll-->cclk, rxclk, txclk
@ -186,7 +186,7 @@ module dv_elink(/*AUTOARG*/
// Outputs // Outputs
.pll_bypass ({clkin,clkin,clkin,clkin}), .pll_bypass ({clkin,clkin,clkin,clkin}),
.pll_clkin (clkin), .pll_clkin (clkin),
.sys_clk (clk[0]), .sys_clk (clk),
.\(.*\) (@"(substring vl-cell-name 0 6)"_\1[]), .\(.*\) (@"(substring vl-cell-name 0 6)"_\1[]),
); );
*/ */
@ -236,7 +236,7 @@ module dv_elink(/*AUTOARG*/
// Inputs // Inputs
.reset (reset), // Templated .reset (reset), // Templated
.pll_clkin (clkin), // Templated .pll_clkin (clkin), // Templated
.sys_clk (clk[0]), // Templated .sys_clk (clk), // Templated
.rxwr_wait (elink0_rxwr_wait), // Templated .rxwr_wait (elink0_rxwr_wait), // Templated
.rxrd_wait (elink0_rxrd_wait), // Templated .rxrd_wait (elink0_rxrd_wait), // Templated
.rxrr_wait (elink0_rxrr_wait), // Templated .rxrr_wait (elink0_rxrr_wait), // Templated
@ -301,7 +301,7 @@ module dv_elink(/*AUTOARG*/
// Inputs // Inputs
.reset (reset), // Templated .reset (reset), // Templated
.pll_clkin (clkin), // Templated .pll_clkin (clkin), // Templated
.sys_clk (clk[0]), // Templated .sys_clk (clk), // Templated
.rxwr_wait (elink1_rxwr_wait), // Templated .rxwr_wait (elink1_rxwr_wait), // Templated
.rxrd_wait (elink1_rxrd_wait), // Templated .rxrd_wait (elink1_rxrd_wait), // Templated
.rxrr_wait (elink1_rxrr_wait), // Templated .rxrr_wait (elink1_rxrr_wait), // Templated
@ -316,20 +316,21 @@ module dv_elink(/*AUTOARG*/
wire elink2_access; wire elink2_access;
wire [PW-1:0] elink2_packet; wire [PW-1:0] elink2_packet;
fifo_cdc #(.DW(104), .AW(7)) model_fifo( defparam model_fifo.WIDTH=104;
// Outputs defparam model_fifo.DEPTH=16;
.wait_out (), fifo_cdc model_fifo(
.access_out (elink2_access), // Outputs
.packet_out (elink2_packet[PW-1:0]), .wait_out (),
// Inputs .access_out (elink2_access),
.clk_in (clk[0]), .packet_out (elink2_packet[PW-1:0]),
.clk_out (clk[0]), // Inputs
.reset (reset), .clk_in (clk),
.access_in (ext_access), .clk_out (clk),
.packet_in (ext_packet[PW-1:0]), .reset (reset),
.wait_in (elink2_wait_out) .access_in (ext_access),
); .packet_in (ext_packet[PW-1:0]),
.wait_in (elink2_wait_out)
);
elink_e16 elink2 ( elink_e16 elink2 (
// Outputs // Outputs
.rxi_rd_wait (), .rxi_rd_wait (),
@ -348,10 +349,10 @@ module dv_elink(/*AUTOARG*/
.c0_mesh_wait_out (elink2_wait_out), .c0_mesh_wait_out (elink2_wait_out),
// Inputs // Inputs
.reset (reset), .reset (reset),
.c0_clk_in (clk[0]), .c0_clk_in (clk),
.c1_clk_in (clk[0]), .c1_clk_in (clk),
.c2_clk_in (clk[0]), .c2_clk_in (clk),
.c3_clk_in (clk[0]), .c3_clk_in (clk),
.rxi_data (elink0_txo_data_p[7:0]), .rxi_data (elink0_txo_data_p[7:0]),
.rxi_lclk (elink0_txo_lclk_p), .rxi_lclk (elink0_txo_lclk_p),
.rxi_frame (elink0_txo_frame_p), .rxi_frame (elink0_txo_frame_p),
@ -367,9 +368,6 @@ module dv_elink(/*AUTOARG*/
); );
assign emem_access = (elink1_rxwr_access & ~(elink1_rxwr_packet[39:28]==elink1.ID)) | assign emem_access = (elink1_rxwr_access & ~(elink1_rxwr_packet[39:28]==elink1.ID)) |
(elink1_rxrd_access & ~(elink1_rxrd_packet[39:28]==elink1.ID)); (elink1_rxrd_access & ~(elink1_rxrd_packet[39:28]==elink1.ID));
@ -388,7 +386,7 @@ module dv_elink(/*AUTOARG*/
*/ */
ememory emem (.wait_in (1'b0), //only one read at a time, set to zero for no1 ememory emem (.wait_in (1'b0), //only one read at a time, set to zero for no1
.clk (clk[0]), .clk (clk),
.wait_out (emem_wait), .wait_out (emem_wait),
/*AUTOINST*/ /*AUTOINST*/
// Outputs // Outputs
@ -415,7 +413,7 @@ module dv_elink(/*AUTOARG*/
emesh_monitor #(.NAME("stimulus")) ext_monitor (.emesh_wait ((dut_rd_wait | dut_wr_wait)),//TODO:fix collisions emesh_monitor #(.NAME("stimulus")) ext_monitor (.emesh_wait ((dut_rd_wait | dut_wr_wait)),//TODO:fix collisions
.clk (clk[0]), .clk (clk),
/*AUTOINST*/ /*AUTOINST*/
// Inputs // Inputs
.reset (reset), .reset (reset),
@ -425,7 +423,7 @@ module dv_elink(/*AUTOARG*/
.emesh_packet (ext_packet[PW-1:0])); // Templated .emesh_packet (ext_packet[PW-1:0])); // Templated
emesh_monitor #(.NAME("dut")) dut_monitor (.emesh_wait (1'b0), emesh_monitor #(.NAME("dut")) dut_monitor (.emesh_wait (1'b0),
.clk (clk[0]), .clk (clk),
/*AUTOINST*/ /*AUTOINST*/
// Inputs // Inputs
.reset (reset), .reset (reset),
@ -435,7 +433,7 @@ module dv_elink(/*AUTOARG*/
.emesh_packet (dut_packet[PW-1:0])); // Templated .emesh_packet (dut_packet[PW-1:0])); // Templated
emesh_monitor #(.NAME("emem")) mem_monitor (.emesh_wait (1'b0), emesh_monitor #(.NAME("emem")) mem_monitor (.emesh_wait (1'b0),
.clk (clk[0]), .clk (clk),
.emesh_access (emem_access), .emesh_access (emem_access),
.emesh_packet (emem_packet[PW-1:0]), .emesh_packet (emem_packet[PW-1:0]),
/*AUTOINST*/ /*AUTOINST*/
@ -449,7 +447,7 @@ module dv_elink(/*AUTOARG*/
// Outputs // Outputs
.txopll_bypass ({clkin,clkin,clkin,clkin}), .txopll_bypass ({clkin,clkin,clkin,clkin}),
.clkin (clkin), .clkin (clkin),
.sys_clk (clk[0]), .sys_clk (clk),
.\(.*\) (@"(substring vl-cell-name 0 6)"_\1[]), .\(.*\) (@"(substring vl-cell-name 0 6)"_\1[]),
); );
*/ */
@ -462,7 +460,7 @@ module dv_elink(/*AUTOARG*/
.cclk_p (), .cclk_p (),
.cclk_n (), .cclk_n (),
.start (ext_access), .start (ext_access),
.clk (clk[0]), .clk (clk),
.rxi_lclk_p (txo_lclk_p), .rxi_lclk_p (txo_lclk_p),
.rxi_lclk_n (txo_lclk_n), .rxi_lclk_n (txo_lclk_n),
.rxi_frame_p (txo_frame_p), .rxi_frame_p (txo_frame_p),

64
elink/dv/dv_elink_tb.v
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@ -13,7 +13,7 @@ module dv_elink_tb();
/* verilator lint_off STMTDLY */ /* verilator lint_off STMTDLY */
/* verilator lint_off UNOPTFLAT */ /* verilator lint_off UNOPTFLAT */
//REGS //REGS
reg [1:0] clk; reg clk;
reg reset; reg reset;
reg go; reg go;
reg [1:0] datamode; reg [1:0] datamode;
@ -32,7 +32,10 @@ module dv_elink_tb();
reg [MW-1:0] stimarray[MD-1:0]; reg [MW-1:0] stimarray[MD-1:0];
reg [MW-1:0] transaction; reg [MW-1:0] transaction;
reg [MAW-1:0] stim_addr; reg [MAW-1:0] stim_addr;
reg [1:0] state;
reg [31:0] count;
reg start;
integer i; integer i;
`ifdef MANUAL `ifdef MANUAL
@ -48,19 +51,17 @@ module dv_elink_tb();
//Forever clock //Forever clock
always always
#1 clk[0] = ~clk[0]; //fast clock #1 clk = ~clk; //fast clock
always
#50 clk[1] = ~clk[1]; //slow clock wire clkstim = clk;
wire clkstim = clk[1];
//Reset //Reset
initial initial
begin begin
#0 #0
reset = 1'b1; // reset is active reset = 1'b1; // reset is active
go = 1'b0; start = 1'b0;
clk[1:0] = 2'b0; clk = 1'b0;
#1000 #1000
`ifdef AUTO `ifdef AUTO
@ -73,21 +74,31 @@ module dv_elink_tb();
`endif `endif
reset = 1'b0; // at time 100 release reset reset = 1'b0; // at time 100 release reset
#4000 #4000
go = 1'b1; start = 1'b1;
#10000
`ifdef AUTO
go = 1'b0;
`endif
#20000 #20000
$finish; $finish;
end end
//Notes:The testbench connects a 64 bit master to a 32 bit slave
`define IDLE 2'b00
`define DONE 2'b10
`define GO 2'b01
always @ (posedge clk or posedge reset)
if(reset)
state[1:0] <= `IDLE;//not started
else if(start & (state[1:0]==`IDLE))
state[1:0] <= `GO;//going
else if( ~(|count) & (state[1:0]==`GO))
state[1:0] <= `DONE;//gone
//Notes:The testbench
// connects a 64 bit master to a 32 bit slave
//To make this work, we limit the addresses to 64 bit aligned //To make this work, we limit the addresses to 64 bit aligned
//Stimulus Driver
always @ (posedge clkstim) always @ (posedge clkstim)
if(reset | ~go) if(reset)
begin begin
ext_access <= 1'b0; //empty ext_access <= 1'b0; //empty
ext_write <= 1'b0; ext_write <= 1'b0;
@ -100,10 +111,10 @@ always @ (posedge clkstim)
ext_wr_wait <= 1'b0; ext_wr_wait <= 1'b0;
stim_addr[MAW-1:0] <= 'd0; stim_addr[MAW-1:0] <= 'd0;
transaction[MW-1:0] <= 'd0; transaction[MW-1:0] <= 'd0;
count <= `TRANS;
end end
else if (go & ~(dut_wr_wait|dut_rd_wait)) else if ((state[1:0]==`GO) & ~(dut_wr_wait|dut_rd_wait))
begin begin
`ifdef MANUAL
transaction[MW-1:0] <= stimarray[stim_addr]; transaction[MW-1:0] <= stimarray[stim_addr];
ext_access <= transaction[0]; ext_access <= transaction[0];
ext_write <= transaction[1]; ext_write <= transaction[1];
@ -113,13 +124,11 @@ always @ (posedge clkstim)
ext_data[31:0] <= transaction[71:40]; ext_data[31:0] <= transaction[71:40];
ext_srcaddr[31:0] <= transaction[103:72]; ext_srcaddr[31:0] <= transaction[103:72];
stim_addr[MAW-1:0] <= stim_addr[MAW-1:0] + 1'b1; stim_addr[MAW-1:0] <= stim_addr[MAW-1:0] + 1'b1;
`else count <= count - 1'b1;
ext_access <= |(transaction[103:0]); end
ext_data[31:0] <= ext_data[31:0] + 32'b1; else
ext_dstaddr[31:0] <= ext_dstaddr[31:0] + 32'd8;//(32'b1<<datamode) ext_access <= 1'b0;
ext_datamode[1:0] <= datamode[1:0];
`endif
end
//Waveform dump //Waveform dump
`ifndef TARGET_VERILATOR `ifndef TARGET_VERILATOR
initial initial
@ -137,7 +146,6 @@ always @ (posedge clkstim)
wire dut_passed; // From dv_elink of dv_elink.v wire dut_passed; // From dv_elink of dv_elink.v
wire dut_rd_wait; // From dv_elink of dv_elink.v wire dut_rd_wait; // From dv_elink of dv_elink.v
wire dut_wr_wait; // From dv_elink of dv_elink.v wire dut_wr_wait; // From dv_elink of dv_elink.v
wire [PW-1:0] packet_out; // From e2p of emesh2packet.v
// End of automatics // End of automatics
emesh2packet e2p ( emesh2packet e2p (
@ -163,7 +171,7 @@ always @ (posedge clkstim)
.dut_access (dut_access), .dut_access (dut_access),
.dut_packet (dut_packet[PW-1:0]), .dut_packet (dut_packet[PW-1:0]),
// Inputs // Inputs
.clk (clk[CW-1:0]), .clk (clk),
.reset (reset), .reset (reset),
.ext_access (ext_access), .ext_access (ext_access),
.ext_packet (ext_packet[PW-1:0]), .ext_packet (ext_packet[PW-1:0]),

5
elink/dv/test.memh
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@ -3,3 +3,8 @@ C7C6C5C4_C3C2C1C0_80800008_0f //write to epiphany
D7D6D5D4_D3D2D1D0_80800010_0f //write to epiphany D7D6D5D4_D3D2D1D0_80800010_0f //write to epiphany
E7E6E5E4_E3E2E1E0_80800018_0f //write to epiphany E7E6E5E4_E3E2E1E0_80800018_0f //write to epiphany
F7F6F5F4_F3F2F1F0_80800020_0f //write to epiphany F7F6F5F4_F3F2F1F0_80800020_0f //write to epiphany
810D0000_B3B2B1B0_80800000_0D //read
810D0008_C3C2C1C0_80800008_0D //read
810D0010_D3D2D1D0_80800010_0D //read
810D0018_E3E2E1E0_80800018_0D //read
810D0020_F3F2F1F0_80800020_0D //read