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Clock cleanup
-Moving to single clock -Unifying the timescale (1ns period) -Stopping access when done with stimulus file
This commit is contained in:
Andreas Olofsson
parent
1f6c18a764
commit
38d7fe1af9
@ -20,7 +20,7 @@ module dv_elink(/*AUTOARG*/
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//Basic
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input [CW-1:0] clk; // clocks
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input clk; // system clock
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input reset; // Reset
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output dut_passed; // Indicates passing test
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output dut_failed; // Indicates failing test
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@ -153,7 +153,7 @@ module dv_elink(/*AUTOARG*/
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//Clocks
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wire clkin = clk[0]; //for pll-->cclk, rxclk, txclk
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wire clkin = clk; //for pll-->cclk, rxclk, txclk
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@ -186,7 +186,7 @@ module dv_elink(/*AUTOARG*/
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// Outputs
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.pll_bypass ({clkin,clkin,clkin,clkin}),
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.pll_clkin (clkin),
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.sys_clk (clk[0]),
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.sys_clk (clk),
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.\(.*\) (@"(substring vl-cell-name 0 6)"_\1[]),
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);
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*/
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@ -236,7 +236,7 @@ module dv_elink(/*AUTOARG*/
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// Inputs
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.reset (reset), // Templated
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.pll_clkin (clkin), // Templated
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.sys_clk (clk[0]), // Templated
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.sys_clk (clk), // Templated
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.rxwr_wait (elink0_rxwr_wait), // Templated
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.rxrd_wait (elink0_rxrd_wait), // Templated
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.rxrr_wait (elink0_rxrr_wait), // Templated
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@ -301,7 +301,7 @@ module dv_elink(/*AUTOARG*/
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// Inputs
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.reset (reset), // Templated
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.pll_clkin (clkin), // Templated
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.sys_clk (clk[0]), // Templated
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.sys_clk (clk), // Templated
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.rxwr_wait (elink1_rxwr_wait), // Templated
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.rxrd_wait (elink1_rxrd_wait), // Templated
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.rxrr_wait (elink1_rxrr_wait), // Templated
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@ -316,20 +316,21 @@ module dv_elink(/*AUTOARG*/
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wire elink2_access;
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wire [PW-1:0] elink2_packet;
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fifo_cdc #(.DW(104), .AW(7)) model_fifo(
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// Outputs
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.wait_out (),
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.access_out (elink2_access),
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.packet_out (elink2_packet[PW-1:0]),
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// Inputs
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.clk_in (clk[0]),
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.clk_out (clk[0]),
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.reset (reset),
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.access_in (ext_access),
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.packet_in (ext_packet[PW-1:0]),
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.wait_in (elink2_wait_out)
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);
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defparam model_fifo.WIDTH=104;
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defparam model_fifo.DEPTH=16;
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fifo_cdc model_fifo(
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// Outputs
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.wait_out (),
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.access_out (elink2_access),
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.packet_out (elink2_packet[PW-1:0]),
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// Inputs
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.clk_in (clk),
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.clk_out (clk),
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.reset (reset),
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.access_in (ext_access),
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.packet_in (ext_packet[PW-1:0]),
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.wait_in (elink2_wait_out)
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);
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elink_e16 elink2 (
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// Outputs
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.rxi_rd_wait (),
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@ -348,10 +349,10 @@ module dv_elink(/*AUTOARG*/
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.c0_mesh_wait_out (elink2_wait_out),
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// Inputs
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.reset (reset),
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.c0_clk_in (clk[0]),
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.c1_clk_in (clk[0]),
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.c2_clk_in (clk[0]),
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.c3_clk_in (clk[0]),
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.c0_clk_in (clk),
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.c1_clk_in (clk),
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.c2_clk_in (clk),
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.c3_clk_in (clk),
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.rxi_data (elink0_txo_data_p[7:0]),
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.rxi_lclk (elink0_txo_lclk_p),
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.rxi_frame (elink0_txo_frame_p),
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@ -367,9 +368,6 @@ module dv_elink(/*AUTOARG*/
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);
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assign emem_access = (elink1_rxwr_access & ~(elink1_rxwr_packet[39:28]==elink1.ID)) |
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(elink1_rxrd_access & ~(elink1_rxrd_packet[39:28]==elink1.ID));
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@ -388,7 +386,7 @@ module dv_elink(/*AUTOARG*/
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*/
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ememory emem (.wait_in (1'b0), //only one read at a time, set to zero for no1
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.clk (clk[0]),
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.clk (clk),
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.wait_out (emem_wait),
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/*AUTOINST*/
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// Outputs
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@ -415,7 +413,7 @@ module dv_elink(/*AUTOARG*/
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emesh_monitor #(.NAME("stimulus")) ext_monitor (.emesh_wait ((dut_rd_wait | dut_wr_wait)),//TODO:fix collisions
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.clk (clk[0]),
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.clk (clk),
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/*AUTOINST*/
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// Inputs
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.reset (reset),
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@ -425,7 +423,7 @@ module dv_elink(/*AUTOARG*/
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.emesh_packet (ext_packet[PW-1:0])); // Templated
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emesh_monitor #(.NAME("dut")) dut_monitor (.emesh_wait (1'b0),
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.clk (clk[0]),
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.clk (clk),
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/*AUTOINST*/
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// Inputs
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.reset (reset),
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@ -435,7 +433,7 @@ module dv_elink(/*AUTOARG*/
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.emesh_packet (dut_packet[PW-1:0])); // Templated
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emesh_monitor #(.NAME("emem")) mem_monitor (.emesh_wait (1'b0),
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.clk (clk[0]),
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.clk (clk),
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.emesh_access (emem_access),
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.emesh_packet (emem_packet[PW-1:0]),
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/*AUTOINST*/
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@ -449,7 +447,7 @@ module dv_elink(/*AUTOARG*/
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// Outputs
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.txopll_bypass ({clkin,clkin,clkin,clkin}),
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.clkin (clkin),
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.sys_clk (clk[0]),
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.sys_clk (clk),
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.\(.*\) (@"(substring vl-cell-name 0 6)"_\1[]),
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);
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*/
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@ -462,7 +460,7 @@ module dv_elink(/*AUTOARG*/
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.cclk_p (),
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.cclk_n (),
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.start (ext_access),
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.clk (clk[0]),
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.clk (clk),
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.rxi_lclk_p (txo_lclk_p),
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.rxi_lclk_n (txo_lclk_n),
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.rxi_frame_p (txo_frame_p),
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@ -13,7 +13,7 @@ module dv_elink_tb();
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/* verilator lint_off STMTDLY */
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/* verilator lint_off UNOPTFLAT */
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//REGS
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reg [1:0] clk;
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reg clk;
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reg reset;
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reg go;
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reg [1:0] datamode;
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@ -32,7 +32,10 @@ module dv_elink_tb();
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reg [MW-1:0] stimarray[MD-1:0];
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reg [MW-1:0] transaction;
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reg [MAW-1:0] stim_addr;
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reg [1:0] state;
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reg [31:0] count;
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reg start;
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integer i;
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`ifdef MANUAL
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@ -48,19 +51,17 @@ module dv_elink_tb();
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//Forever clock
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always
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#1 clk[0] = ~clk[0]; //fast clock
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always
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#50 clk[1] = ~clk[1]; //slow clock
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wire clkstim = clk[1];
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#1 clk = ~clk; //fast clock
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wire clkstim = clk;
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//Reset
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initial
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begin
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#0
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reset = 1'b1; // reset is active
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go = 1'b0;
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clk[1:0] = 2'b0;
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start = 1'b0;
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clk = 1'b0;
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#1000
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`ifdef AUTO
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@ -73,21 +74,31 @@ module dv_elink_tb();
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`endif
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reset = 1'b0; // at time 100 release reset
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#4000
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go = 1'b1;
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#10000
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`ifdef AUTO
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go = 1'b0;
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`endif
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start = 1'b1;
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#20000
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$finish;
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end
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//Notes:The testbench connects a 64 bit master to a 32 bit slave
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`define IDLE 2'b00
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`define DONE 2'b10
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`define GO 2'b01
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always @ (posedge clk or posedge reset)
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if(reset)
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state[1:0] <= `IDLE;//not started
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else if(start & (state[1:0]==`IDLE))
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state[1:0] <= `GO;//going
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else if( ~(|count) & (state[1:0]==`GO))
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state[1:0] <= `DONE;//gone
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//Notes:The testbench
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// connects a 64 bit master to a 32 bit slave
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//To make this work, we limit the addresses to 64 bit aligned
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//Stimulus Driver
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always @ (posedge clkstim)
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if(reset | ~go)
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if(reset)
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begin
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ext_access <= 1'b0; //empty
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ext_write <= 1'b0;
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@ -100,10 +111,10 @@ always @ (posedge clkstim)
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ext_wr_wait <= 1'b0;
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stim_addr[MAW-1:0] <= 'd0;
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transaction[MW-1:0] <= 'd0;
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count <= `TRANS;
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end
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else if (go & ~(dut_wr_wait|dut_rd_wait))
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else if ((state[1:0]==`GO) & ~(dut_wr_wait|dut_rd_wait))
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begin
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`ifdef MANUAL
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transaction[MW-1:0] <= stimarray[stim_addr];
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ext_access <= transaction[0];
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ext_write <= transaction[1];
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@ -113,13 +124,11 @@ always @ (posedge clkstim)
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ext_data[31:0] <= transaction[71:40];
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ext_srcaddr[31:0] <= transaction[103:72];
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stim_addr[MAW-1:0] <= stim_addr[MAW-1:0] + 1'b1;
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`else
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ext_access <= |(transaction[103:0]);
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ext_data[31:0] <= ext_data[31:0] + 32'b1;
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ext_dstaddr[31:0] <= ext_dstaddr[31:0] + 32'd8;//(32'b1<<datamode)
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ext_datamode[1:0] <= datamode[1:0];
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`endif
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end
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count <= count - 1'b1;
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end
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else
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ext_access <= 1'b0;
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//Waveform dump
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`ifndef TARGET_VERILATOR
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initial
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@ -137,7 +146,6 @@ always @ (posedge clkstim)
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wire dut_passed; // From dv_elink of dv_elink.v
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wire dut_rd_wait; // From dv_elink of dv_elink.v
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wire dut_wr_wait; // From dv_elink of dv_elink.v
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wire [PW-1:0] packet_out; // From e2p of emesh2packet.v
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// End of automatics
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emesh2packet e2p (
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@ -163,7 +171,7 @@ always @ (posedge clkstim)
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.dut_access (dut_access),
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.dut_packet (dut_packet[PW-1:0]),
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// Inputs
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.clk (clk[CW-1:0]),
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.clk (clk),
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.reset (reset),
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.ext_access (ext_access),
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.ext_packet (ext_packet[PW-1:0]),
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@ -3,3 +3,8 @@ C7C6C5C4_C3C2C1C0_80800008_0f //write to epiphany
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D7D6D5D4_D3D2D1D0_80800010_0f //write to epiphany
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E7E6E5E4_E3E2E1E0_80800018_0f //write to epiphany
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F7F6F5F4_F3F2F1F0_80800020_0f //write to epiphany
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810D0000_B3B2B1B0_80800000_0D //read
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810D0008_C3C2C1C0_80800008_0D //read
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810D0010_D3D2D1D0_80800010_0D //read
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810D0018_E3E2E1E0_80800018_0D //read
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810D0020_F3F2F1F0_80800020_0D //read
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