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Merge branch 'master' of https://github.com/parallella/oh

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Adding complete register documentation

Conflicts:
	elink/README.md
This commit is contained in:
Andreas Olofsson 2015-04-29 11:55:01 -04:00
commit 395a1b3cb7
16 changed files with 669 additions and 469 deletions
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2
edma/hdl/edma.v
View File

@ -12,7 +12,7 @@ module edma (/*AUTOARG*/
parameter RFAW = 5; // 32 registers for now
parameter AW = 32;
parameter DW = 32;
parameter TEST_PATTERN = 00000000; // test pattern for dummy writes
parameter TEST_PATTERN = 32'h12345678; // test pattern for dummy writes
/******************************/
/*HARDWARE RESET (EXTERNAL) */

416
elink/README.md
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@ -1,14 +1,15 @@
###DESCRIPTION
ELINK INTRODUCTION
=====================================
The "elink" is a low-latency/high-speed interface for communicating between
FPGAs and ASICs (such as Epiphany). The interface "should" achieve a peak
throughput of 8 Gbit/s (duplex) in modern FPGAs using 24 available LVDS signal
pairs.
###ELINK I/O Interface
FPGAs and ASICs (such as Epiphany) that uses 24 signals for full duplex
communication. The interface can achieve a peak throughput of 8 Gbit/s (duplex)
in modern FPGAs using differential LVDS signaling.
###I/O INTERFACE
SIGNAL |DIR| DESCRIPTION
------------------|---|--------------
txo_frame_{p/n} | O | TX packet framing signal.
txo_frame_{p/n} | O | TX packet framing signal
txo_lclk{p/n} | O | TX clock aligned in the center of the data eye
txo_data{p/n}[7:0]| O | TX dual data rate (DDR) that transmits packet
txi_rd_wait{p/n} | I | TX push back (input) for read transactions
@ -18,16 +19,31 @@ rxi_lclk{p/n} | I | RX clock aligned in the center of the data eye
rxi_data{p/n}[7:0]| I | RX dual data rate (DDR) that transmits packet
rxo_rd_wait{p/n} | O | RX push back (output) for read transactions
rxo_wr_wait{p/n} | O | RX push back (output) for write transactions
cclk_{p/n} | O | Epiphany differential high speed clock
chip_resetb | O | Epiphany reset (active low)
colid[3:0] | O | Epiphany column chip coordinate
rowid[3:0] | O | Epiphany row chip coordinate
The Epiphany specific output signals can be left unconnected in systems that
don't include Epiphany chips.
###SYSTEM SIDE INTERFACE
SIGNAL |DIR| DESCRIPTION
------------------|---|--------------
elinkid[11:0] | I | Address ID of elink
hard_reset | I | Reset input
clkin | I | Clock input for CCLK/LCLK PLL
rx_lclk_div4 | O | rxi_lclk clock divided by 4
tx_lclk_div4 | O | txo_lclk clock divided by 4
clkbypass[2:0] | I | Clocks inputs for bypassing PLL
cclk_{p/n} | O | Differential clock output for Epiphany
chip_resetb | O | Reset for Epiphany (active low)
colid[3:0] | O | Column chip coordinate pins for Epiphany
rowid[3:0] | O | Row chip coordinate pins for Epiphany
embox_not_empty | O | Mailbox not empty (connect to interrupt line)
embox_full | O | Mailbox is full indicator
timeout | O | Read request timeout indicator
mi_en | I | Congiruation access enable
mi_we | I | Configuration write
mi_addr[19:0] | I | Configuration register address
mi_din[31:0] | I | Configuration data input
mi_dout[31:0] | O | Configuration readback data
txwr_access | I | TX write
txwr_packet[103:0]| I | TX write packet
txwr_wait | O | TX write wait (pushback)
@ -47,53 +63,54 @@ rxrr_access | O | RX read-response
rxrr_packet[103:0]| O | RX read-response packet
rxrr_wait | I | RX read-response wait (pushback)
###ELINK I/O PROTOCOL
###I/O PROTOCOL
The default protocol for the elink is the Epiphany chip to chip interface.
The Epiphany protocol uses a source synchronous clocks, a packet frame signal,
an 8-bit wide dual data rate data bus, and separate read and write packet wait
signals to implement a gluless point to point link.
__ ___ ___ ___ ___ ___ ___ ___ ___
```
__ ___ ___ ___ ___ ___ ___ ___
LCLK \___/ \___/ \___/ \___/ \___/ \___/ \___/ \___/
_______________________________________________________________
FRAME _/ \______
DATA XXXX|B00|B01|B02|B03|B04|B05|B06|B07|B08|B09|B10|B11|B12|B13|B14.
```
BYTE | DESCRIPTION
---------|--------------
B00 | 00000000
B01 | ctrlmode[3:0],dstaddr[31:28]
B01 | {ctrlmode[3:0],dstaddr[31:28]}
B02 | dstaddr[27:20]
B03 | dstaddr[19:12]
B04 | dstaddr[11:4]
B05 | dstaddr[3:0],datamode[1:0],write,access
B05 | {dstaddr[3:0],datamode[1:0],write,access}
B06 | data[31:24] (or srcaddr[31:24] if read transaction)
B07 | data[23:16] (or srcaddr[23:16] if read transaction)
B08 | data[15:8] (or srcaddr[15:8] if read transaction)
B09 | data[7:0] (or srcaddr[7:0] if read transaction)
*B10 | data[63:56]
+B10 | data[63:56]
B11 | data[55:48]
B12 | data[47:40]
B13 | data[39:32]
**B14 | data[31:24] (in 64 bit write burst mode)
++B14 | data[31:24] (in 64 bit write burst mode)
B15 | data[23:16] (in 64 bit write burst mode)
... | ...
* byte9 is the last byte of 32 bit write or read transaction
** if 64 bit write transaction, data of byte14 is the first data byte of
bursting transaction
+B09 is the last byte of 32 bit write or read transaction
++B14 is the first data byte of bursting transaction
The data captured on the rising edge of the LCLK is considered to be B0 if
the FRAME control captured at the same cycle is high but was low at the rising
edge of the previous LCLK cycle (ie rising edge). If the FRAME control signal
stays high after B13, then the the eLink goes into “bursting mode”, meaning
that the last byte of the previous transaction (B13) will be followed by B06
of a new transaction.
of a new transaction.
The data is transmitted MSB first but in 32bits resolution. If we want to
transmit 64 bits it will be [31:0] (msb first) and then [63:32] (msb first)
transmit 64 bits it will be bits 31:0 (msb first) and then 63:32 (msb first)
The wait signals are used to stall transmission when a receiver is unable to
accept more transactions. The receiver will raise its WAIT output signal during
@ -104,18 +121,18 @@ sampled with the two-cycle synchronizer. Once synchronized to the transmitter's
LCLK clock domain, the WAIT control signals will prevent new transaction from
being transmitted. If the transaction is in the middle of the transmission when
the synchronized WAIT control goes high, the transmission process is to
completed without interruption.
completed without interruption.
###BUS PROTOCOL
###SYSTEM SIDE PROTOCOL
Communication between the elink and the system side (i.e. the AXI side) is done
using the rx and tx parallel interfaces. Read, write, and read response
transactions have independent channels into the elink. Data from a receiver
read request is expected to return on the read response transmit chanel.
The "access" signals indicate a valid transaction. The wait signals indicate
that the receiving block is not ready to receive the packet.
The elink packets haave the following bit ordering.
that the receiving block is not ready to receive the packet. An elink packet
has the following bit ordering.
PACKET FIELD | BITS | DESCRIPTION
--------------|---------|----------
@ -129,13 +146,14 @@ The elink packets haave the following bit ordering.
###INTERNAL STRUCTURE
(link)
(link to picture)
###ELINK REGISTER MAP
###REGISTER MAP
The elink has a 12 bit ID that maps to address bits [31:20].
As an example, if the ID is set to 0x810, then writing to the E_RESET
register would be done to address 0x810E0040
The full 32 bit physical address of an elink register is the address seen below
added to the 12 bit elink ID that maps to address bits 31:20. As an example,
if the elink ID is 0x810, then writing to the E_RESET register would be done to
address 0x810D0000.
REGISTER | ADDRESS | DESCRIPTION
---------------|---------|------------------
@ -146,15 +164,11 @@ E_VERSION | 0xD000C | Version number
ETX_CFG | 0xD0040 | TX configuration
ETX_STATUS | 0xD0044 | TX status
ETX_GPIO | 0xD0048 | TX data in GPIO mode
ETX_TEST | 0xD0050 | TX test mode configuration
ETX_DSTADDR | 0xD0054 | TX destination address for test mode
ETX_DATA | 0xD0058 | TX data for test mode
ETX_SRCADDR | 0xD005c | TX return address for read in test mode
ETX_MMU | 0xD8000 | TX MMU table
ERX_CFG | 0xE0000 | RX configuration
ERX_STATUS | 0xE0004 | RX status register
ERX_GPIO | 0xE0008 | RX data in GPIO mode
ERX_RRR | 0xE000c | RX read response address
ERX_RR | 0xE000c | RX read response address
ERX_OFFSET | 0xE0000 | RX memory offset in remap mode
ERX_MAILBOXLO | 0xE0040 | RX mailbox (lower 32 bit)
ERX_MAILBOXHI | 0xE0044 | RX mailbox (upper 32 bits)
@ -166,75 +180,259 @@ ERX_DMADSTADDR | 0xE0090 | RX DMA destination address
ERX_DMASTATUS | 0xE0094 | RX DMA status
ERX_MMU | 0xE8000 | RX MMU table
###ELINK REGISTER DESCRIPTIONS
REGISTER | DESCRIPTION
---------- | --------------------------------------------------
ELRESET | (elink reset register)
[0] | 0: elink is active
| 1: elink in reset
---------- |---------------------------------------------------
ELTX | (elink transmit configuration register)
[0] | 0: TX disable
| 1: TX enable
[1] | 0: static address translation
| 1: enables MMU based address translation
[3:2] | 00: default elink packet transfer mode
| 01: forces values from ESYSDATAOUT on output pins
| 1x: reserved
[7:4] | Transmit control mode for eMesh
[8] | AXI slave read timeout enable
-----------|----------------------------------------------------
ELRX | (elink receive configuration register)
[0] | 0: elink RX disable
| 1: elink RX enable
[1] | 0: static address translation
| 1: enables MMU based address translation
[3:2] | 00: default elink packet receive mode
| 01: stores input pin data in ESYSDATAIN register
| 1x: reserved
-----------|---------------------------------------------------
ELCLK | (elink PLL configuration register)
[0] | 0:cclk clock disabled
| 1:cclk clock enabled
[1] | 0:tx_lclk clock disabled
| 1:tx_lclk clock enabled
[2] | 0: cclk driven from internal PLL
| 1: cclk driven from clkbypass[2:0] input
[3] | 0: lclk driven from internal PLL
| 1: lclk driven from clkbypass[2:0] input
[7:4] | 0000: cclk=pllclk/1
| 0001: cclk=pllclk/2
| 0010: cclk=pllclk/4
| 0011: cclk=pllclk/8
| 0100: cclk=pllclk/16
| 0101: cclk=pllclk/32
| 0110: cclk=pllclk/64
| 0111: cclk=pllclk/128
| 1xxx: RESERVED
[11:8] | 0000: lclk=pllclk/1
| 0001: lclk=pllclk/2
| 0010: lclk=pllclk/4
| 0011: lclk=pllclk/8
| 0100: lclk=pllclk/16
| 0101: lclk=pllclk/32
| 0110: lclk=pllclk/64
| 0111: lclk=pllclk/128
| 1xxx: RESERVED
[15:12] | PLL frequency
-----------|-------------------------------------------------
ELCOREID | (coordinate ID for Epiphany)
[5:0] | Column ID for connected Epiphany chip
[11:6] | Row ID for connected Epiphany chip
-----------|-------------------------------------------------
ELVERSION | (platform and version ID)
[7:0] | Platform model number
[7:0] | Revision number
-----------|-------------------------------------------------
EDATAIN | (data on elink input pins)
[7:0] | rx_data[7:0]
[8] | tx_frame
[9] | tx_wait_rd
[10] | tx_wait_wr
-----------|-------------------------------------------------
REGISTER DESCRIPTIONS
===========================================
###E_RESET
Reset control register for the elink and Epiphany chip
FIELD | DESCRIPTION
-------- | --------------------------------------------------
[0] | 0: elink is active
| 1: elink in reset
[1] | 0: epiphany chip is active
| 1: epiphany chip in reset
[2] | 1: Starts an internal reset and clock sequnce block
(self resetting bit)
###E_CLK (LABS)
Transmit and Epiphany clock settings.
(NOTE: not currently implemented)
FIELD | DESCRIPTION
---------| --------------------------------------------------
[0] | 0: cclk clock disabled
| 1: cclk clock enabled
[1] | 0: tx_lclk clock disabled
| 1: tx_lclk clock enabled
[2] | 0: cclk driven from internal PLL
| 1: cclk driven from clkbypass[0] input
[3] | 0: lclk driven from internal PLL
| 1: lclk driven from clkbypass[1] input
[7:4] | 0000: cclk=pllclk/1
| 0001: cclk=pllclk/2
| 0010: cclk=pllclk/4
| 0011: cclk=pllclk/8
| 0100: cclk=pllclk/16
| 0101: cclk=pllclk/32
| 0110: cclk=pllclk/64
| 0111: cclk=pllclk/128
| 1xxx: RESERVED
[11:8] | 0000: lclk=pllclk/1
| 0001: lclk=pllclk/2
| 0010: lclk=pllclk/4
| 0011: lclk=pllclk/8
| 0100: lclk=pllclk/16
| 0101: lclk=pllclk/32
| 0110: lclk=pllclk/64
| 0111: lclk=pllclk/128
| 1xxx: RESERVED
[15:12] | PLL frequency (TBD)
###E_CHIPID
Column and row chip id pins to the Epiphany chip.
FIELD | DESCRIPTION
-------- |---------------------------------------------------
[5:2] | Column chip ID for Epiphany chip
[11:8] | Row chip ID for Epiphany chip
###E_VERSION
Platform and revision number.
FIELD | DESCRIPTION
-------- |---------------------------------------------------
[7:0] | Platform version
[15:8] | Revision number
###ETX_CFG
TX configuration settings
FIELD | DESCRIPTION
-------- |---------------------------------------------------
[0] | 0: TX disable
| 1: TX enable
[1] | 0: MMU disabled
| 1: MMU enabled
[3:2] | 00: Address remapping disabled
| 01: TX addr_out = {addr[29:16],|addr[17:16]?11:00,addr[15:0]}
| 1x: Reserved
[7:4] | Epiphany routing control mode bits
| 0000: Normal routing
| 0001: Force NORTH routing on address match (instead of "into" core)
| 0101: Force EAST routing on address match (instead of "into" core)
| 1001: Force SOUTH routing on address match (instead of "into" core)
| 1101: Force WEST routing on address match (instead of "into" core)
| 0011: Multicast routing (LABS)
[8] | Control mode select for TXRD/TXWR channels
| 0: ctrlmode field taken from incoming transmit packet
| 1: ctrlmode field taken E_TXCFG
[11:9] | 00: Normal transmit mode
| 01: GPIO direct drive mode
| 10: Enables test pattern generator for IO (LABS)
###ETX_STATUS
TX status register
FIELD | DESCRIPTION
-------- |---------------------------------------------------
[15:0] | TBD
###ETX_GPIO
Data to drive on txo_data and txo_frame pins in gpio mode
FIELD | DESCRIPTION
-------- |---------------------------------------------------
[7:0] | Data for txo_data pins
[8] | Data for txo_frame pin
###ETX_MMU
A table of N entries for translating incoming 12 bit address
to a new value. Entries are aligned on 8 byte boundaroies
FIELD | DESCRIPTION
-------- |---------------------------------------------------
[11:0] | Output address bits 31:20
[43:12] | Output address bits 63:32 (TBD)
###ERX_CFG
RX configuration register
FIELD | DESCRIPTION
-------- |---------------------------------------------------
[0] | 0: RX disabled
| 1: RX enabled
[1] | 0: MMU disabled
| 1: MMU enabled
[3:2] | RX address remapping mode
| 00: pass-through mode, remapping disabled
| 01: "static" remap_addr =
| (remap_sel[11:0] & remap_pattern[11:0]) |
| (~remap_sel[11:0] & addr_in[31:20]);
| 10: "dynamic" remap_addr =
| addr_in[31:0]
| - (colid << 20)
| + ERX_OFFSET[31:0]
| - (addr_in[31:26]<<clog2(colid));
[15:4] | Remap selection for "01" remap method
| "1" means remap bit is selected
[27:16] | Remap values (for addr[31:20)
[29:28] | Read request timeout counter configuration
| 00: Timeout counter turned off
| 01: Timeout value set to 000000FF
| 10: Timeout value set to 0000FFFF
| 11: Timeout value set to FFFFFFFF
###ERX_STATUS
RX status register
FIELD | DESCRIPTION
-------- |---------------------------------------------------
[15:0] | TBD
###ERX_GPIO
RX status register
Data sampled on rxi_data and rxi_frame pins in gpio mode
FIELD | DESCRIPTION
-------- |---------------------------------------------------
[7:0] | Data from rxi_data pins
[8] | Data from rxi_frame pin
###ERX_RR
Last read response data that was received on rxrr_packet[103:0]
FIELD | DESCRIPTION
-------- |---------------------------------------------------
[31:0] | Read response data (lower 32 bits)
###ERX_OFFSET
Address offset used in the dynamic address remapping mode
FIELD | DESCRIPTION
-------- |---------------------------------------------------
[31:0] | Memory offset
###ERX_MAILBOXLO
Lower 32 bit word of current entry of RX 64-bit wide mailbox FIFO. This
register should be read before the ERX_MAILBOXHI.
FIELD | DESCRIPTION
-------- |---------------------------------------------------
[31:0] | Lower data of RX FIFO
###ERX_MAILBOXHI
Upper 32 bit word of current entry of RX 64-bit wide mailbox FIFO. Reading this
register causes the RX FIFO read pointer to increment by one
FIELD | DESCRIPTION
-------- |---------------------------------------------------
[31:0] | Upper data of RX FIFO
###DMACFG
Configuration register for DMA
FIELD | DESCRIPTION
-------- |---------------------------------------------------
[0] | 0: DMA disabled
| 1: DMA enabled
[1] | 0: Slave mode
| 1: Master mode
[6:5] | 00: byte transfers
| 01: half-word transfers
| 10: word transfers
| 11: double word transfers
[10] | 0: Message mode disabled
| 1: Enables special message mode
[11] | 0: Source address shift disabled
| 1: Left shifts stride by 16 bits
[12] | 0: Destination address shift disabled
| 1: Left shifts stride by 16 bits
###DMACOUNT
The number of DMA left to complete The DMA transfer is complete when the
DMACOUNT register reaches zero.
FIELD | DESCRIPTION
-------- |---------------------------------------------------
[31:0] | The number of transfers remaining
###DMADSTADDR
The current 32-bit address being transferred
FIELD | DESCRIPTION
-------- |---------------------------------------------------
[31:0] | Current transaction destination address to write to
###DMASRCADDR
The current 32-bit address being read from in master mode
FIELD | DESCRIPTION
-------- |---------------------------------------------------
[31:0] | Current transaction destination address to write to
###DMASTRIDE
Two signed 16-bit values specifying the stride, in bytes, used to update the
DMASRCADDR and DMADSTADDR after each completed transfer.
FIELD | DESCRIPTION
-------- |---------------------------------------------------
[15:0] | Value to add to DMASRCADDR after each transaction
[31:16] | Value to add to DMADSTADDR after each transaction
###DMASTRIDE
Status of DMA
FIELD | DESCRIPTION
-------- |---------------------------------------------------
[31:0] | TBD
###ERX_MMU
A table of N entries for translating incoming 12 bit address to a new value.
Entries are aligned on 8 byte boundaries
FIELD | DESCRIPTION
-------- |---------------------------------------------------
[11:0] | Output address bits 31:20
[43:12] | Output address bits 63:32 (TBD)

144
elink/dv/test.memh
View File

@ -1,118 +1,32 @@
00000000_00000001_810e000c_0b //assert reset
00000000_00000001_810e0010_0b //clocks on full speed
00000000_00000111_810e0010_0b //clk/2
00000000_00000221_810e0010_0b //clk/4
00000000_00000331_810e0010_0b //clk/8
00000000_00000441_810e0010_0b //clk/16
00000000_00000551_810e0010_0b //clk/32
00000000_00000661_810e0010_0b //clk/64
00000000_00000000_810e0010_0b //stop cclk
00000000_00000000_810e000c_0b //deassert reset
00000000_00000213_810e0010_0b //start cclk and lclk
00000000_00000001_810e0000_0b //enable tx
00000000_00000001_820e0000_0b //ELINK1: enable tx
00000000_00000213_820e0010_0b //ELINK1: start cclk and lclk
00000000_00000810_810ec080_0b //write to TX MMU(810)
00000000_00000820_810ec100_0b //write to TX MMU(820)
00000000_00000408_810ec040_0b //write to TX MMU(808)
00000000_00000810_820dc080_0b //ELINK1: write to RX MMU(810)
00000000_00000820_820dc100_0b //ELINK1: write to RX MMU(820)
00000000_00000608_820da040_0b //ELINK1: write to RX MMU(408)
00000000_AAAA0000_80800000_0b //write to epiphany
00000000_AAAA0001_80800004_0b //write to epiphany
00000000_AAAA0002_80800008_0b //write to epiphany
00000000_AAAA0003_8080000c_0b //write to epiphany
00000000_AAAA0004_80800010_0b //write to epiphany
810D000c_00000000_80800010_09 //read from epiphany
810D000c_00000000_8080000c_09 //read from epiphany
810D000c_00000000_80800008_09 //read from epiphany
810D000c_00000000_80800004_09 //read from epiphany
810D000c_00000000_80800000_09 //read from epiphany
00000000_00000000_00000000_00 //***START OF TX REGS***
00000000_00000001_810e000c_0b //ELRESET
00000000_00000000_810e000c_0b //ELRESET
00000000_00000331_810e0010_0b //ELCLK
00000000_00000001_810e0000_0b //ELTXCFG
00000000_00000001_810e0004_0b //ELTXSTATUS
00000000_FFFFFFFF_810e0008_0b //ELTXGPIO
00000000_AAAAAAAA_810e0014_0b //ELCHIPID
00000000_BBBBBBBB_810e0018_0b //ELVERSION
00000000_808CCCCC_810e0020_0b //ELTXDSTADDR
00000000_DDDDDDDD_810e0024_0b //ELTXDATA
00000000_810d0014_810e0028_0b //ELTXSRCADDR
00000000_0000000b_810e001c_0b //ELTXTEST
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_0508fff5_820d0000_0b //ELINK1:enable rx remap
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000005_810e0000_0b //enable tx remap
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_BBBB0000_20200000_0b //write to epiphany
00000000_BBBB0001_20200004_0b //write to epiphany
00000000_BBBB0002_20200008_0b //write to epiphany
00000000_BBBB0003_2020000c_0b //write to epiphany
00000000_BBBB0004_20200010_0b //write to epiphany
810D000C_00000000_20200010_09 //read from epiphany
810D000C_00000000_2020000c_09 //read from epiphany
810D000C_00000000_20200008_09 //read from epiphany
810D000C_00000000_20200004_09 //read from epiphany
810D000C_00000000_20200000_09 //read from epiphany
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000003_810e0000_0b //enable TX MMU
00000000_00000003_820d0000_0b //ELINK1: enable RX MMU***
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_CCCC0000_80800000_0b //write to epiphany
00000000_CCCC0001_80800004_0b //write to epiphany
00000000_CCCC0002_80800008_0b //write to epiphany
00000000_CCCC0003_8080000c_0b //write to epiphany
00000000_CCCC0004_80800010_0b //write to epiphany
810D000C_00000000_80800010_09 //read from epiphany
810D000C_00000000_8080000c_09 //read from epiphany
810D000C_00000000_80800008_09 //read from epiphany
810D000C_00000000_80800004_09 //read from epiphany
810D000C_00000000_80800000_09 //read from epiphany
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000000_00000000_00 //WAIT
00000000_00000001_810e0000_0b //enable tx (normal mode)
00000000_00000001_820d0000_0b //ELINK1: enable rx (normal mode)
00000000_00000810_810ec080_0b //ETXMMU
00000000_00000000_00000000_00 //***END OF TX REGS***
00000000_00000001_810d0000_0b //ELRXCFG
00000000_00000001_810d0004_0b //ELRXSTATUS
00000000_AAAAAAAA_810d0008_0b //ELRXGPIO
00000000_BBBBBBBB_810d0014_0b //ELRXRR
00000000_CCCCCCCC_810d0018_0b //ELRXBASE
00000000_DDDDDDDD_810d0020_0b //ELMAILBOXLO
00000000_EEEEEEEE_810d0020_0b //ELMAILBOXHI
00000000_00000213_810d0024_0b //EDMACFG
00000000_00000000_810d0028_0b //EDMACOUNT
00000000_00000000_810d0028_0b //EDMASTRIDE
00000000_00000000_810d0028_0b //EDMASTRIDE
00000000_00000000_810d0028_0b //EDMASRCADDR
00000000_00000000_810d0028_0b //EDMADSTADDR
00000000_00000810_810dc080_0b //ERXMMU

12
elink/hdl/ecfg_base.v
View File

@ -42,11 +42,11 @@ module ecfg_base (/*AUTOARG*/
/*ELINK CONTROL SIGNALS */
/*****************************/
//clocks
output [15:0] ecfg_clk_settings; // clock settings
output [15:0] ecfg_clk_settings; // clock settings (for pll)
//coreid
output [3:0] colid;
output [3:0] rowid;
//chipid
output [3:0] colid; //sampled by reset rising edge
output [3:0] rowid;
/*------------------------CODE BODY---------------------------------------*/
@ -70,8 +70,8 @@ module ecfg_base (/*AUTOARG*/
/*****************************/
//read/write decode
assign ecfg_write = mi_en & mi_we & (mi_addr[19:16]==GROUP);
assign ecfg_read = mi_en & ~mi_we & (mi_addr[19:16]==GROUP);
assign ecfg_write = mi_en & mi_we;
assign ecfg_read = mi_en & ~mi_we;
//Config write enables
assign ecfg_reset_write = ecfg_write & (mi_addr[RFAW+1:2]==`ELRESET);

85
elink/hdl/ecfg_if.v
View File

@ -2,16 +2,17 @@
########################################################################
ELINK CONFIGURATION INTERFACE
########################################################################
*/
module ecfg_if (/*AUTOARG*/
// Outputs
txwr_wait, txrd_wait, mi_en, mi_we, mi_addr, mi_din,
txwr_wait, txrd_wait, mi_txcfg_en, mi_basecfg_en, mi_txmmu_en,
mi_rxcfg_en, mi_mailbox_en, mi_dma_en, mi_rxmmu_en, mi_we, mi_addr,
mi_din,
// Inputs
sys_clk, reset, txwr_access, txwr_packet, txrd_access, txrd_packet,
rxwr_access, rxwr_packet, mi_el_dout, mi_rx_dout, mi_tx_dout,
mi_mailbox_dout
sys_clk, tx_lclk_div4, rx_lclk_div4, reset, txwr_access,
txwr_packet, txrd_access, txrd_packet, rxwr_access, rxwr_packet,
mi_el_dout, mi_rx_dout, mi_tx_dout, mi_mailbox_dout
);
parameter ID = 12'h800;
@ -21,9 +22,11 @@ module ecfg_if (/*AUTOARG*/
/********************************/
/*One clock domain */
/*Clocks/reset */
/********************************/
input sys_clk;
input tx_lclk_div4;
input rx_lclk_div4;
input reset;
/********************************/
@ -46,13 +49,33 @@ module ecfg_if (/*AUTOARG*/
input [PW-1:0] rxwr_packet;
/********************************/
/*Register Interface */
/*TX Register Interface */
/********************************/
output mi_en;
output mi_we;
output mi_tx_cfg_en;
output mi_tx_mmu_en;
output mi_tx_we;
output [19:0] mi_tx_addr;
output [63:0] mi_tx_din;
/********************************/
/*RX Register Interface */
/********************************/
output mi_rx_cfg_en;
output mi_rx_dma_en;
output mi_rx_mmu_en;
output mi_rx_we;
output [19:0] mi_rx_addr;
output [63:0] mi_rx_din;
/********************************/
/*SYS_CLK Register Interface */
/********************************/
output mi_basecfg_en;
output mi_mailbox_en;
output mi_we;
output [19:0] mi_addr;
output [63:0] mi_din;
/******************************/
/*Readback Data */
/******************************/
@ -70,8 +93,6 @@ module ecfg_if (/*AUTOARG*/
wire [AW-1:0] txrd_dstaddr;
wire [AW-1:0] txrd_srcaddr;
wire mi_wr;
wire mi_rd;
reg [63:0] rx_mi_data_reg;
@ -118,9 +139,14 @@ module ecfg_if (/*AUTOARG*/
assign mi_rd = tx_rd; //no access from receiver
//DODO: 64 bit writes?
assign mi_we = mi_wr;
assign mi_en = mi_wr | mi_rd;
assign mi_we = mi_wr;
assign mi_en = mi_wr | mi_rd;
//Enable signals (keep decoding in one place!!!)
//Read/write address
assign mi_addr[19:0] = rx_wr ? rxwr_dstaddr[19:0] :
tx_rd ? txrd_dstaddr[19:0] :
@ -129,15 +155,36 @@ module ecfg_if (/*AUTOARG*/
//Data (prepare for it)
assign mi_din[63:0] = rx_wr ? rxwr_data[63:0] :
txwr_data[63:0];
//Interface clock (gate?)
assign mi_clk = sys_clk;
//Wait signals
assign txwr_wait = tx_wr & rx_wr;
assign txrd_wait = tx_rd & (tx_wr | rx_wr);
/********************************/
/*BASIC Register Interface */
/********************************/
assign mi_basecfg_en = mi_en & (mi_addr[19:15]=={`EGROUP_TX,1'b0}) & (mi_addr[7:6]==`EBLOCK1);
assign mi_mailbox_en = mi_en & (mi_addr[19:15]=={`EGROUP_RX,1'b0}) & (mi_addr[7:6]==`EBLOCK1);
/********************************/
/*TX Register Interface */
/********************************/
assign mi_tx_cfg_en = mi_en & (mi_addr[19:15]=={`EGROUP_TX,1'b0}) & (mi_addr[7:6]==`EBLOCK0);
assign mi_tx_mmu_en = mi_en & (mi_addr[19:15]=={`EGROUP_RX,1'b1});
assign mi_tx_wen = mi_din[63:0];
assign mi_tx_din[63:0] = mi_din[63:0];
assign mi_tx_addr[19:0] = mi_addr[19:0];
/********************************/
/*RX Register Interface */
/********************************/
assign mi_rx_cfg_en = mi_en & (mi_addr[19:15]=={`EGROUP_RX,1'b0}) & (mi_addr[7:6]==`EBLOCK0);
assign mi_rx_dma_en = mi_en & (mi_addr[19:15]=={`EGROUP_RX,1'b0}) & (mi_addr[7:6]==`EBLOCK2);
assign mi_rx_mmu_en = mi_en & (mi_addr[19:15]=={`EGROUP_RX,1'b1});
assign mi_rx_din[63:0] = mi_din[63:0];
assign mi_rx_addr[19:0] = mi_addr[19:0];
//TODO: Do readback later....
//
endmodule // ecfg_if

36
elink/hdl/ecfg_rx.v
View File

@ -10,7 +10,7 @@ module ecfg_rx (/*AUTOARG*/
mi_dout, rx_enable, mmu_enable, remap_mode, remap_base,
remap_pattern, remap_sel, timer_cfg,
// Inputs
reset, sys_clk, mi_en, mi_we, mi_addr, mi_din, gpio_datain,
reset, clk, mi_en, mi_we, mi_addr, mi_din, gpio_datain,
debug_vector
);
@ -24,7 +24,7 @@ module ecfg_rx (/*AUTOARG*/
/*HARDWARE RESET (EXTERNAL) */
/******************************/
input reset; // ecfg registers reset only by "hard reset"
input sys_clk;
input clk;
/*****************************/
/*SIMPLE MEMORY INTERFACE */
/*****************************/
@ -39,14 +39,14 @@ module ecfg_rx (/*AUTOARG*/
/*****************************/
//rx
output rx_enable; // enable signal for rx
output mmu_enable; // enables MMU on rx path
input [8:0] gpio_datain; // frame and data inputs
input [15:0] debug_vector; // erx debug signals
output [1:0] remap_mode; //remap mode
output [31:0] remap_base; //base for dynamic remap
output [11:0] remap_pattern;//patter for static remap
output [11:0] remap_sel; //selects for static remap
output [1:0] timer_cfg; //timeout config (00=off)
output mmu_enable; // enables MMU on rx path (static)
input [8:0] gpio_datain; // frame and data inputs (static)
input [15:0] debug_vector; // erx debug signals (static)
output [1:0] remap_mode; // remap mode (static)
output [31:0] remap_base; // base for dynamic remap (static)
output [11:0] remap_pattern;// patter for static remap (static)
output [11:0] remap_sel; // selects for static remap (static)
output [1:0] timer_cfg; // timeout config (00=off) (static)
/*------------------------CODE BODY---------------------------------------*/
@ -70,8 +70,8 @@ module ecfg_rx (/*AUTOARG*/
/*****************************/
//read/write decode
assign ecfg_write = mi_en & mi_we & (mi_addr[19:15]=={GROUP,1'b0});
assign ecfg_read = mi_en & ~mi_we & (mi_addr[19:15]=={GROUP,1'b0});
assign ecfg_write = mi_en & mi_we;
assign ecfg_read = mi_en & ~mi_we;
//Config write enables
assign ecfg_rx_write = ecfg_write & (mi_addr[RFAW+1:2]==`ELRXCFG);
@ -80,7 +80,7 @@ module ecfg_rx (/*AUTOARG*/
//###########################
//# RXCFG
//###########################
always @ (posedge sys_clk)
always @ (posedge clk)
if(reset)
ecfg_rx_reg[31:0] <= 'b0;
else if (ecfg_rx_write)
@ -96,7 +96,7 @@ module ecfg_rx (/*AUTOARG*/
//###########################
//# DATAIN (synchronized)
//###########################
always @ (posedge sys_clk)
always @ (posedge clk)
begin
ecfg_datain_sync[8:0] <= gpio_datain[8:0];
ecfg_datain_reg[8:0] <= ecfg_datain_sync[8:0];
@ -106,7 +106,7 @@ module ecfg_rx (/*AUTOARG*/
//# DEBUG
//###########################
always @ (posedge sys_clk)
always @ (posedge clk)
if(reset)
ecfg_rx_debug_reg[2:0] <= 'd0;
else
@ -115,7 +115,7 @@ module ecfg_rx (/*AUTOARG*/
//###########################1
//# DYNAMIC REMAP BASE
//###########################
always @ (posedge sys_clk)
always @ (posedge clk)
if(reset)
ecfg_base_reg[31:0] <='d0;
else if (ecfg_base_write)
@ -128,7 +128,7 @@ module ecfg_rx (/*AUTOARG*/
//###############################
//Pipelineing readback
always @ (posedge sys_clk)
always @ (posedge clk)
if(ecfg_read)
case(mi_addr[RFAW+1:2])
`ELRXCFG: mi_dout[31:0] <= {ecfg_rx_reg[31:0]};
@ -137,7 +137,7 @@ module ecfg_rx (/*AUTOARG*/
default: mi_dout[31:0] <= 32'd0;
endcase
endmodule // ecfg
endmodule // ecfg_rx
/*
Copyright (C) 2013 Adapteva, Inc.

74
elink/hdl/ecfg_tx.v
View File

@ -7,10 +7,10 @@
module ecfg_tx (/*AUTOARG*/
// Outputs
mi_dout, ecfg_tx_enable, ecfg_tx_mmu_enable, ecfg_tx_gpio_enable,
ecfg_tx_tp_enable, ecfg_tx_ctrlmode, ecfg_tx_ctrlmode_bp,
ecfg_tx_remap_enable, ecfg_dataout, ecfg_access, ecfg_packet,
ecfg_tx_tp_enable, ecfg_tx_remap_enable, ecfg_dataout, ecfg_access,
ecfg_packet, ecfg_tx_ctrlmode, ecfg_tx_ctrlmode_bp,
// Inputs
reset, sys_clk, mi_en, mi_we, mi_addr, mi_din, ecfg_tx_debug
reset, clk, mi_en, mi_we, mi_addr, mi_din, ecfg_tx_debug
);
/******************************/
@ -24,7 +24,7 @@ module ecfg_tx (/*AUTOARG*/
/*HARDWARE RESET (EXTERNAL) */
/******************************/
input reset; // ecfg registers reset only by "hard reset"
input sys_clk;
input clk; // main tx logic clock
/*****************************/
/*SIMPLE MEMORY INTERFACE */
@ -38,18 +38,24 @@ module ecfg_tx (/*AUTOARG*/
/*****************************/
/*ELINK CONTROL SIGNALS */
/*****************************/
//tx
//tx (static configs)
output ecfg_tx_enable; // enable signal for TX
output ecfg_tx_mmu_enable; // enables MMU on transmit path
output ecfg_tx_gpio_enable; // forces TX output pins to constants
output ecfg_tx_tp_enable; // enables 1/0 pattern on transmit
output ecfg_tx_tp_enable; // enables 1/0 pattern on transmit
output ecfg_tx_remap_enable; // enable address remapping
input [15:0] ecfg_tx_debug; // etx debug signals
//sampled by tx_lclk (test)
output [8:0] ecfg_dataout; // data for elink outputs (static)
//sampled by tx_lclk (test)
output ecfg_access; // direct test access
output [PW-1:0] ecfg_packet; // packet for direct test access
//dynamic (control timing by use mode)
output [3:0] ecfg_tx_ctrlmode; // value for emesh ctrlmode tag
output ecfg_tx_ctrlmode_bp; // bypass value for emesh ctrlmode tag
output ecfg_tx_remap_enable; // enable address remapping
output [8:0] ecfg_dataout; // data for elink outputs
input [15:0] ecfg_tx_debug; // etx debug signals
output ecfg_access; // direct test access
output [PW-1:0] ecfg_packet; //packet for direct test access
/*------------------------CODE BODY---------------------------------------*/
@ -80,22 +86,22 @@ module ecfg_tx (/*AUTOARG*/
/*****************************/
//read/write decode
assign ecfg_write = mi_en & mi_we & (mi_addr[19:16]==GROUP);
assign ecfg_read = mi_en & ~mi_we & (mi_addr[19:16]==GROUP);
assign ecfg_write = mi_en & mi_we;
assign ecfg_read = mi_en & ~mi_we;
//Config write enables
assign ecfg_tx_config_write = ecfg_write & (mi_addr[RFAW+1:2]==`ELTXCFG);
assign ecfg_tx_status_write = ecfg_write & (mi_addr[RFAW+1:2]==`ELTXSTATUS);
assign ecfg_tx_gpio_write = ecfg_write & (mi_addr[RFAW+1:2]==`ELTXGPIO);
assign ecfg_tx_test_write = ecfg_write & (mi_addr[RFAW+1:2]==`ELTXTEST);
assign ecfg_tx_dstaddr_write = ecfg_write & (mi_addr[RFAW+1:2]==`ELTXDSTADDR);
assign ecfg_tx_data_write = ecfg_write & (mi_addr[RFAW+1:2]==`ELTXDATA);
assign ecfg_tx_srcaddr_write = ecfg_write & (mi_addr[RFAW+1:2]==`ELTXSRCADDR);
assign ecfg_tx_config_write = ecfg_write & (mi_addr[RFAW+1:2]==`ELTXCFG);
assign ecfg_tx_status_write = ecfg_write & (mi_addr[RFAW+1:2]==`ELTXSTATUS);
assign ecfg_tx_gpio_write = ecfg_write & (mi_addr[RFAW+1:2]==`ELTXGPIO);
assign ecfg_tx_test_write = ecfg_write & (mi_addr[RFAW+1:2]==`ELTXTEST);
assign ecfg_tx_dstaddr_write= ecfg_write & (mi_addr[RFAW+1:2]==`ELTXDSTADDR);
assign ecfg_tx_data_write = ecfg_write & (mi_addr[RFAW+1:2]==`ELTXDATA);
assign ecfg_tx_srcaddr_write= ecfg_write & (mi_addr[RFAW+1:2]==`ELTXSRCADDR);
//###########################
//# TX CONFIG
//###########################
always @ (posedge sys_clk)
always @ (posedge clk)
if(reset)
ecfg_tx_config_reg[10:0] <= 11'b0;
else if (ecfg_tx_config_write)
@ -107,26 +113,26 @@ module ecfg_tx (/*AUTOARG*/
assign ecfg_tx_ctrlmode[3:0] = ecfg_tx_config_reg[7:4];
assign ecfg_tx_ctrlmode_bp = ecfg_tx_config_reg[8];
assign ecfg_tx_gpio_enable = (ecfg_tx_config_reg[10:9]==2'b01);
assign ecfg_tx_tp_enable = (ecfg_tx_config_reg[10:9]==2'b10);//test pattern
//###########################1
//# STATUS REGISTER
assign ecfg_tx_tp_enable = (ecfg_tx_config_reg[10:9]==2'b10);
//###########################
always @ (posedge sys_clk)
//# STATUS REGISTER
//###########################
always @ (posedge clk)
if(reset)
ecfg_tx_status_reg[15:0] <= 'd0;
else if(ecfg_tx_status_write)
ecfg_tx_status_reg[15:0] <= mi_din[15:0];
else
begin
ecfg_tx_status_reg[2:0] <= ecfg_tx_status_reg[2:0] | ecfg_tx_debug[2:0];
ecfg_tx_status_reg[2:0]<= ecfg_tx_status_reg[2:0] | ecfg_tx_debug[2:0];
ecfg_tx_status_reg[15:3] <= ecfg_tx_debug[15:3];
end
//###########################
//# GPIO DATA
//###########################
always @ (posedge sys_clk)
always @ (posedge clk)
if(reset)
ecfg_tx_gpio_reg[8:0] <= 'd0;
else if (ecfg_tx_gpio_write)
@ -143,7 +149,7 @@ module ecfg_tx (/*AUTOARG*/
//7:4 = ctrlmode
//8 = continuous-loop mode
always @ (posedge sys_clk)
always @ (posedge clk)
if(reset)
ecfg_tx_test_reg[8:0] <= 'd0;
else if (ecfg_tx_test_write)
@ -154,7 +160,7 @@ module ecfg_tx (/*AUTOARG*/
//###########################
//# DSTADDR REGISTER
//###########################
always @ (posedge sys_clk)
always @ (posedge clk)
if(reset)
ecfg_tx_dstaddr_reg[31:0] <= 'd0;
else if (ecfg_tx_dstaddr_write)
@ -163,7 +169,7 @@ module ecfg_tx (/*AUTOARG*/
//###########################
//# DATA REGISTER
//###########################
always @ (posedge sys_clk)
always @ (posedge clk)
if(reset)
ecfg_tx_data_reg[31:0] <= 'd0;
else if (ecfg_tx_data_write)
@ -172,7 +178,7 @@ module ecfg_tx (/*AUTOARG*/
//###########################
//# SRCADDR REGISTER
//###########################
always @ (posedge sys_clk)
always @ (posedge clk)
if(reset)
ecfg_tx_srcaddr_reg[31:0] <= 'd0;
else if (ecfg_tx_srcaddr_write)
@ -189,7 +195,7 @@ module ecfg_tx (/*AUTOARG*/
ecfg_tx_test_reg[7:0]
};
always @ (posedge sys_clk or posedge reset)
always @ (posedge clk or posedge reset)
if(reset)
ecfg_access <= 0;
else if(ecfg_tx_test_write & mi_din[0])
@ -204,7 +210,7 @@ module ecfg_tx (/*AUTOARG*/
//###############################
//Pipelineing readback
always @ (posedge sys_clk)
always @ (posedge clk)
if(ecfg_read)
case(mi_addr[RFAW+1:2])
`ELTXCFG: mi_dout[31:0] <= {21'b0, ecfg_tx_config_reg[10:0]};

155
elink/hdl/elink.v
View File

@ -2,9 +2,8 @@
###DESCRIPTION
The "elink" is a low-latency/high-speed interface for communicating between
FPGAs and ASICs (such as Epiphany) that implement the elink protocol.
The interface "should" achieve a peak throughput of 8 Gbit/s in FPGAs with
24 available LVDS signal pairs.
FPGAs and ASICs (such as Epiphany). The interface "should" achieve a peak throughput of
8 Gbit/s (duplex) in modern FPGAs using 24 available LVDS signal pairs.
###ELINK INTERFACE I/O SIGNALS
@ -32,8 +31,9 @@
embox_not_empty| O | Mailbox not empty (connect to interrupt line)
embox_full | O | Mailbox is full indicator
###BUS INTERFACE
###SYSTEM INTERFACE
The elink has a 64 bit data AXI master and 32-bit data AXI slave interface
for connecting to a standard AXI network.
@ -93,13 +93,9 @@
###ELINK MEMORY MAP
The elink has an parameter called 'ELINKID' that can be configured by
the module instantiating the elink.
Each elink has a 12 bit ID that that gets matched to bits [31:20] of the
incoming address.
REGISTER | ADDRESS | NOTES
------------| --------|------
ESYSRESET | 0xF0000 | Soft reset
ESYSTX | 0xF0004 | Elink tranmit config
ESYSRX | 0xF0008 | Elink receiver config
ESYSCLK | 0xF000C | Clock config
ESYSCOREID | 0xF0010 | ID to drive to Epiphany chip
@ -113,7 +109,9 @@
ESYSMMUTX | 0xD0000 | Start of transmit MMU lookup table (tbd)
###ELINK CONFIGURATION REGISTERS
REGISTER | DESCRIPTION
REGISTER | ADDR | DESCRIPTION
---------- | --------------
ESYSRESET | (elink reset register)
[0] | 0: elink is active
@ -188,39 +186,7 @@
[9] | rx_wait_rd
[10] | rx_wait_wr
-------------------------------------------------------------
ESYSDEBUG | (various debug signals from elink)
[31] | embox_not_empty
[30] | emesh_rx_rd_wait
[29] | emesh_rx_wr_wait
[28] | esaxi_emrr_rd_en
[27] | emrr_full
[26] | emrr_progfull
[25] | emrr_wr_en
[24] | emaxi_emrq_rd_en
[23] | emrq_progfull
[22] | emrq_wr_en
[21] | emaxi_emwr_rd_en
[20] | emwr_progfull
[19] | emwr_wr_en (rx)
[18] | e_tx_rd_wait
[17] | e_tx_wr_wait
[16] | emrr_rd_en
[15] | emaxi_emrr_prog_full
[14] | emaxi_emrr_wr_en
[13] | emrq_rd_en
[12] | esaxi_emrq_prog_full
[11] | esaxi_emrq_wr_en
[10] | emwr_rd_en
[9] | esaxi_emwr_prog_full
[8] | esaxi_emwr_wr_en
[7] | reserved
[6] | sticky emrr_full (rx)
[5] | sticky emrq_full (rx)
[4] | sticky emwr_full (rx)
[3] | sticky emaxi_emrr_full (tx)
[2] | sticky esaxi_emrq_full (tx)
[1] | sticky esaxi_emwr_full (tx)
[0] | sticky embox_full (mailbox)
###INTERNAL STRUCTURE
```
@ -253,18 +219,21 @@ elink - Top level level AXI elink peripheral
module elink(/*AUTOARG*/
// Outputs
colid, rowid, chip_resetb, cclk_p, cclk_n, rxo_wr_wait_p,
rxo_wr_wait_n, rxo_rd_wait_p, rxo_rd_wait_n, txo_lclk_p,
txo_lclk_n, txo_frame_p, txo_frame_n, txo_data_p, txo_data_n,
mailbox_not_empty, mailbox_full, timeout, rxwr_access, rxwr_packet,
rxrd_access, rxrd_packet, rxrr_access, rxrr_packet, txwr_wait,
txrd_wait, txrr_wait,
mi_tx_we, mi_tx_mmu_en, mi_tx_din, mi_tx_cfg_en, mi_tx_addr,
mi_rx_we, mi_rx_mmu_en, mi_rx_dma_en, mi_rx_din, mi_rx_cfg_en,
mi_rx_addr, rx_lclk_div4, tx_lclk_div4, colid, rowid, chip_resetb,
cclk_p, cclk_n, rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p,
rxo_rd_wait_n, txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n,
txo_data_p, txo_data_n, mailbox_not_empty, mailbox_full, timeout,
rxwr_access, rxwr_packet, rxrd_access, rxrd_packet, rxrr_access,
rxrr_packet, txwr_wait, txrd_wait, txrr_wait,
// Inputs
mi_txmmu_en, mi_txcfg_en, mi_rxmmu_en, mi_rxcfg_en, mi_dma_en,
hard_reset, clkin, clkbypass, rxi_lclk_p, rxi_lclk_n, rxi_frame_p,
rxi_frame_n, rxi_data_p, rxi_data_n, txi_wr_wait_p, txi_wr_wait_n,
txi_rd_wait_p, txi_rd_wait_n, sys_clk, rxwr_wait, rxrd_wait,
rxrr_wait, txwr_access, txwr_packet, txrd_access, txrd_packet,
txrr_access, txrr_packet
txi_rd_wait_p, txi_rd_wait_n, sys_clk, mi_en, mi_we, mi_addr,
mi_din, mi_dout, rxwr_wait, rxrd_wait, rxrr_wait, txwr_access,
txwr_packet, txrd_access, txrd_packet, txrr_access, txrr_packet
);
parameter AW = 32;
@ -278,8 +247,9 @@ module elink(/*AUTOARG*/
input hard_reset; // active high synhcronous hardware reset
input clkin; // clock for pll
input [2:0] clkbypass; // bypass clocks for elinks w/o pll
// "advanced", tie to zero if not used
output rx_lclk_div4; // rxi_lclk clock divided by 4
output tx_lclk_div4; // txo_lclk clock divided by 4
/********************************/
/*EPIPHANY INTERFACE (I/O PINS) */
/********************************/
@ -310,18 +280,24 @@ module elink(/*AUTOARG*/
output mailbox_not_empty;
output mailbox_full;
/*****************************/
/*****************************/tx
/*READBACK TIMEOUT */
/*****************************/
output timeout;
/*****************************/
/*"System" Interface */
/*****************************/
/*****************************/
//One clock to rule them all..
input sys_clk;
input sys_clk;
//Primary configuration interface
input mi_en;
input mi_we; //only 32 aligned accesses allowed
input [19:0] mi_addr;//address is complete byte address
input [31:0] mi_din;
input [31:0] mi_dout;
//Master Write (from RX)
output rxwr_access;
output [PW-1:0] rxwr_packet;
@ -357,7 +333,27 @@ module elink(/*AUTOARG*/
/*#############################################*/
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input mi_dma_en; // To erx of erx.v
input mi_rxcfg_en; // To erx of erx.v
input mi_rxmmu_en; // To erx of erx.v
input mi_txcfg_en; // To etx of etx.v
input mi_txmmu_en; // To etx of etx.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [19:0] mi_rx_addr; // From ecfg_if of ecfg_if.v
output mi_rx_cfg_en; // From ecfg_if of ecfg_if.v
output [63:0] mi_rx_din; // From ecfg_if of ecfg_if.v
output mi_rx_dma_en; // From ecfg_if of ecfg_if.v
output mi_rx_mmu_en; // From ecfg_if of ecfg_if.v
output mi_rx_we; // From ecfg_if of ecfg_if.v
output [19:0] mi_tx_addr; // From ecfg_if of ecfg_if.v
output mi_tx_cfg_en; // From ecfg_if of ecfg_if.v
output [63:0] mi_tx_din; // From ecfg_if of ecfg_if.v
output mi_tx_mmu_en; // From ecfg_if of ecfg_if.v
output mi_tx_we; // From ecfg_if of ecfg_if.v
// End of automatics
//wires
wire [31:0] mi_rd_data;
@ -368,37 +364,48 @@ module elink(/*AUTOARG*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [15:0] ecfg_clk_settings; // From ecfg_base of ecfg_base.v
wire etx_read; // From etx of etx.v
wire [19:0] mi_addr; // From ecfg_if of ecfg_if.v
wire [63:0] mi_din; // From ecfg_if of ecfg_if.v
wire mi_basecfg_en; // From ecfg_if of ecfg_if.v
wire [31:0] mi_el_dout; // From ecfg_base of ecfg_base.v
wire mi_en; // From ecfg_if of ecfg_if.v
wire [31:0] mi_mailbox_dout; // From emailbox of emailbox.v
wire mi_mailbox_en; // From ecfg_if of ecfg_if.v
wire [31:0] mi_rx_dout; // From erx of erx.v
wire [31:0] mi_tx_dout; // From etx of etx.v
wire mi_we; // From ecfg_if of ecfg_if.v
wire reset; // From ereset of ereset.v
wire soft_reset; // From ecfg_base of ecfg_base.v
wire tx_lclk; // From eclocks of eclocks.v
wire tx_lclk90; // From eclocks of eclocks.v
wire tx_lclk_div4; // From eclocks of eclocks.v
// End of automatics
/***********************************************************/
/*ELINK CONFIGURATION INTERFACE */
/***********************************************************/
defparam ecfg_if.ID=ID;
ecfg_if ecfg_if(
/*AUTOINST*/
// Outputs
.txwr_wait (txwr_wait),
.txrd_wait (txrd_wait),
.mi_en (mi_en),
.mi_tx_cfg_en (mi_tx_cfg_en),
.mi_tx_mmu_en (mi_tx_mmu_en),
.mi_tx_we (mi_tx_we),
.mi_tx_addr (mi_tx_addr[19:0]),
.mi_tx_din (mi_tx_din[63:0]),
.mi_rx_cfg_en (mi_rx_cfg_en),
.mi_rx_dma_en (mi_rx_dma_en),
.mi_rx_mmu_en (mi_rx_mmu_en),
.mi_rx_we (mi_rx_we),
.mi_rx_addr (mi_rx_addr[19:0]),
.mi_rx_din (mi_rx_din[63:0]),
.mi_basecfg_en (mi_basecfg_en),
.mi_mailbox_en (mi_mailbox_en),
.mi_we (mi_we),
.mi_addr (mi_addr[19:0]),
.mi_din (mi_din[63:0]),
// Inputs
.sys_clk (sys_clk),
.tx_lclk_div4 (tx_lclk_div4),
.rx_lclk_div4 (rx_lclk_div4),
.reset (reset),
.txwr_access (txwr_access),
.txwr_packet (txwr_packet[PW-1:0]),
@ -417,6 +424,7 @@ module elink(/*AUTOARG*/
/*ecfg_base AUTO_TEMPLATE (
.mi_dout (mi_el_dout[]),
.mi_en (mi_basecfg_en[]),
.ecfg_reset (reset),
.clk (mi_clk),
)
@ -434,7 +442,7 @@ module elink(/*AUTOARG*/
// Inputs
.hard_reset (hard_reset),
.sys_clk (sys_clk),
.mi_en (mi_en),
.mi_en (mi_basecfg_en), // Templated
.mi_we (mi_we),
.mi_addr (mi_addr[19:0]),
.mi_din (mi_din[31:0]));
@ -473,6 +481,7 @@ module elink(/*AUTOARG*/
/***********************************************************/
/*emailbox AUTO_TEMPLATE (
.mi_dout (mi_mailbox_dout[]),
.mi_en (mi_mailbox_en),
);
*/
@ -485,7 +494,7 @@ module elink(/*AUTOARG*/
// Inputs
.reset (reset),
.sys_clk (sys_clk),
.mi_en (mi_en),
.mi_en (mi_mailbox_en), // Templated
.mi_we (mi_we),
.mi_addr (mi_addr[19:0]),
.mi_din (mi_din[63:0]));
@ -518,10 +527,10 @@ module elink(/*AUTOARG*/
.rxrr_access (rxrr_access),
.rxrr_packet (rxrr_packet[PW-1:0]),
.mi_dout (mi_rx_dout[31:0]), // Templated
.rx_lclk_div4 (rx_lclk_div4),
.timeout (timeout),
// Inputs
.reset (reset),
.sys_clk (sys_clk),
.rxi_lclk_p (rxi_lclk_p),
.rxi_lclk_n (rxi_lclk_n),
.rxi_frame_p (rxi_frame_p),
@ -531,7 +540,9 @@ module elink(/*AUTOARG*/
.rxwr_wait (rxwr_wait),
.rxrd_wait (rxrd_wait),
.rxrr_wait (rxrr_wait),
.mi_en (mi_en),
.mi_rxcfg_en (mi_rxcfg_en),
.mi_dma_en (mi_dma_en),
.mi_rxmmu_en (mi_rxmmu_en),
.mi_we (mi_we),
.mi_addr (mi_addr[19:0]),
.mi_din (mi_din[31:0]),
@ -567,8 +578,8 @@ module elink(/*AUTOARG*/
.tx_lclk (tx_lclk),
.tx_lclk90 (tx_lclk90),
.tx_lclk_div4 (tx_lclk_div4),
.sys_clk (sys_clk),
.mi_en (mi_en),
.mi_txcfg_en (mi_txcfg_en),
.mi_txmmu_en (mi_txmmu_en),
.mi_we (mi_we),
.mi_addr (mi_addr[19:0]),
.mi_din (mi_din[31:0]),

50
elink/hdl/elink_regmap.v
View File

@ -3,7 +3,8 @@
//[31:20] = LINKID
//[19:16] = GROUP SELECT
//[15] = MMU SELECT (for RX/TX)
//[14:6] = USED BY MMU ONLY
//[14:6] = USED BY MMU ONLY
//[7:6] = 16 register blocks
//[5:2] = REGISTER ADDRESS (0..15)
//[1:0] = IGNORED (no byte access)
@ -12,31 +13,46 @@
`define EGROUP_TX 4'hE
`define EGROUP_RX 4'hD
//REG BLOCK [7:6]
`define EBLOCK0 2'h0
`define EBLOCK1 2'h1
`define EBLOCK2 2'h2
`define EBLOCK3 2'h3
//BLOCK0
`define ELRESET 4'h0 //E0040-reset
`define ELCLK 4'h1 //E0044-clock configuration
`define ELCHIPID 4'h2 //E0048-Epiphany chip id for colid/rowid pins
`define ELVERSION 4'h3 //E004c-version #
//ELINK TX registers
//BLOCK1
`define ELTXCFG 4'h0 //E0000-config
`define ELTXSTATUS 4'h1 //E0004-tx status
`define ELTXGPIO 4'h2 //E0008-direct data for tx pins
`define ELRESET 4'h3 //E000C-reset
`define ELCLK 4'h4 //E0010-clock configuration
`define ELCHIPID 4'h5 //E0014-Epiphany chip id for colid/rowid pins
`define ELVERSION 4'h6 //E0018-version #
`define ELTXTEST 4'h7 //E001C-control for driving SERDES directly
`define ELTXDSTADDR 4'h8 //E0020-static addr (for testing)
`define ELTXDATA 4'h9 //E0024-static data (for testing)
`define ELTXSRCADDR 4'hA //E0028-static source addr (for testing)
`define ELTXRES 4'h3 //E000C-reservec
`define ELTXTEST 4'h4 //E0020-control for driving SERDES directly
`define ELTXDSTADDR 4'h5 //E0024-static addr (for testing)
`define ELTXDATA 4'h6 //E0028-static data (for testing)
`define ELTXSRCADDR 4'h7 //E002c-static source addr (for testing)
//ELINK RX registers
//BLOCK0
`define ELRXCFG 4'h0 //D0000-config
`define ELRXSTATUS 4'h1 //D0004-status register
`define ELRXGPIO 4'h2 //D0008-sampled data
`define ELRXRR 4'h3 //D000C-read response address
`define ELRXBASE 4'h4 //D0010-memory base for remap
`define ELRESERVED 4'h5 //D0014-reserved
`define EMAILBOXLO 4'h6 //D0018-mailbox
`define EMAILBOXHI 4'h7 //D001c-mailbox
`define EDMACFG 4'h8 //D0020-dma
`define EDMACOUNT 4'h9 //D0024-dma
`define EDMASTRIDE 4'hA //D0028-dma
`define EDMASRCADDR 4'hB //D002c-dma
`define EDMADSTADDR 4'hC //D0028-dma
`define EDMASTATUS 4'hD //D0030-dma
//BLOCK1
`define EMAILBOXLO 4'h0 //D0018-mailbox
`define EMAILBOXHI 4'h1 //D001c-mailbox
//BLOCk2
`define EDMACFG 4'h0 //D0020-dma
`define EDMACOUNT 4'h1 //D0024-dma
`define EDMASTRIDE 4'h2 //D0028-dma
`define EDMASRCADDR 4'h3 //D002c-dma
`define EDMADSTADDR 4'h4 //D0028-dma
`define EDMASTATUS 4'h5 //D0030-dma

52
elink/hdl/erx.v
View File

@ -2,11 +2,12 @@ module erx (/*AUTOARG*/
// Outputs
rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p, rxo_rd_wait_n,
rxwr_access, rxwr_packet, rxrd_access, rxrd_packet, rxrr_access,
rxrr_packet, mi_dout, timeout,
rxrr_packet, mi_dout, rx_lclk_div4, timeout,
// Inputs
reset, sys_clk, rxi_lclk_p, rxi_lclk_n, rxi_frame_p, rxi_frame_n,
rxi_data_p, rxi_data_n, rxwr_wait, rxrd_wait, rxrr_wait, mi_en,
mi_we, mi_addr, mi_din, etx_read
reset, rxi_lclk_p, rxi_lclk_n, rxi_frame_p, rxi_frame_n,
rxi_data_p, rxi_data_n, rxwr_wait, rxrd_wait, rxrr_wait,
mi_rxcfg_en, mi_dma_en, mi_rxmmu_en, mi_we, mi_addr, mi_din,
etx_read
);
parameter AW = 32;
@ -16,7 +17,6 @@ module erx (/*AUTOARG*/
//reset
input reset;
input sys_clk;
//FROM IO Pins
input rxi_lclk_p, rxi_lclk_n; //link rx clock input
@ -41,12 +41,15 @@ module erx (/*AUTOARG*/
input rxrr_wait;
//Register Access Interface
input mi_en;
input mi_rxcfg_en;
input mi_dma_en;
input mi_rxmmu_en;
input mi_we;
input [19:0] mi_addr;
input [31:0] mi_din;
output [31:0] mi_dout;
output rx_lclk_div4; //for synchronization with sys_clk
//Starts timeout counter
input etx_read;
@ -81,7 +84,6 @@ module erx (/*AUTOARG*/
wire [63:0] rx_data_par; // From erx_io of erx_io.v
wire rx_enable; // From ecfg_rx of ecfg_rx.v
wire [7:0] rx_frame_par; // From erx_io of erx_io.v
wire rx_lclk_div4; // From erx_io of erx_io.v
wire rx_rd_wait; // From erx_disty of erx_disty.v
wire rx_wr_wait; // From erx_disty of erx_disty.v
wire rxrd_fifo_access; // From erx_disty of erx_disty.v
@ -113,6 +115,8 @@ module erx (/*AUTOARG*/
defparam ecfg_rx.GROUP=`EGROUP_RX;
/*ecfg_rx AUTO_TEMPLATE (.mi_dout (mi_rx_cfg_dout[DW-1:0]),
.mi_en (mi_rxcfg_en),
.clk (rx_lclk_div4),
);
*/
@ -129,8 +133,8 @@ module erx (/*AUTOARG*/
.timer_cfg (timer_cfg[1:0]),
// Inputs
.reset (reset),
.sys_clk (sys_clk),
.mi_en (mi_en),
.clk (rx_lclk_div4), // Templated
.mi_en (mi_rxcfg_en), // Templated
.mi_we (mi_we),
.mi_addr (mi_addr[19:0]),
.mi_din (mi_din[31:0]),
@ -141,12 +145,11 @@ module erx (/*AUTOARG*/
/************************************************************/
defparam ecfg_rx.GROUP=`EGROUP_RX;
erx_mux erx_mux (/*AUTOINST*/
erx_mux erx_mux (.sys_clk (rx_lclk_div4),
/*AUTOINST*/
// Outputs
.mi_dout (mi_dout[DW-1:0]),
// Inputs
.sys_clk (sys_clk),
.mi_en (mi_en),
.mi_addr (mi_addr[19:0]),
.mi_rx_cfg_dout (mi_rx_cfg_dout[DW-1:0]),
.mi_rx_edma_dout (mi_rx_edma_dout[DW-1:0]),
@ -187,7 +190,7 @@ module erx (/*AUTOARG*/
.prog_full (@"(substring vl-cell-name 0 4)"_fifo_wait),
.valid (@"(substring vl-cell-name 0 4)"_access),
// Inputs
.rd_clk (sys_clk),
.rd_clk (rx_lclk_div4),
.wr_clk (rx_lclk_div4),
.wr_en (@"(substring vl-cell-name 0 4)"_fifo_access),
.rd_en (~@"(substring vl-cell-name 0 4)"_wait & ~@"(substring vl-cell-name 0 4)"_empty),
@ -212,7 +215,7 @@ module erx (/*AUTOARG*/
// Inputs
.reset (reset), // Templated
.wr_clk (rx_lclk_div4), // Templated
.rd_clk (sys_clk), // Templated
.rd_clk (rx_lclk_div4), // Templated
.wr_en (rxrd_fifo_access), // Templated
.din (rxrd_fifo_packet[PW-1:0]), // Templated
.rd_en (~rxrd_wait & ~rxrd_empty)); // Templated
@ -231,7 +234,7 @@ module erx (/*AUTOARG*/
// Inputs
.reset (reset), // Templated
.wr_clk (rx_lclk_div4), // Templated
.rd_clk (sys_clk), // Templated
.rd_clk (rx_lclk_div4), // Templated
.wr_en (rxwr_fifo_access), // Templated
.din (rxwr_fifo_packet[PW-1:0]), // Templated
.rd_en (~rxwr_wait & ~rxwr_empty)); // Templated
@ -250,7 +253,7 @@ module erx (/*AUTOARG*/
// Inputs
.reset (reset), // Templated
.wr_clk (rx_lclk_div4), // Templated
.rd_clk (sys_clk), // Templated
.rd_clk (rx_lclk_div4), // Templated
.wr_en (rxrr_fifo_access), // Templated
.din (rxrr_fifo_packet[PW-1:0]), // Templated
.rd_en (~rxrr_wait & ~rxrr_empty)); // Templated
@ -300,6 +303,7 @@ module erx (/*AUTOARG*/
/************************************************************/
/*edma AUTO_TEMPLATE (.clk (rx_lclk_div4),
.mi_en (mi_dma_en),
.edma_access (edma_access),
.mi_dout (mi_rx_edma_dout[DW-1:0]),
.edma_access (edma_access),
@ -325,7 +329,7 @@ module erx (/*AUTOARG*/
// Inputs
.reset (reset),
.clk (rx_lclk_div4), // Templated
.mi_en (mi_en),
.mi_en (mi_dma_en), // Templated
.mi_we (mi_we),
.mi_addr (mi_addr[19:0]),
.mi_din (mi_din[31:0]),
@ -340,11 +344,12 @@ module erx (/*AUTOARG*/
//Inputs
.emesh_\(.*\)_in (emesh_remap_\1[]),
.mmu_en (mmu_enable),
.emesh_clk (rx_lclk_div4),
.clk (rx_lclk_div4),
.mi_dout (mi_rx_emmu_dout[DW-1:0]),
.emesh_packet_hi_out (),
.mmu_bp (remap_bypass),
.emesh_wait_in (erx_wait),
.emesh_wait_in (erx_wait),
.mi_en (mi_rxmmu_en),
);
*/
@ -358,14 +363,13 @@ module erx (/*AUTOARG*/
.emesh_packet_hi_out (), // Templated
// Inputs
.reset (reset),
.sys_clk (sys_clk),
.clk (rx_lclk_div4), // Templated
.mmu_en (mmu_enable), // Templated
.mmu_bp (remap_bypass), // Templated
.mi_en (mi_en),
.mi_en (mi_rxmmu_en), // Templated
.mi_we (mi_we),
.mi_addr (mi_addr[19:0]),
.mi_din (mi_din[DW-1:0]),
.emesh_clk (rx_lclk_div4), // Templated
.emesh_access_in (emesh_remap_access), // Templated
.emesh_packet_in (emesh_remap_packet[PW-1:0]), // Templated
.emesh_wait_in (erx_wait)); // Templated
@ -449,7 +453,7 @@ module erx (/*AUTOARG*/
/************************************************************/
/*Debug signals */
/************************************************************/
always @ (posedge sys_clk)
always @ (posedge rx_lclk_div4)
begin
debug_vector[15:0] <= {2'b0, //15:14
rx_rd_wait, //13

7
elink/hdl/erx_mux.v
View File

@ -2,8 +2,7 @@ module erx_mux (/*AUTOARG*/
// Outputs
mi_dout,
// Inputs
sys_clk, mi_en, mi_addr, mi_rx_cfg_dout, mi_rx_edma_dout,
mi_rx_emmu_dout
sys_clk, mi_addr, mi_rx_cfg_dout, mi_rx_edma_dout, mi_rx_emmu_dout
);
parameter DW = 32;
@ -12,7 +11,7 @@ module erx_mux (/*AUTOARG*/
input sys_clk;
//Needed for selecting data
input mi_en;
input [19:0] mi_addr;
input [DW-1:0] mi_rx_cfg_dout;
@ -20,5 +19,7 @@ module erx_mux (/*AUTOARG*/
input [DW-1:0] mi_rx_emmu_dout;
output [DW-1:0] mi_dout;
endmodule // erx_mux

43
elink/hdl/etx.v
View File

@ -3,8 +3,8 @@ module etx(/*AUTOARG*/
mi_dout, txrd_wait, txwr_wait, txrr_wait, etx_read, txo_lclk_p,
txo_lclk_n, txo_frame_p, txo_frame_n, txo_data_p, txo_data_n,
// Inputs
reset, tx_lclk, tx_lclk90, tx_lclk_div4, sys_clk, mi_en, mi_we,
mi_addr, mi_din, txrd_access, txrd_packet, txwr_access,
reset, tx_lclk, tx_lclk90, tx_lclk_div4, mi_txcfg_en, mi_txmmu_en,
mi_we, mi_addr, mi_din, txrd_access, txrd_packet, txwr_access,
txwr_packet, txrr_access, txrr_packet, txi_wr_wait_p,
txi_wr_wait_n, txi_rd_wait_p, txi_rd_wait_n
);
@ -18,10 +18,10 @@ module etx(/*AUTOARG*/
input tx_lclk; // high speed serdes clock
input tx_lclk90; // lclk for output
input tx_lclk_div4; // slow speed parallel clock
input sys_clk; // main system clock
//Register Access Interface
input mi_en;
input mi_txcfg_en;
input mi_txmmu_en;
input mi_we; // single we, must write 32 bit words
input [19:0] mi_addr; // complete physical address (no shifting!)
input [31:0] mi_din;
@ -105,7 +105,9 @@ module etx(/*AUTOARG*/
/************************************************************/
/* ETX CONFIGURATION */
/************************************************************/
/*ecfg_tx AUTO_TEMPLATE (.mi_dout (mi_tx_cfg_dout[DW-1:0]),
/*ecfg_tx AUTO_TEMPLATE (.mi_dout (mi_tx_cfg_dout[DW-1:0]),
.mi_en (mi_txcfg_en),
.clk (tx_lclk_div4),
);
*/
defparam ecfg_tx.GROUP=`EGROUP_TX;
@ -118,16 +120,16 @@ module etx(/*AUTOARG*/
.ecfg_tx_mmu_enable (ecfg_tx_mmu_enable),
.ecfg_tx_gpio_enable(ecfg_tx_gpio_enable),
.ecfg_tx_tp_enable (ecfg_tx_tp_enable),
.ecfg_tx_ctrlmode (ecfg_tx_ctrlmode[3:0]),
.ecfg_tx_ctrlmode_bp(ecfg_tx_ctrlmode_bp),
.ecfg_tx_remap_enable(ecfg_tx_remap_enable),
.ecfg_dataout (ecfg_dataout[8:0]),
.ecfg_access (ecfg_access),
.ecfg_packet (ecfg_packet[PW-1:0]),
.ecfg_tx_ctrlmode (ecfg_tx_ctrlmode[3:0]),
.ecfg_tx_ctrlmode_bp(ecfg_tx_ctrlmode_bp),
// Inputs
.reset (reset),
.sys_clk (sys_clk),
.mi_en (mi_en),
.clk (tx_lclk_div4), // Templated
.mi_en (mi_txcfg_en), // Templated
.mi_we (mi_we),
.mi_addr (mi_addr[19:0]),
.mi_din (mi_din[31:0]),
@ -137,13 +139,12 @@ module etx(/*AUTOARG*/
/* ETX READBACK MUX */
/************************************************************/
etx_mux etx_mux (/*AUTOINST*/
etx_mux etx_mux (.sys_clk (tx_lclk_div4),
/*AUTOINST*/
// Outputs
.mi_dout (mi_dout[DW-1:0]),
// Inputs
.sys_clk (sys_clk),
.reset (reset),
.mi_en (mi_en),
.mi_addr (mi_addr[19:0]),
.mi_tx_emmu_dout (mi_tx_emmu_dout[DW-1:0]),
.mi_tx_cfg_dout (mi_tx_cfg_dout[DW-1:0]));
@ -162,7 +163,7 @@ module etx(/*AUTOARG*/
.prog_full (@"(substring vl-cell-name 0 4)"_fifo_prog_full),
// Inputs
.rd_clk (tx_lclk_div4),
.wr_clk (sys_clk),
.wr_clk (tx_lclk_div4),
.wr_en (@"(substring vl-cell-name 0 4)"_access),
.rd_en (@"(substring vl-cell-name 0 4)"_fifo_read),
.reset (reset),
@ -184,7 +185,7 @@ module etx(/*AUTOARG*/
.valid (), // Templated
// Inputs
.reset (reset), // Templated
.wr_clk (sys_clk), // Templated
.wr_clk (tx_lclk_div4), // Templated
.rd_clk (tx_lclk_div4), // Templated
.din (txwr_packet[PW-1:0]), // Templated
.rd_en (txwr_fifo_read)); // Templated
@ -201,7 +202,7 @@ module etx(/*AUTOARG*/
.valid (), // Templated
// Inputs
.reset (reset), // Templated
.wr_clk (sys_clk), // Templated
.wr_clk (tx_lclk_div4), // Templated
.rd_clk (tx_lclk_div4), // Templated
.din (txrd_packet[PW-1:0]), // Templated
.rd_en (txrd_fifo_read)); // Templated
@ -219,7 +220,7 @@ module etx(/*AUTOARG*/
.valid (), // Templated
// Inputs
.reset (reset), // Templated
.wr_clk (sys_clk), // Templated
.wr_clk (tx_lclk_div4), // Templated
.rd_clk (tx_lclk_div4), // Templated
.wr_en (txrr_access), // Templated
.din (txrr_packet[PW-1:0]), // Templated
@ -290,12 +291,13 @@ module etx(/*AUTOARG*/
.emesh_\(.*\)_out (emmu_\1[]),
.mmu_en (ecfg_tx_mmu_enable),
.mmu_bp (etx_rr),
.emesh_clk (tx_lclk_div4),
.clk (tx_lclk_div4),
.emmu_access_out (emmu_access),
.emmu_packet_out (emmu_packet[PW-1:0]),
.mi_dout (mi_tx_emmu_dout[DW-1:0]),
.emesh_wait_in (etx_wait),
.emesh_packet_hi_out (),
.mi_en (mi_txmmu_en),
);
*/
@ -309,14 +311,13 @@ module etx(/*AUTOARG*/
.emesh_packet_hi_out (), // Templated
// Inputs
.reset (reset),
.sys_clk (sys_clk),
.clk (tx_lclk_div4), // Templated
.mmu_en (ecfg_tx_mmu_enable), // Templated
.mmu_bp (etx_rr), // Templated
.mi_en (mi_en),
.mi_en (mi_txmmu_en), // Templated
.mi_we (mi_we),
.mi_addr (mi_addr[19:0]),
.mi_din (mi_din[DW-1:0]),
.emesh_clk (tx_lclk_div4), // Templated
.emesh_access_in (etx_remap_access), // Templated
.emesh_packet_in (etx_remap_packet[PW-1:0]), // Templated
.emesh_wait_in (etx_wait)); // Templated
@ -387,7 +388,7 @@ module etx(/*AUTOARG*/
/************************************************************/
/*Debug signals (async sampling) */
/************************************************************/
always @ (posedge sys_clk)
always @ (posedge tx_lclk_div4)
begin
ecfg_tx_debug[15:0] <= {2'b0, //15:14
etx_rd_wait, //13

14
elink/hdl/etx_mux.v
View File

@ -2,22 +2,26 @@ module etx_mux (/*AUTOARG*/
// Outputs
mi_dout,
// Inputs
sys_clk, reset, mi_en, mi_addr, mi_tx_emmu_dout, mi_tx_cfg_dout
sys_clk, reset, mi_addr, mi_tx_emmu_dout, mi_tx_cfg_dout
);
parameter AW = 32;
parameter DW = 32;
parameter AW = 32;
parameter DW = 32;
parameter GROUP = 0;
//Needed for selecting data
input sys_clk;
input reset;
input mi_en;
input [19:0] mi_addr;
input [DW-1:0] mi_tx_emmu_dout;
input [DW-1:0] mi_tx_cfg_dout;
output [DW-1:0] mi_dout;
endmodule // etx_mux

14
emailbox/hdl/emailbox.v
View File

@ -74,16 +74,16 @@ module emailbox (/*AUTOARG*/
/*****************************/
/*WRITE PORT */
/*****************************/
assign mailbox_write = mi_en & mi_we &
(mi_addr[31:20]==ID) &
(mi_addr[19:16]==GROUP) &
(mi_addr[RFAW+1:2]==`EMAILBOXLO);
assign mailbox_write = mi_en & mi_we & (mi_addr[RFAW+1:2]==`EMAILBOXLO);
/*****************************/
/*READ BACK DATA */
/*****************************/
assign mailbox_read = mi_en & ~mi_we & (mi_addr[19:16]==GROUP) & mailbox_not_empty;
assign mailbox_pop_fifo = mailbox_read & (mi_addr[RFAW+1:2]==`EMAILBOXHI); //fifo read
/*****************************/
assign mailbox_pop_fifo = mi_en &
~mi_we &
mailbox_not_empty &
mailbox_read & (mi_addr[RFAW+1:2]==`EMAILBOXHI); //fifo read
always @ (posedge sys_clk)
if(mailbox_read)

24
emmu/hdl/emmu.v
View File

@ -19,8 +19,8 @@ module emmu (/*AUTOARG*/
// Outputs
mi_dout, emesh_access_out, emesh_packet_out, emesh_packet_hi_out,
// Inputs
reset, sys_clk, mmu_en, mmu_bp, mi_en, mi_we, mi_addr, mi_din,
emesh_clk, emesh_access_in, emesh_packet_in, emesh_wait_in
reset, clk, mmu_en, mmu_bp, mi_en, mi_we, mi_addr, mi_din,
emesh_access_in, emesh_packet_in, emesh_wait_in
);
parameter DW = 32; //data width
parameter AW = 32; //address width
@ -34,7 +34,7 @@ module emmu (/*AUTOARG*/
/*DATAPATH CLOCk */
/*****************************/
input reset;
input sys_clk;
input clk;
/*****************************/
/*MMU LOOKUP DATA */
@ -54,8 +54,7 @@ module emmu (/*AUTOARG*/
/*****************************/
/*EMESH INPUTS */
/*****************************/
input emesh_clk;
/*****************************/
input emesh_access_in;
input [PW-1:0] emesh_packet_in;
input emesh_wait_in; //downstream pushback
@ -84,12 +83,11 @@ module emmu (/*AUTOARG*/
/*****************************/
/*MMU WRITE LOGIC */
/*****************************/
assign mi_match = mi_en & (mi_addr[19:16]==GROUP) & (mi_addr[15]);
//write controls
assign mi_wr_vec[5:0] = (mi_match & mi_we & ~mi_addr[2]) ? 6'b001111 :
(mi_match & mi_we & mi_addr[2]) ? 6'b110000 :
6'b000000 ;
assign mi_wr_vec[5:0] = (mi_en & mi_we & ~mi_addr[2]) ? 6'b001111 :
(mi_en & mi_we & mi_addr[2]) ? 6'b110000 :
6'b000000 ;
//write data
assign mi_wr_data[63:0] = {mi_din[31:0], mi_din[31:0]};
@ -105,11 +103,11 @@ module emmu (/*AUTOARG*/
// Outputs
.rd_data (emmu_lookup_data[MW-1:0]),
// Inputs
.wr_clk (sys_clk),
.wr_clk (clk),
.wr_en (mi_wr_vec[5:0]),
.wr_addr (mi_addr[14:3]),
.wr_data (mi_wr_data[MW-1:0]),
.rd_clk (emesh_clk),
.rd_clk (clk),
.rd_en (emesh_access_in),
.rd_addr (emmu_rd_addr[MAW-1:0])
);
@ -120,13 +118,13 @@ module emmu (/*AUTOARG*/
//pipeline to compensate for table lookup pipeline
//assumes one cycle memory access!
always @ (posedge emesh_clk or posedge reset)
always @ (posedge clk or posedge reset)
if(reset)
emesh_access_out <= 1'b0;
else if(~emesh_wait_in)
emesh_access_out <= emesh_access_in;
always @ (posedge emesh_clk)
always @ (posedge clk)
if(emesh_access_in & ~emesh_wait_in)
emesh_packet_reg[PW-1:0] <= emesh_packet_in[PW-1:0];

10
xilibs/hdl/OSERDESE2.v
View File

@ -21,14 +21,14 @@ module OSERDESE2 ( /*AUTOARG*/
output OFB; // output feedback port
output OQ; // data output port, D1 appears first
output SHIFTOUT1; // connect to shift in of master, example?
output SHIFTOUT2; // connect to shift in of master, example?
output SHIFTOUT1; // connect to shift in of master
output SHIFTOUT2; // connect to shift in of master
output TBYTEOUT; // byte group tristate output to IOB
output TFB; // 3-state control output for ODELAYE2
output TQ; // 3-state control output
input CLK; // high speed clock
input CLKDIV; // low speed clock (/8 for example)
input D1; //
input CLK; // high speed shift out clock
input CLKDIV; // low speed clock (/4 for example)
input D1; // first bit to shift out
input D2; //
input D3; //
input D4; //