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Prettifying format..starting to look decent
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Andreas Olofsson
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3c2b760a2f
@ -1,10 +1,10 @@
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###DESCRIPTION
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###DESCRIPTION
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The "elink" is a low-latency/high-speed interface for communicating between
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FPGAs and ASICs (such as Epiphany) that implement the elink protocol.
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The interface "should" achieve a peak throughput of 8 Gbit/s in FPGAs with
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24 available LVDS signal pairs.
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###ELINK INTERFACE I/O SIGNALS
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###ELINK INTERFACE I/O SIGNALS
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SIGNAL |DIR| DESCRIPTION
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---------------|---|--------------
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@ -30,12 +30,15 @@
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embox_not_empty| O | Mailbox not empty (connect to interrupt line)
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embox_full | O | Mailbox is full indicator
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###BUS INTERFACE
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###BUS INTERFACE
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The elink has a 64 bit data AXI master and 32-bit data AXI slave interface
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for connecting to a standard AXI network.
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###EMESH PACKET
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###EMESH PACKET FORMAT
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The elink was born out of a need to connect multiple Epiphany chips together
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and uses the eMesh 104 bit atomic packet structure for communication.
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The eMesh atomic packet consists of the following sub fields.
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PACKET SUBFIELD | DESCRIPTION
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----------------|----------------
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@ -47,14 +50,7 @@
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data[31:0] | Data for write transaction, return data for read response
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srcaddr[31:0] | Return address for read-request, upper data for 64 bit write
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###PACKET-FORMAT:
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The elink was born out of a need to connect multiple Epiphany chips together
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and uses the eMesh 104 bit atomic packet structure for communication.
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The eMesh atomic packet consists of the following sub fields.
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###FRAMING:
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###PACKET FRAMING
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The number of bytes to be received is determined by the data of the first
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“valid” byte (byte0) and the level of the FRAME signal. The data captured
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@ -68,7 +64,7 @@
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last byte of the previous transaction (byte8 or byte12) will be followed
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by byte5 of the new transaction.
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###PUSHBACK:
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###PUSHBACK
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The WAIT_RD and WAIT_WR signals are used to stall transmission when a receiver
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is unable to accept more transactions. The receiver will raise its WAIT output
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@ -89,13 +85,13 @@
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to indicate to the transmit logic that no more transactions can be received
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because the receiver buffer full.
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###ELINK MEMORY MAP
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###ELINK MEMORY MAP
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The elink has an parameter called 'ELINKID' that can be configured by
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the module instantiating the elink.
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REGISTER | ADDRESS | NOTES
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------------| --------|------
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REGISTER |ADDRESS |NOTES
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------------|---------|--------------------------------------------
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ESYSRESET | 0xF0000 | Soft reset
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ESYSTX | 0xF0004 | Elink tranmit config
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ESYSRX | 0xF0008 | Elink receiver config
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@ -110,13 +106,13 @@
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ESYSMMURX | 0xE0000 | Start of receiver MMU lookup table
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ESYSMMUTX | 0xD0000 | Start of transmit MMU lookup table (tbd)
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###ELINK CONFIGURATION REGISTERS
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###ELINK CONFIGURATION REGISTERS
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REGISTER | DESCRIPTION
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---------- | --------------
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---------- | --------------------------------------------------
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ESYSRESET | (elink reset register)
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[0] | 0: elink is active
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| 1: elink in reset
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---------- |-------------------
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---------- |---------------------------------------------------
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ESYSTX | (elink transmit configuration register)
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[0] | 0: TX disable
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| 1: TX enable
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@ -127,7 +123,7 @@
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| 1x: reserved
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[7:4] | Transmit control mode for eMesh
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[8] | AXI slave read timeout enable
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---------- |-------------------
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-----------|----------------------------------------------------
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ESYSRX | (elink receive configuration register)
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[0] | 0: elink RX disable
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| 1: elink RX enable
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@ -136,7 +132,7 @@
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[3:2] | 00: default elink packet receive mode
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| 01: stores input pin data in ESYSDATAIN register
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| 1x: reserved
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---------- |-------------------
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-----------|---------------------------------------------------
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ESYSCLk | (elink PLL configuration register)
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[0] | 0:cclk clock disabled
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| 1:cclk clock enabled
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@ -165,27 +161,27 @@
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| 0111: lclk=pllclk/128
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| 1xxx: RESERVED
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[15:12] | PLL frequency
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---------- |-------------------
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-----------|-------------------------------------------------
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ESYSCOREID | (coordinate ID for Epiphany)
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[5:0] | Column ID for connected Epiphany chip
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[11:6] | Row ID for connected Epiphany chip
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-------------------------------------------------------------
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ESYSLATFORM| (platform ID)
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-----------|-------------------------------------------------
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ESYSID | (platform and version ID)
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[7:0] | Platform model number
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[7:0] | Revision number
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-------------------------------------------------------------
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-----------|-------------------------------------------------
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ESYSDATAIN | (data on elink input pins)
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[7:0] | rx_data[7:0]
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[8] | tx_frame
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[9] | tx_wait_rd
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[10] | tx_wait_wr
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-------------------------------------------------------------
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-----------|-------------------------------------------------
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ESYSDATAOUT| (data on eLink output pins)
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[7:0] | tx_data[7:0]
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[8] | tx_frame
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[9] | rx_wait_rd
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[10] | rx_wait_wr
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-------------------------------------------------------------
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-----------|-------------------------------------------------
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ESYSDEBUG | (various debug signals from elink)
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[31] | embox_not_empty
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[30] | emesh_rx_rd_wait
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