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CHIP DESIGN REFERENCE FLOW
=======================================
This folder contains a recommended reference flow for implementing chips using OH!
## Flow Reference Guides
* [Synthesis](synthesis/README.md)
* [Place & Route](pnr/README.md)
* [Signoff](signoff/README.md)
## Other Resources
* [Glossary](../../docs/chip_glossary.md)
* [Constants](../../docs/chip_constants.md)
## Required Shell Variables
| SHELL VARIABLE | DESCRIPTION |
|------------------|----------------------------------------|
| $PROCESS_HOME | Path to foundry process |
| $OH_HOME | Path to OH repo home |
| $EDA_HOME | Path to private repo or "$OH_HOME/eda" |
## Required TCL Variables ("Designer API")
| TCL VARIABLE | DESCRIPTION |
|------------------|-------------------------------------|
| $OH_VENDOR | synopsys, cadence, etc |
| $OH_TOOL | dc, rc, etc |
| $OH_DESIGN | Name of top level module |
| $OH_FILES | Design files "-f commands" |
| $OH_LIBS | Synthesis libraries (ex: my_svtlib) |
| $OH_MACROS | Hard macros in design (ex: my_sram) |
| $OH_FLOORPLAN | Floorplanning file (tcl) |
| $OH_CONSTRAINTS | Timing constraints file |
## DIRECTORY STRUCTURE & NAMING METHODOLOGY
The structure is designed to simplify implementation scripts and maximize portability across:
* multiple foundries
* multiple process nodes
* multiple IP vendors
* multiple EDA vendors
| DIRECTORY NAME | DESCRIPTION |
|----------------------------|-----------------------------------------------|
| docs | open source documents and design guidelines |
| synthesis | open source synthesis scripts |
| pnr | open source place & route scripts |
| signoff | open source signoff scripts |
| eda | eda proprietary scripts |
| foundry ("foundry1") | tsmc, gf, tower, smic, umc, etc |
| process ("process1") | 28slp, 65g, etc |
| IP types("ip1") | pdk, stdlib, io, sram, serdes, etc |
| IP company name ("ipco1")| arm, synopsys, cadence, tsmc, etc |
| eda company name ("eda1")| synopsys, cadence, mentor, etc |
| proprietary | content under NDA not for distribution |
![alt tag](docs/directory_structure.png)
Description of contents inside each folder can be found in the local README.md file.
To visualize the directory structure, use the 'tree' utility.
## Example Design
```tcl
set OH_VENDOR "synopsys"
set OH_TOOl "dc"
set OH_DESIGN "ecore"
set OH_LIBS ""
set OH_MACROS ""
set OH_FILES "../../../hdl/$OH_DESIGN.v \
-y $env(OH_HOME)/emesh/hdl \
-y $env(OH_HOME)/common/hdl \
-y $env(EPIPHANY_HOME)/chip/hdl \
-y $env(EPIPHANY_HOME)/ecore/hdl \
-y $env(EPIPHANY_HOME)/emesh/hdl \
-y $env(EPIPHANY_HOME)/edma/hdl \
-y $env(EPIPHANY_HOME)/compute/hdl \
-y $env(EPIPHANY_HOME)/memory/hdl \
-y $env(EPIPHANY_HOME)/fpumm/hdl \
+incdir+$env(EPIPHANY_HOME)/emesh/hdl \
+incdir+$env(EPIPHANY_HOME)/ecore/hdl \
+incdir+$env(EPIPHANY_HOME)/edma/hdl"
set OH_CONSTRAINTS ${OH_DESIGN}.sdc
set OH_FLOORPLAN ${OH_DESIGN}_floorplan.tcl
```

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## CONTENTS
* EDA specific scripts
* Some companies don't allow sharing, in that case you probably want to have a private repo of scripts and include a symbolic link here to that repo.
* For example "ln -s /home/synopsys ."

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#CONTENT
* Various open source tools
* front end: yosys
* analog simulator: spice
* verilog simulator: iverilog, verilator
* pnr: n/a
* lvs: n/a
* drc: n/a
* schmatic entry: n/a
* polygon-push: n/a
* analog circuit generators: n/a
* logical equivalence : n/a
* dft compiler : n/a
* power compiler: n/a
* power grid analysis: n/a
* extraction tool: n/a
* signal integrity: n/a
* cell characterization: n/a
* transistor level STA: n/a
* signoff STA: n/a
* scan pattern generator: n/a
* memory compiler: n/a
* generic standard cell library: n/a
* generic io library: n/a

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## CONTENTS
* place holder for yosys synthesis tool...

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## CONTENT
* This directory contains a set of foundries (gf, tsmc, tower, etc)
* If you have a foundry with ANY open files, by all means put the files here.
* More likely, you will need to place a symbolic link here to something that
is off line. For example "ln -s /home/tsmc ."

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## CONTENTS
* "pdk": process specific technology files provided by foundry
* Process node specific hard IP like standard logic libraries, general purpose IO, SERDS, memory macros

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## CONTENTS
* Various IP vendors. ipco1, ipco2, etc

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## CONTENTS
- script for putting links to files in standard folders "standardizing"
- script for unpacking files (solving a delivery mess)
- directory "links"

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#!/bin/bash
#Script to collect view from all the directories
#DOCS
mkdir -p links/docs
cd links/docs
ln -s ../../proprietary/*/TSMCHOME/digital/Documentation/documents/* .
cd ../../
#VERILOG
mkdir -p links/verilog
cd links/verilog
ln -s ../../proprietary/*/TSMCHOME/digital/Front_End/verilog/* .
cd ../../
#SPICE
mkdir -p links/spice
cd links/spice
ln -s ../../proprietary/*/TSMCHOME/digital/Back_End/lpe_spice/* .
cd ../../
#GDS
mkdir -p links/gds
cd links/gds
ln -s ../../proprietary/*/GDS/TSMCHOME/digital/Back_End/gds/* .
cd ../../
#LEF
mkdir -p links/lef
cd links/lef
ln -s ../../proprietary/*/LEF/TSMCHOME/digital/Back_End/lef/* .
cd ../../

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## CONTENT
* directories of symbolic links. Filled by the create_links.sh script

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#!/bin/bash
#Script to unpack all views of all libs
#FOR ALL LIBS
cd proprietary
for dir in `ls -d * | grep -v tar.gz`
do
cd $dir
for f in *.tar.gz;
do
echo "Unpack $f in directory $dir";
tar -zxf $f;
done
#FOR ALL VIEWS (GLORIOUS HACK!)
for view in `ls -d Apollo* CDK GDS LEF | grep -v tar.gz`
do
cd $view
#FOR ALL FILES
for f in *.tar.gz;
do
echo "Unpack $f in directory $dir";
tar -zxf $f;
done
cd ../
done
cd ../
#REMOVE TAR BALLS TO SAVE SPACE
#find . -name "*.tar.gz" | xargs rm -f
done
cd ../

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#FOLDER CONTENTS
* Scripts needed to setup up IP in the various EDA tools to take design from design to Tcl files needed to set up the setup.tc

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## CONTENTS
* proprietary: files from vendor

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## CONTENTS
* Various IP vendors. ipco1, ipco2, etc

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## CONTENTS
* Links to eda specific files from proprietary pdk directory
* Technology setup scripts on a per tool basis (synthesis, P&R as examples)

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## CONTENTS
* Various IP vendors. ipco1, ipco2, etc

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## CONTENTS
* Various IP vendors. ipco1, ipco2, etc

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source $env(EDA_HOME)/$OH_VENDOR/$OH_TOOL/01_setup.tcl

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source $env(EDA_HOME)/$OH_VENDOR/$OH_TOOL/02_netlist.tcl

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source $env(EDA_HOME)/$OH_VENDOR/$OH_TOOL/03_constrain.tcl

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source $env(EDA_HOME)/$OH_VENDOR/$OH_TOOL/04_floorplan.tcl

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source $env(EDA_HOME)/$OH_VENDOR/$OH_TOOL/05_place.tcl

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source $env(EDA_HOME)/$OH_VENDOR/$OH_TOOL/06_clock.tcl

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source $env(EDA_HOME)/$OH_VENDOR/$OH_TOOL/07_route.tcl

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source $env(EDA_HOME)/$OH_VENDOR/$OH_TOOL/08_cleanup.tcl

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source $env(EDA_HOME)/$OH_VENDOR/$OH_TOOL/09_signoff.tcl

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OH!: Place and Route Flow
=====================================
This guide documents the OH! back end place and route flow that takes the design from netlist to GDS. The flow requires certain TCL and Shell variables to be setup, as defined [HERE](../README.md).
The synthesis flow scripts call EDA specific scipts as needed.
# SYNTHESIS FLOW
| FILE | NOTES |
|-------------------|--------------------------------------------------|
| 01_setup.tcl | Setup synthesis tool |
| 02_netlist.tcl | Read in netlist |
| 03_constrain.tcl | Constrain design |
| 04_floorplan.tcl | Read floorplan information |
| 05_place.tcl | Place design |
| 06_clock.tcl | Place and route clock nets |
| 07_route.tcl | Route all other nets |
| 08_cleanup.tcl | Cleanup (antenna, fill, etc) |
| 09_signoff.tcl | DRC/LVS signoff, reports, final GDS out |
## Example Setup File ("example.tcl")
```tcl
set OH_VENDOR "synopsys"
set OH_TOOl "icc"
set OH_DESIGN "ecore"
set OH_LIBS "svtlib"
set OH_MACROS "sram64x1024"
set OH_FILES "${OH_DESIGN}_syn.vg"
set OH_CONSTRAINTS "${OH_DESIGN}.sdc"
set OH_FLOORPLAN "${OH_DESIGN}_floorplan.tcl"
```
## Usage
```
>> cd
>> dc_shell -topographical_mode
dc_shell> source $env(OH_HOME)/chip/synthesis/example.tcl
```

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#################################
# PROCESS/LIBS DEFAULTS (SHELL)
#################################
if {[info exists env(OH_VENDOR)]} {
set OH_VENDOR "$env(OH_VENDOR)"; # synopsys, cadence, xilinx
}
if {[info exists env(OH_TARGET)]} {
set OH_TARGET "$env(OH_TARGET)"; # "lib1.db lib2.db lib3.db" or "xc7z020clg400-1"
}
if {[info exists env(OH_MACROS)]} {
set OH_MACROS "$env(OH_MACROS)"; # "macro1.lib macro2.lib"
}

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set LOCALPATH [file dirname [ info script ]]
######################################
# DESIGN SPECIFIC
######################################
set OH_DESIGN "ecore"
set OH_FILES "../../../hdl/$OH_DESIGN.v \
-y $env(OH_HOME)/emesh/hdl \
-y $env(OH_HOME)/common/hdl \
-y $env(EPIPHANY_HOME)/chip/hdl \
-y $env(EPIPHANY_HOME)/ecore/hdl \
-y $env(EPIPHANY_HOME)/emesh/hdl \
-y $env(EPIPHANY_HOME)/edma/hdl \
-y $env(EPIPHANY_HOME)/compute/hdl \
-y $env(EPIPHANY_HOME)/memory/hdl \
-y $env(EPIPHANY_HOME)/fpumm/hdl \
+incdir+$env(EPIPHANY_HOME)/emesh/hdl \
+incdir+$env(EPIPHANY_HOME)/ecore/hdl \
+incdir+$env(EPIPHANY_HOME)/edma/hdl"
set OH_CONSTRAINTS "${OH_DESIGN}.sdc"
set OH_FLOORPLAN "${OH_DESIGN}_floorplan.tcl"
set OH_LIBS "svtlib lvtlib"; # ip library names
set OH_MACROS "sram_macro"; # hard macro library names
set OH_VENDOR "synopsys"; # eda vendor name
set OH_TOOL "dc"; # name of eda vendor synthesis tool
######################################
# RUN SYNTHESIS
#####################################
source $LOCALPATH/run.tcl

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#SET PATH
set LOCALPATH [file dirname [ info script ]]
################################
# SETUP PROCESS
################################
source $env(PROCESS_HOME)/eda/$OH_VENDOR/setup_process.tcl
################################
# CHECK ENVIRONMENT VARIABLES
################################
set OH_VENDOR "synopsys"
set OH_MACROS ""
set OH_TARGET ""
if {[string match synopsys $OH_VENDOR]} {
set OH_TOOL "dc"
} elseif {[string match cadence $OH_VENDOR]} {
set OH_TOOL "rc"
} elseif {[string match xilinx $OH_VENDOR]} {
set OH_TOOL "vivado"
}
# Check that all variabls are defined
# If not defined exit!
puts $OH_DESIGN
puts $OH_TOP
puts $OH_CFG
puts $OH_LIBS
puts $OH_FLOORPLAN
puts $OH_VENDOR
puts $OH_TOOL
puts $OH_TARGET
puts $OH_MACROS
puts $OH_LAYER_MIN
puts $OH_LAYER_MAX
puts $OH_LIBPATH
puts $OH_TECHFILE
puts $OH_MAP
puts $OH_RCMODEL_MAX
puts $OH_RCMODEL_MIN
################################
# STEP1: SETUP TOOL
################################
source $LOCALPATH/01_setup.tcl
################################
# STEP2: READ NETLIST
################################
source $LOCALPATH/02_nelist.tcl
################################
# STEP3: CONSTRAIN DESIGN
################################
source $LOCALPATH/03_constrain.tcl
################################
# STEP4: READ FLOORPLAN
################################
source $LOCALPATH/04_floorplan.tcl
################################
# STEP5: PLACE DESIGN
################################
source $LOCALPATH/05_place.tcl
################################
# STEP6: CLOCKS
################################
source $LOCALPATH/06_clock.tcl
################################
# STEP7: ROUTE
################################
source $LOCALPATH/07_route.tcl
################################
# STEP8: CLEANUP
################################
source $LOCALPATH/08_cleanup.tcl
################################
# STEP8: SIGNOFF
################################
source $LOCALPATH/09_signoff.tcl
#exit

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## CONTENT
* All the scripts needed to finish the chip
* STA, IR DROP, FORMAL, SI, LVS, DRC, ...

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source $env(EDA_HOME)/$OH_VENDOR/$OH_TOOL/01_setup_tool.tcl

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source $env(EDA_HOME)/$OH_VENDOR/$OH_TOOL/02_read_design.tcl

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source $env(EDA_HOME)/$OH_VENDOR/$OH_TOOL/03_read_constraints.tcl

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source $env(EDA_HOME)/$OH_VENDOR/$OH_TOOL/05_floorplan.tcl

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source $env(EDA_HOME)/$OH_VENDOR/$OH_TOOL/07_compile.tcl

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source $env(EDA_HOME)/$OH_VENDOR/$OH_TOOL/08_dft.tcl

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source $env(EDA_HOME)/$OH_VENDOR/$OH_TOOL/09_optimize.tcl

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source $env(EDA_HOME)/$OH_VENDOR/$OH_TOOL/10_write_netlist.tcl

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OH!: Synthesis Flow
=====================================
This guide documents the OH! fron end synthesis flow that compiles Verilog HDL into a gate level netlist. The flow requires certain TCL and Shell variables to be setup, as defined [HERE](../README.md).
The synthesis flow scripts call EDA specific scipts as needed.
# SYNTHESIS FLOW
| FILE | NOTES |
|------------------|---------------------------------------------|
| 01_setup.tcl | Setup synthesis tool |
| 02_hdl.tcl | Read in design files |
| 03_constrain.tcl | Read in design constraints |
| 04_floorplan.tcl | Setup floorplan |
| 05_compile.tcl | Comile HDL to gates |
| 06_dft.tcl | Insert test features (scan) |
| 07_optimize.tcl | Seconday optimization step |
| 08_signoff.tcl | Write out netlists and reports |
## Example Setup File ("example.tcl")
```tcl
set OH_VENDOR "synopsys"
set OH_TOOl "dc"
set OH_DESIGN "ecore"
set OH_LIBS "svtlib"
set OH_MACROS "sram64x1024"
set OH_FILES "../../../hdl/$OH_DESIGN.v \
-y $env(OH_HOME)/emesh/hdl \
-y $env(OH_HOME)/common/hdl \
-y $env(EPIPHANY_HOME)/chip/hdl \
-y $env(EPIPHANY_HOME)/ecore/hdl \
-y $env(EPIPHANY_HOME)/emesh/hdl \
-y $env(EPIPHANY_HOME)/edma/hdl \
-y $env(EPIPHANY_HOME)/compute/hdl \
-y $env(EPIPHANY_HOME)/memory/hdl \
-y $env(EPIPHANY_HOME)/fpumm/hdl \
+incdir+$env(EPIPHANY_HOME)/emesh/hdl \
+incdir+$env(EPIPHANY_HOME)/ecore/hdl \
+incdir+$env(EPIPHANY_HOME)/edma/hdl"
set OH_CONSTRAINTS "${OH_DESIGN}.sdc"
set OH_FLOORPLAN "${OH_DESIGN}_floorplan.tcl"
```
## Usage
```
>> cd
>> dc_shell -topographical_mode
dc_shell> source $env(OH_HOME)/chip/synthesis/example.tcl
```

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#################################
# PROCESS/LIBS DEFAULTS (SHELL)
#################################
if {[info exists env(OH_VENDOR)]} {
set OH_VENDOR "$env(OH_VENDOR)"; # synopsys, cadence, xilinx
}
if {[info exists env(OH_TARGET)]} {
set OH_TARGET "$env(OH_TARGET)"; # "lib1.db lib2.db lib3.db" or "xc7z020clg400-1"
}
if {[info exists env(OH_MACROS)]} {
set OH_MACROS "$env(OH_MACROS)"; # "macro1.lib macro2.lib"
}

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set LOCALPATH [file dirname [ info script ]]
######################################
# DESIGN SPECIFIC
######################################
set OH_DESIGN "ecore"
set OH_FILES "../../../hdl/$OH_DESIGN.v \
-y $env(OH_HOME)/emesh/hdl \
-y $env(OH_HOME)/common/hdl \
-y $env(EPIPHANY_HOME)/chip/hdl \
-y $env(EPIPHANY_HOME)/ecore/hdl \
-y $env(EPIPHANY_HOME)/emesh/hdl \
-y $env(EPIPHANY_HOME)/edma/hdl \
-y $env(EPIPHANY_HOME)/compute/hdl \
-y $env(EPIPHANY_HOME)/memory/hdl \
-y $env(EPIPHANY_HOME)/fpumm/hdl \
+incdir+$env(EPIPHANY_HOME)/emesh/hdl \
+incdir+$env(EPIPHANY_HOME)/ecore/hdl \
+incdir+$env(EPIPHANY_HOME)/edma/hdl"
set OH_CONSTRAINTS "${OH_DESIGN}.sdc"
set OH_FLOORPLAN "${OH_DESIGN}_floorplan.tcl"
set OH_LIBS "svtlib lvtlib"; # ip library names
set OH_MACROS "sram_macro"; # hard macro library names
set OH_VENDOR "synopsys"; # eda vendor name
set OH_TOOL "dc"; # name of eda vendor synthesis tool
######################################
# RUN SYNTHESIS
#####################################
source $LOCALPATH/run.tcl

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#SET PATH
set LOCALPATH [file dirname [ info script ]]
################################
# SETUP PROCESS
################################
source $env(PROCESS_HOME)/eda/$OH_VENDOR/setup_process.tcl
################################
# CHECK ENVIRONMENT VARIABLES
################################
set OH_VENDOR "synopsys"
set OH_MACROS ""
set OH_TARGET ""
if {[string match synopsys $OH_VENDOR]} {
set OH_TOOL "dc"
} elseif {[string match cadence $OH_VENDOR]} {
set OH_TOOL "rc"
} elseif {[string match xilinx $OH_VENDOR]} {
set OH_TOOL "vivado"
}
# Check that all variabls are defined
# If not defined exit!
puts $OH_DESIGN
puts $OH_TOP
puts $OH_CFG
puts $OH_LIBS
puts $OH_FLOORPLAN
puts $OH_VENDOR
puts $OH_TOOL
puts $OH_TARGET
puts $OH_MACROS
puts $OH_LAYER_MIN
puts $OH_LAYER_MAX
puts $OH_LIBPATH
puts $OH_TECHFILE
puts $OH_MAP
puts $OH_RCMODEL_MAX
puts $OH_RCMODEL_MIN
################################
# STEP1: SETUP TOOL
################################
source $LOCALPATH/01_setup.tcl
################################
# STEP2: READ HDL
################################
source $LOCALPATH/02_hdl.tcl
################################
# STEP3: READ CONSTRAINTS
################################
source $LOCALPATH/03_constrain.tcl
################################
# STEP4: READ FLROOPLAN
################################
source $LOCALPATH/04_floorplan.tcl
################################
# STEP5: COMPILE
################################
source $LOCALPATH/05_compile.tcl
################################
# STEP6: DFT
################################
source $LOCALPATH/06_dft.tcl
################################
# STEP7: OPTIMIZE
################################
source $LOCALPATH/07_optimize.tcl
################################
# STEP8: WRITE NETLIST/REPORTS
################################
source $LOCALPATH/08_signoff.tcl
#exit