From 3c6c41ff83c76c2413690c45e3ccc02a3d86b9cd Mon Sep 17 00:00:00 2001 From: aolofsson Date: Mon, 26 Apr 2021 09:39:36 -0400 Subject: [PATCH] Removing depracated eda directory --- eda/README.md | 101 ------------------ eda/docs/directory_structure.png | Bin 28776 -> 0 bytes eda/eda/README.md | 4 - eda/eda/open/README.md | 25 ----- eda/eda/open/yosys/README.md | 2 - eda/foundry/README.md | 5 - eda/foundry/foundry1/process1/README.md | 4 - eda/foundry/foundry1/process1/io/README.md | 2 - .../foundry1/process1/io/ipco1/README.md | 4 - .../process1/io/ipco1/create_links.sh | 35 ------ .../process1/io/ipco1/links/README.md | 2 - .../foundry1/process1/io/ipco1/unpack.sh | 31 ------ .../foundry1/process1/io/setup/eda1/README.md | 5 - eda/foundry/foundry1/process1/pdk/README.md | 3 - .../foundry1/process1/serdes/README.md | 2 - .../foundry1/process1/setup/eda1/README.md | 3 - eda/foundry/foundry1/process1/sram/README.md | 2 - .../foundry1/process1/stdlib/README.md | 2 - eda/pnr/01_setup.tcl | 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eda/synthesis/example.tcl delete mode 100644 eda/synthesis/run.tcl diff --git a/eda/README.md b/eda/README.md deleted file mode 100644 index 1678dd8..0000000 --- a/eda/README.md +++ /dev/null @@ -1,101 +0,0 @@ -CHIP DESIGN REFERENCE FLOW -======================================= - -This folder contains a recommended reference flow for implementing chips using OH! - -## Flow Reference Guides - -* [Synthesis](synthesis/README.md) -* [Place & Route](pnr/README.md) -* [Signoff](signoff/README.md) - -## Other Resources -* [Glossary](../../docs/chip_glossary.md) -* [Constants](../../docs/chip_constants.md) - -## Required Shell Variables - -| SHELL VARIABLE | DESCRIPTION | -|------------------|----------------------------------------| -| $PROCESS_HOME | Path to foundry process | -| $OH_HOME | Path to OH repo home | -| $EDA_HOME | Path to private repo or "$OH_HOME/eda" | - -## Required TCL Variables ("Designer API") - -| TCL VARIABLE | DESCRIPTION | -|------------------|-------------------------------------| -| $OH_VENDOR | synopsys, cadence, etc | -| $OH_TOOL | dc, rc, etc | -| $OH_DESIGN | Name of top level module | -| $OH_FILES | Design files "-f commands" | -| $OH_LIBS | Synthesis libraries (ex: my_svtlib) | -| $OH_MACROS | Hard macros in design (ex: my_sram) | -| $OH_FLOORPLAN | Floorplanning file (tcl) | -| $OH_CONSTRAINTS | Timing constraints file | - - -## DIRECTORY STRUCTURE & NAMING METHODOLOGY - -The structure is designed to simplify implementation scripts and maximize portability across: -* multiple foundries -* multiple process nodes -* multiple IP vendors -* multiple EDA vendors - -| DIRECTORY NAME | DESCRIPTION | -|----------------------------|-----------------------------------------------| -| docs | open source documents and design guidelines | -| synthesis | open source synthesis scripts | -| pnr | open source place & route scripts | -| signoff | open source signoff scripts | -| eda | eda proprietary scripts | -| foundry ("foundry1") | tsmc, gf, tower, smic, umc, etc | -| process ("process1") | 28slp, 65g, etc | -| IP types("ip1") | pdk, stdlib, io, sram, serdes, etc | -| IP company name ("ipco1")| arm, synopsys, cadence, tsmc, etc | -| eda company name ("eda1")| synopsys, cadence, mentor, etc | -| proprietary | content under NDA not for distribution | - -![alt tag](docs/directory_structure.png) - -Description of contents inside each folder can be found in the local README.md file. - -To visualize the directory structure, use the 'tree' utility. - - -## Example Design - -```tcl -set OH_VENDOR "synopsys" - -set OH_TOOl "dc" - -set OH_DESIGN "ecore" - -set OH_LIBS "" - -set OH_MACROS "" - -set OH_FILES "../../../hdl/$OH_DESIGN.v \ - -y $env(OH_HOME)/emesh/hdl \ - -y $env(OH_HOME)/common/hdl \ - -y $env(EPIPHANY_HOME)/chip/hdl \ - -y $env(EPIPHANY_HOME)/ecore/hdl \ - -y $env(EPIPHANY_HOME)/emesh/hdl \ - -y $env(EPIPHANY_HOME)/edma/hdl \ - -y $env(EPIPHANY_HOME)/compute/hdl \ - -y $env(EPIPHANY_HOME)/memory/hdl \ - -y $env(EPIPHANY_HOME)/fpumm/hdl \ - +incdir+$env(EPIPHANY_HOME)/emesh/hdl \ - +incdir+$env(EPIPHANY_HOME)/ecore/hdl \ - +incdir+$env(EPIPHANY_HOME)/edma/hdl" - -set OH_CONSTRAINTS ${OH_DESIGN}.sdc - -set OH_FLOORPLAN ${OH_DESIGN}_floorplan.tcl - -``` - - - diff --git a/eda/docs/directory_structure.png b/eda/docs/directory_structure.png deleted file mode 100644 index 8e89de6da3b958c94f0a96057bb8515a6ae7162a..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 28776 zcmd421ymgCwk=$ZOK^7!5Fj`Nm*5aIxDz0_yVE2{2u>il2X}W#(BSUw?yj%d`<#8w zx$nIDzxUtw#<+vgbk{eky1uIZYOT5EoGVySUJ?a~5D5SP6lp23_W%Hj2LLE`1SrTz zg++V?^!%6Jocj$jf@mkD=?DPGSkEsIkeG}Q8H9I|mJ^3xhC)Yyq2;+! zTLA!aKw9jrireh|f~Stk$4B_%p@h2^?EQA8bv?T1*v$Fnbnbmx17v#Nnp8|CZE|$0 zTq-Ae9b6gu7{>;*svWF3i(fO&v9U&RpufdfMRkY@fokt(>EGz*Zxu2?#|9l`E?pH) z^~JMq@wX>93ZC%~C7;2P`=g5>Q2hO$R0ItSU~e}pdNhCHdqOBVnQ-bM;TeEFnuP!$ z@Jn8OJ;#vtZVHT0{c4tmF5+Pj$zy@`9d8embvXS~BJ~pSuP;KVXJqZd&njg=q!5S( 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link here to that repo. -* For example "ln -s /home/synopsys ." \ No newline at end of file diff --git a/eda/eda/open/README.md b/eda/eda/open/README.md deleted file mode 100644 index 22a5db8..0000000 --- a/eda/eda/open/README.md +++ /dev/null @@ -1,25 +0,0 @@ -#CONTENT -* Various open source tools -* front end: yosys -* analog simulator: spice -* verilog simulator: iverilog, verilator -* pnr: n/a -* lvs: n/a -* drc: n/a -* schmatic entry: n/a -* polygon-push: n/a -* analog circuit generators: n/a -* logical equivalence : n/a -* dft compiler : n/a -* power compiler: n/a -* power grid analysis: n/a -* extraction tool: n/a -* signal integrity: n/a -* cell characterization: n/a -* transistor level STA: n/a -* signoff STA: n/a -* scan pattern generator: n/a -* memory compiler: n/a -* generic standard cell library: n/a -* generic io library: n/a - diff --git a/eda/eda/open/yosys/README.md b/eda/eda/open/yosys/README.md deleted file mode 100644 index a85c49b..0000000 --- a/eda/eda/open/yosys/README.md +++ /dev/null @@ -1,2 +0,0 @@ -## CONTENTS -* place holder for yosys synthesis tool... \ No newline at end of file diff --git a/eda/foundry/README.md b/eda/foundry/README.md deleted file mode 100644 index 99e206e..0000000 --- a/eda/foundry/README.md +++ /dev/null @@ -1,5 +0,0 @@ -## CONTENT -* This directory contains a set of foundries (gf, tsmc, tower, etc) -* If you have a foundry with ANY open files, by all means put the files here. -* More likely, you will need to place a symbolic link here to something that - is off line. For example "ln -s /home/tsmc ." \ No newline at end of file diff --git a/eda/foundry/foundry1/process1/README.md b/eda/foundry/foundry1/process1/README.md deleted file mode 100644 index 843e822..0000000 --- a/eda/foundry/foundry1/process1/README.md +++ /dev/null @@ -1,4 +0,0 @@ -## CONTENTS - -* "pdk": process specific technology files provided by foundry -* Process node specific hard IP like standard logic libraries, general purpose IO, SERDS, memory macros diff --git a/eda/foundry/foundry1/process1/io/README.md b/eda/foundry/foundry1/process1/io/README.md deleted file mode 100644 index 39c2a64..0000000 --- a/eda/foundry/foundry1/process1/io/README.md +++ /dev/null @@ -1,2 +0,0 @@ -## CONTENTS -* Various IP vendors. ipco1, ipco2, etc \ No newline at end of file diff --git a/eda/foundry/foundry1/process1/io/ipco1/README.md b/eda/foundry/foundry1/process1/io/ipco1/README.md deleted file mode 100644 index fad0775..0000000 --- a/eda/foundry/foundry1/process1/io/ipco1/README.md +++ /dev/null @@ -1,4 +0,0 @@ -## CONTENTS -- script for putting links to files in standard folders "standardizing" -- script for unpacking files (solving a delivery mess) -- directory "links" \ No newline at end of file diff --git a/eda/foundry/foundry1/process1/io/ipco1/create_links.sh b/eda/foundry/foundry1/process1/io/ipco1/create_links.sh deleted file mode 100755 index f5ad891..0000000 --- a/eda/foundry/foundry1/process1/io/ipco1/create_links.sh +++ /dev/null @@ -1,35 +0,0 @@ -#!/bin/bash - -#Script to collect view from all the directories - -#DOCS -mkdir -p links/docs -cd links/docs -ln -s ../../proprietary/*/TSMCHOME/digital/Documentation/documents/* . -cd ../../ - -#VERILOG -mkdir -p links/verilog -cd links/verilog -ln -s ../../proprietary/*/TSMCHOME/digital/Front_End/verilog/* . -cd ../../ - -#SPICE -mkdir -p links/spice -cd links/spice -ln -s ../../proprietary/*/TSMCHOME/digital/Back_End/lpe_spice/* . -cd ../../ - -#GDS -mkdir -p links/gds -cd links/gds -ln -s ../../proprietary/*/GDS/TSMCHOME/digital/Back_End/gds/* . -cd ../../ - -#LEF -mkdir -p links/lef -cd links/lef -ln -s ../../proprietary/*/LEF/TSMCHOME/digital/Back_End/lef/* . -cd ../../ - - diff --git a/eda/foundry/foundry1/process1/io/ipco1/links/README.md b/eda/foundry/foundry1/process1/io/ipco1/links/README.md deleted file mode 100644 index 9b11e9c..0000000 --- a/eda/foundry/foundry1/process1/io/ipco1/links/README.md +++ /dev/null @@ -1,2 +0,0 @@ -## CONTENT -* directories of symbolic links. Filled by the create_links.sh script diff --git a/eda/foundry/foundry1/process1/io/ipco1/unpack.sh b/eda/foundry/foundry1/process1/io/ipco1/unpack.sh deleted file mode 100755 index 93535bd..0000000 --- a/eda/foundry/foundry1/process1/io/ipco1/unpack.sh +++ /dev/null @@ -1,31 +0,0 @@ -#!/bin/bash - -#Script to unpack all views of all libs - -#FOR ALL LIBS -cd proprietary -for dir in `ls -d * | grep -v tar.gz` -do - cd $dir - for f in *.tar.gz; - do - echo "Unpack $f in directory $dir"; - tar -zxf $f; - done - #FOR ALL VIEWS (GLORIOUS HACK!) - for view in `ls -d Apollo* CDK GDS LEF | grep -v tar.gz` - do - cd $view - #FOR ALL FILES - for f in *.tar.gz; - do - echo "Unpack $f in directory $dir"; - tar -zxf $f; - done - cd ../ - done - cd ../ - #REMOVE TAR BALLS TO SAVE SPACE - #find . -name "*.tar.gz" | xargs rm -f -done -cd ../ diff --git a/eda/foundry/foundry1/process1/io/setup/eda1/README.md b/eda/foundry/foundry1/process1/io/setup/eda1/README.md deleted file mode 100644 index 7d6d343..0000000 --- a/eda/foundry/foundry1/process1/io/setup/eda1/README.md +++ /dev/null @@ -1,5 +0,0 @@ -#FOLDER CONTENTS -* Scripts needed to setup up IP in the various EDA tools to take design from design to Tcl files needed to set up the setup.tc - - - \ No newline at end of file diff --git a/eda/foundry/foundry1/process1/pdk/README.md b/eda/foundry/foundry1/process1/pdk/README.md deleted file mode 100644 index 3df5928..0000000 --- a/eda/foundry/foundry1/process1/pdk/README.md +++ /dev/null @@ -1,3 +0,0 @@ -## CONTENTS - -* proprietary: files from vendor diff --git a/eda/foundry/foundry1/process1/serdes/README.md b/eda/foundry/foundry1/process1/serdes/README.md deleted file mode 100644 index 39c2a64..0000000 --- a/eda/foundry/foundry1/process1/serdes/README.md +++ /dev/null @@ -1,2 +0,0 @@ -## CONTENTS -* Various IP vendors. ipco1, ipco2, etc \ No newline at end of file diff --git a/eda/foundry/foundry1/process1/setup/eda1/README.md b/eda/foundry/foundry1/process1/setup/eda1/README.md deleted file mode 100644 index a77a725..0000000 --- a/eda/foundry/foundry1/process1/setup/eda1/README.md +++ /dev/null @@ -1,3 +0,0 @@ -## CONTENTS -* Links to eda specific files from proprietary pdk directory -* Technology setup scripts on a per tool basis (synthesis, P&R as examples) diff --git a/eda/foundry/foundry1/process1/sram/README.md b/eda/foundry/foundry1/process1/sram/README.md deleted file mode 100644 index 39c2a64..0000000 --- a/eda/foundry/foundry1/process1/sram/README.md +++ /dev/null @@ -1,2 +0,0 @@ -## CONTENTS -* Various IP vendors. ipco1, ipco2, etc \ No newline at end of file diff --git a/eda/foundry/foundry1/process1/stdlib/README.md b/eda/foundry/foundry1/process1/stdlib/README.md deleted file mode 100644 index 39c2a64..0000000 --- a/eda/foundry/foundry1/process1/stdlib/README.md +++ /dev/null @@ -1,2 +0,0 @@ -## CONTENTS -* Various IP vendors. ipco1, ipco2, etc \ No newline at end of file diff --git a/eda/pnr/01_setup.tcl b/eda/pnr/01_setup.tcl deleted file mode 100644 index aeac8d4..0000000 --- a/eda/pnr/01_setup.tcl +++ /dev/null @@ -1,2 +0,0 @@ -source $env(EDA_HOME)/$OH_VENDOR/$OH_TOOL/01_setup.tcl - diff --git a/eda/pnr/02_netlist.tcl b/eda/pnr/02_netlist.tcl deleted file mode 100644 index 2d61afb..0000000 --- a/eda/pnr/02_netlist.tcl +++ /dev/null @@ -1,2 +0,0 @@ -source $env(EDA_HOME)/$OH_VENDOR/$OH_TOOL/02_netlist.tcl - diff --git a/eda/pnr/03_constrain.tcl b/eda/pnr/03_constrain.tcl deleted file mode 100644 index 1afa8e4..0000000 --- a/eda/pnr/03_constrain.tcl +++ /dev/null @@ -1,2 +0,0 @@ -source $env(EDA_HOME)/$OH_VENDOR/$OH_TOOL/03_constrain.tcl - diff --git a/eda/pnr/04_floorplan.tcl b/eda/pnr/04_floorplan.tcl deleted file mode 100644 index b815763..0000000 --- a/eda/pnr/04_floorplan.tcl +++ /dev/null @@ -1 +0,0 @@ -source $env(EDA_HOME)/$OH_VENDOR/$OH_TOOL/04_floorplan.tcl diff --git a/eda/pnr/05_place.tcl b/eda/pnr/05_place.tcl deleted file mode 100644 index f69e23c..0000000 --- a/eda/pnr/05_place.tcl +++ /dev/null @@ -1 +0,0 @@ -source $env(EDA_HOME)/$OH_VENDOR/$OH_TOOL/05_place.tcl diff --git a/eda/pnr/06_clock.tcl b/eda/pnr/06_clock.tcl deleted file mode 100644 index 8c4e15e..0000000 --- a/eda/pnr/06_clock.tcl +++ /dev/null @@ -1,2 +0,0 @@ -source $env(EDA_HOME)/$OH_VENDOR/$OH_TOOL/06_clock.tcl - diff --git a/eda/pnr/07_route.tcl b/eda/pnr/07_route.tcl deleted file mode 100644 index 581adcd..0000000 --- a/eda/pnr/07_route.tcl +++ /dev/null @@ -1,2 +0,0 @@ -source $env(EDA_HOME)/$OH_VENDOR/$OH_TOOL/07_route.tcl - diff --git a/eda/pnr/08_cleanup.tcl b/eda/pnr/08_cleanup.tcl deleted file mode 100644 index 368122c..0000000 --- a/eda/pnr/08_cleanup.tcl +++ /dev/null @@ -1,2 +0,0 @@ -source $env(EDA_HOME)/$OH_VENDOR/$OH_TOOL/08_cleanup.tcl - diff --git a/eda/pnr/09_signoff.tcl b/eda/pnr/09_signoff.tcl deleted file mode 100644 index 861d7c9..0000000 --- a/eda/pnr/09_signoff.tcl +++ /dev/null @@ -1,2 +0,0 @@ -source $env(EDA_HOME)/$OH_VENDOR/$OH_TOOL/09_signoff.tcl - diff --git a/eda/pnr/README.md b/eda/pnr/README.md deleted file mode 100644 index 04c3a9c..0000000 --- a/eda/pnr/README.md +++ /dev/null @@ -1,49 +0,0 @@ -OH!: Place and Route Flow -===================================== - -This guide documents the OH! back end place and route flow that takes the design from netlist to GDS. The flow requires certain TCL and Shell variables to be setup, as defined [HERE](../README.md). - -The synthesis flow scripts call EDA specific scipts as needed. - -# SYNTHESIS FLOW - -| FILE | NOTES | -|-------------------|--------------------------------------------------| -| 01_setup.tcl | Setup synthesis tool | -| 02_netlist.tcl | Read in netlist | -| 03_constrain.tcl | Constrain design | -| 04_floorplan.tcl | Read floorplan information | -| 05_place.tcl | Place design | -| 06_clock.tcl | Place and route clock nets | -| 07_route.tcl | Route all other nets | -| 08_cleanup.tcl | Cleanup (antenna, fill, etc) | -| 09_signoff.tcl | DRC/LVS signoff, reports, final GDS out | - -## Example Setup File ("example.tcl") - -```tcl -set OH_VENDOR "synopsys" - -set OH_TOOl "icc" - -set OH_DESIGN "ecore" - -set OH_LIBS "svtlib" - -set OH_MACROS "sram64x1024" - -set OH_FILES "${OH_DESIGN}_syn.vg" - -set OH_CONSTRAINTS "${OH_DESIGN}.sdc" - -set OH_FLOORPLAN "${OH_DESIGN}_floorplan.tcl" - -``` - -## Usage - -``` ->> cd ->> dc_shell -topographical_mode -dc_shell> source $env(OH_HOME)/chip/synthesis/example.tcl -``` diff --git a/eda/pnr/defaults.tcl b/eda/pnr/defaults.tcl deleted file mode 100644 index 9307cbc..0000000 --- a/eda/pnr/defaults.tcl +++ /dev/null @@ -1,15 +0,0 @@ -################################# -# PROCESS/LIBS DEFAULTS (SHELL) -################################# - -if {[info exists env(OH_VENDOR)]} { - set OH_VENDOR "$env(OH_VENDOR)"; # synopsys, cadence, xilinx -} - -if {[info exists env(OH_TARGET)]} { - set OH_TARGET "$env(OH_TARGET)"; # "lib1.db lib2.db lib3.db" or "xc7z020clg400-1" -} - -if {[info exists env(OH_MACROS)]} { - set OH_MACROS "$env(OH_MACROS)"; # "macro1.lib macro2.lib" -} diff --git a/eda/pnr/example.tcl b/eda/pnr/example.tcl deleted file mode 100644 index b4948ae..0000000 --- a/eda/pnr/example.tcl +++ /dev/null @@ -1,39 +0,0 @@ -set LOCALPATH [file dirname [ info script ]] - -###################################### -# DESIGN SPECIFIC -###################################### - -set OH_DESIGN "ecore" - -set OH_FILES "../../../hdl/$OH_DESIGN.v \ - -y $env(OH_HOME)/emesh/hdl \ - -y $env(OH_HOME)/common/hdl \ - -y $env(EPIPHANY_HOME)/chip/hdl \ - -y $env(EPIPHANY_HOME)/ecore/hdl \ - -y $env(EPIPHANY_HOME)/emesh/hdl \ - -y $env(EPIPHANY_HOME)/edma/hdl \ - -y $env(EPIPHANY_HOME)/compute/hdl \ - -y $env(EPIPHANY_HOME)/memory/hdl \ - -y $env(EPIPHANY_HOME)/fpumm/hdl \ - +incdir+$env(EPIPHANY_HOME)/emesh/hdl \ - +incdir+$env(EPIPHANY_HOME)/ecore/hdl \ - +incdir+$env(EPIPHANY_HOME)/edma/hdl" - -set OH_CONSTRAINTS "${OH_DESIGN}.sdc" - -set OH_FLOORPLAN "${OH_DESIGN}_floorplan.tcl" - -set OH_LIBS "svtlib lvtlib"; # ip library names - -set OH_MACROS "sram_macro"; # hard macro library names - -set OH_VENDOR "synopsys"; # eda vendor name - -set OH_TOOL "dc"; # name of eda vendor synthesis tool - -###################################### -# RUN SYNTHESIS -##################################### -source $LOCALPATH/run.tcl - diff --git a/eda/pnr/run.tcl b/eda/pnr/run.tcl deleted file mode 100644 index 6a0bdf3..0000000 --- a/eda/pnr/run.tcl +++ /dev/null @@ -1,100 +0,0 @@ -#SET PATH -set LOCALPATH [file dirname [ info script ]] - -################################ -# SETUP PROCESS -################################ - -source $env(PROCESS_HOME)/eda/$OH_VENDOR/setup_process.tcl - -################################ -# CHECK ENVIRONMENT VARIABLES -################################ - -set OH_VENDOR "synopsys" -set OH_MACROS "" -set OH_TARGET "" - -if {[string match synopsys $OH_VENDOR]} { - set OH_TOOL "dc" -} elseif {[string match cadence $OH_VENDOR]} { - set OH_TOOL "rc" -} elseif {[string match xilinx $OH_VENDOR]} { - set OH_TOOL "vivado" -} - -# Check that all variabls are defined -# If not defined exit! -puts $OH_DESIGN -puts $OH_TOP -puts $OH_CFG -puts $OH_LIBS -puts $OH_FLOORPLAN -puts $OH_VENDOR -puts $OH_TOOL -puts $OH_TARGET -puts $OH_MACROS -puts $OH_LAYER_MIN -puts $OH_LAYER_MAX -puts $OH_LIBPATH -puts $OH_TECHFILE -puts $OH_MAP -puts $OH_RCMODEL_MAX -puts $OH_RCMODEL_MIN - -################################ -# STEP1: SETUP TOOL -################################ - -source $LOCALPATH/01_setup.tcl - -################################ -# STEP2: READ NETLIST -################################ - -source $LOCALPATH/02_nelist.tcl - -################################ -# STEP3: CONSTRAIN DESIGN -################################ - -source $LOCALPATH/03_constrain.tcl - -################################ -# STEP4: READ FLOORPLAN -################################ - -source $LOCALPATH/04_floorplan.tcl - -################################ -# STEP5: PLACE DESIGN -################################ - -source $LOCALPATH/05_place.tcl - -################################ -# STEP6: CLOCKS -################################ - -source $LOCALPATH/06_clock.tcl - -################################ -# STEP7: ROUTE -################################ - -source $LOCALPATH/07_route.tcl - -################################ -# STEP8: CLEANUP -################################ - -source $LOCALPATH/08_cleanup.tcl - -################################ -# STEP8: SIGNOFF -################################ - -source $LOCALPATH/09_signoff.tcl - -#exit - diff --git a/eda/signoff/README.md b/eda/signoff/README.md deleted file mode 100644 index c4f7b39..0000000 --- a/eda/signoff/README.md +++ /dev/null @@ -1,3 +0,0 @@ -## CONTENT -* All the scripts needed to finish the chip -* STA, IR DROP, FORMAL, SI, LVS, DRC, ... \ No newline at end of file diff --git a/eda/synthesis/01_setup.tcl b/eda/synthesis/01_setup.tcl deleted file mode 100644 index e23c77a..0000000 --- a/eda/synthesis/01_setup.tcl +++ /dev/null @@ -1,2 +0,0 @@ -source $env(EDA_HOME)/$OH_VENDOR/$OH_TOOL/01_setup_tool.tcl - diff --git a/eda/synthesis/02_hdl.tcl b/eda/synthesis/02_hdl.tcl deleted file mode 100644 index 406adfe..0000000 --- a/eda/synthesis/02_hdl.tcl +++ /dev/null @@ -1,2 +0,0 @@ -source $env(EDA_HOME)/$OH_VENDOR/$OH_TOOL/02_read_design.tcl - diff --git a/eda/synthesis/03_constrain.tcl b/eda/synthesis/03_constrain.tcl deleted file mode 100644 index 6303f80..0000000 --- a/eda/synthesis/03_constrain.tcl +++ /dev/null @@ -1,2 +0,0 @@ -source $env(EDA_HOME)/$OH_VENDOR/$OH_TOOL/03_read_constraints.tcl - diff --git a/eda/synthesis/04_floorplan.tcl b/eda/synthesis/04_floorplan.tcl deleted file mode 100644 index bac36b1..0000000 --- a/eda/synthesis/04_floorplan.tcl +++ /dev/null @@ -1 +0,0 @@ -source $env(EDA_HOME)/$OH_VENDOR/$OH_TOOL/05_floorplan.tcl diff --git a/eda/synthesis/05_compile.tcl b/eda/synthesis/05_compile.tcl deleted file mode 100644 index 66a9842..0000000 --- a/eda/synthesis/05_compile.tcl +++ /dev/null @@ -1 +0,0 @@ -source $env(EDA_HOME)/$OH_VENDOR/$OH_TOOL/07_compile.tcl diff --git a/eda/synthesis/06_dft.tcl b/eda/synthesis/06_dft.tcl deleted file mode 100644 index 9be949c..0000000 --- a/eda/synthesis/06_dft.tcl +++ /dev/null @@ -1,2 +0,0 @@ -source $env(EDA_HOME)/$OH_VENDOR/$OH_TOOL/08_dft.tcl - diff --git a/eda/synthesis/07_optimize.tcl b/eda/synthesis/07_optimize.tcl deleted file mode 100644 index eeaf165..0000000 --- a/eda/synthesis/07_optimize.tcl +++ /dev/null @@ -1,2 +0,0 @@ -source $env(EDA_HOME)/$OH_VENDOR/$OH_TOOL/09_optimize.tcl - diff --git a/eda/synthesis/08_signoff.tcl b/eda/synthesis/08_signoff.tcl deleted file mode 100644 index fb68f46..0000000 --- a/eda/synthesis/08_signoff.tcl +++ /dev/null @@ -1,2 +0,0 @@ -source $env(EDA_HOME)/$OH_VENDOR/$OH_TOOL/10_write_netlist.tcl - diff --git a/eda/synthesis/README.md b/eda/synthesis/README.md deleted file mode 100644 index 87c0102..0000000 --- a/eda/synthesis/README.md +++ /dev/null @@ -1,60 +0,0 @@ -OH!: Synthesis Flow -===================================== - -This guide documents the OH! fron end synthesis flow that compiles Verilog HDL into a gate level netlist. The flow requires certain TCL and Shell variables to be setup, as defined [HERE](../README.md). - -The synthesis flow scripts call EDA specific scipts as needed. - -# SYNTHESIS FLOW - -| FILE | NOTES | -|------------------|---------------------------------------------| -| 01_setup.tcl | Setup synthesis tool | -| 02_hdl.tcl | Read in design files | -| 03_constrain.tcl | Read in design constraints | -| 04_floorplan.tcl | Setup floorplan | -| 05_compile.tcl | Comile HDL to gates | -| 06_dft.tcl | Insert test features (scan) | -| 07_optimize.tcl | Seconday optimization step | -| 08_signoff.tcl | Write out netlists and reports | - -## Example Setup File ("example.tcl") - -```tcl -set OH_VENDOR "synopsys" - -set OH_TOOl "dc" - -set OH_DESIGN "ecore" - -set OH_LIBS "svtlib" - -set OH_MACROS "sram64x1024" - -set OH_FILES "../../../hdl/$OH_DESIGN.v \ - -y $env(OH_HOME)/emesh/hdl \ - -y $env(OH_HOME)/common/hdl \ - -y $env(EPIPHANY_HOME)/chip/hdl \ - -y $env(EPIPHANY_HOME)/ecore/hdl \ - -y $env(EPIPHANY_HOME)/emesh/hdl \ - -y $env(EPIPHANY_HOME)/edma/hdl \ - -y $env(EPIPHANY_HOME)/compute/hdl \ - -y $env(EPIPHANY_HOME)/memory/hdl \ - -y $env(EPIPHANY_HOME)/fpumm/hdl \ - +incdir+$env(EPIPHANY_HOME)/emesh/hdl \ - +incdir+$env(EPIPHANY_HOME)/ecore/hdl \ - +incdir+$env(EPIPHANY_HOME)/edma/hdl" - -set OH_CONSTRAINTS "${OH_DESIGN}.sdc" - -set OH_FLOORPLAN "${OH_DESIGN}_floorplan.tcl" - -``` - -## Usage - -``` ->> cd ->> dc_shell -topographical_mode -dc_shell> source $env(OH_HOME)/chip/synthesis/example.tcl -``` diff --git a/eda/synthesis/defaults.tcl b/eda/synthesis/defaults.tcl deleted file mode 100644 index 9307cbc..0000000 --- a/eda/synthesis/defaults.tcl +++ /dev/null @@ -1,15 +0,0 @@ -################################# -# PROCESS/LIBS DEFAULTS (SHELL) -################################# - -if {[info exists env(OH_VENDOR)]} { - set OH_VENDOR "$env(OH_VENDOR)"; # synopsys, cadence, xilinx -} - -if {[info exists env(OH_TARGET)]} { - set OH_TARGET "$env(OH_TARGET)"; # "lib1.db lib2.db lib3.db" or "xc7z020clg400-1" -} - -if {[info exists env(OH_MACROS)]} { - set OH_MACROS "$env(OH_MACROS)"; # "macro1.lib macro2.lib" -} diff --git a/eda/synthesis/example.tcl b/eda/synthesis/example.tcl deleted file mode 100644 index b4948ae..0000000 --- a/eda/synthesis/example.tcl +++ /dev/null @@ -1,39 +0,0 @@ -set LOCALPATH [file dirname [ info script ]] - -###################################### -# DESIGN SPECIFIC -###################################### - -set OH_DESIGN "ecore" - -set OH_FILES "../../../hdl/$OH_DESIGN.v \ - -y $env(OH_HOME)/emesh/hdl \ - -y $env(OH_HOME)/common/hdl \ - -y $env(EPIPHANY_HOME)/chip/hdl \ - -y $env(EPIPHANY_HOME)/ecore/hdl \ - -y $env(EPIPHANY_HOME)/emesh/hdl \ - -y $env(EPIPHANY_HOME)/edma/hdl \ - -y $env(EPIPHANY_HOME)/compute/hdl \ - -y $env(EPIPHANY_HOME)/memory/hdl \ - -y $env(EPIPHANY_HOME)/fpumm/hdl \ - +incdir+$env(EPIPHANY_HOME)/emesh/hdl \ - +incdir+$env(EPIPHANY_HOME)/ecore/hdl \ - +incdir+$env(EPIPHANY_HOME)/edma/hdl" - -set OH_CONSTRAINTS "${OH_DESIGN}.sdc" - -set OH_FLOORPLAN "${OH_DESIGN}_floorplan.tcl" - -set OH_LIBS "svtlib lvtlib"; # ip library names - -set OH_MACROS "sram_macro"; # hard macro library names - -set OH_VENDOR "synopsys"; # eda vendor name - -set OH_TOOL "dc"; # name of eda vendor synthesis tool - -###################################### -# RUN SYNTHESIS -##################################### -source $LOCALPATH/run.tcl - diff --git a/eda/synthesis/run.tcl b/eda/synthesis/run.tcl deleted file mode 100644 index d8e6d6d..0000000 --- a/eda/synthesis/run.tcl +++ /dev/null @@ -1,94 +0,0 @@ -#SET PATH -set LOCALPATH [file dirname [ info script ]] - -################################ -# SETUP PROCESS -################################ - -source $env(PROCESS_HOME)/eda/$OH_VENDOR/setup_process.tcl - -################################ -# CHECK ENVIRONMENT VARIABLES -################################ - -set OH_VENDOR "synopsys" -set OH_MACROS "" -set OH_TARGET "" - -if {[string match synopsys $OH_VENDOR]} { - set OH_TOOL "dc" -} elseif {[string match cadence $OH_VENDOR]} { - set OH_TOOL "rc" -} elseif {[string match xilinx $OH_VENDOR]} { - set OH_TOOL "vivado" -} - -# Check that all variabls are defined -# If not defined exit! -puts $OH_DESIGN -puts $OH_TOP -puts $OH_CFG -puts $OH_LIBS -puts $OH_FLOORPLAN -puts $OH_VENDOR -puts $OH_TOOL -puts $OH_TARGET -puts $OH_MACROS -puts $OH_LAYER_MIN -puts $OH_LAYER_MAX -puts $OH_LIBPATH -puts $OH_TECHFILE -puts $OH_MAP -puts $OH_RCMODEL_MAX -puts $OH_RCMODEL_MIN - -################################ -# STEP1: SETUP TOOL -################################ - -source $LOCALPATH/01_setup.tcl - -################################ -# STEP2: READ HDL -################################ - -source $LOCALPATH/02_hdl.tcl - -################################ -# STEP3: READ CONSTRAINTS -################################ - -source $LOCALPATH/03_constrain.tcl - -################################ -# STEP4: READ FLROOPLAN -################################ - -source $LOCALPATH/04_floorplan.tcl - -################################ -# STEP5: COMPILE -################################ - -source $LOCALPATH/05_compile.tcl - -################################ -# STEP6: DFT -################################ - -source $LOCALPATH/06_dft.tcl - -################################ -# STEP7: OPTIMIZE -################################ - -source $LOCALPATH/07_optimize.tcl - -################################ -# STEP8: WRITE NETLIST/REPORTS -################################ - -source $LOCALPATH/08_signoff.tcl - -#exit -