From 3c8be0c08330e71aa54474df67567a6af1aab570 Mon Sep 17 00:00:00 2001 From: "Andreas.Olofsson" Date: Fri, 13 Mar 2020 12:24:35 -0400 Subject: [PATCH] Fixing brain-dead bug! -I guess nobody has been using this fifo, because it was hoplessly broken. Fucking sad. --- common/hdl/oh_fifo_sync.v | 28 ++++++++++++++---- common/hdl/oh_memory_dp.v | 13 +++++---- common/hdl/oh_memory_ram.v | 58 ++++++++++++++++++++++++++------------ 3 files changed, 71 insertions(+), 28 deletions(-) diff --git a/common/hdl/oh_fifo_sync.v b/common/hdl/oh_fifo_sync.v index c30e053..a715e2e 100644 --- a/common/hdl/oh_fifo_sync.v +++ b/common/hdl/oh_fifo_sync.v @@ -7,6 +7,7 @@ module oh_fifo_sync #(parameter DW = 104, //FIFO width parameter DEPTH = 32, //FIFO depth + parameter REG = 1, //Register fifo output parameter PROG_FULL = (DEPTH/2),//prog_full threshold parameter AW = $clog2(DEPTH) //rd_count width ) @@ -28,12 +29,14 @@ module oh_fifo_sync #(parameter DW = 104, //FIFO width reg [AW-1:0] rd_addr; wire fifo_read; wire fifo_write; - - assign empty = (rd_count[AW-1:0] == 0); - assign prog_full = (rd_count[AW-1:0] >= PROG_FULL); - assign full = (rd_count[AW-1:0] == (DEPTH-1)); + assign fifo_read = rd_en & ~empty; assign fifo_write = wr_en & ~full; + assign prog_full = (rd_count[AW-1:0] >= PROG_FULL); + assign full = (rd_count[AW-1:0] == (DEPTH-1)); + assign fifo_empty = (rd_count[AW-1:0] == 0); + + always @ (posedge clk or negedge nreset) if(~nreset) @@ -63,11 +66,26 @@ module oh_fifo_sync #(parameter DW = 104, //FIFO width rd_addr[AW-1:0] <= rd_addr[AW-1:0] + 'd1; rd_count[AW-1:0]<= rd_count[AW-1:0] - 'd1; end + + //Empty register to account for RAM output register + generate + if(REG) + begin + reg empty_reg; + always @ (posedge clk) + empty_reg <= fifo_empty; + assign empty= empty_reg; + end + else + assign empty= fifo_empty; + endgenerate + // GENERIC DUAL PORTED MEMORY oh_memory_dp #(.DW(DW), - .DEPTH(DEPTH)) + .DEPTH(DEPTH), + .REG(REG)) mem (// read port .rd_dout (dout[DW-1:0]), .rd_clk (clk), diff --git a/common/hdl/oh_memory_dp.v b/common/hdl/oh_memory_dp.v index fa36636..97abe8b 100644 --- a/common/hdl/oh_memory_dp.v +++ b/common/hdl/oh_memory_dp.v @@ -8,7 +8,8 @@ module oh_memory_dp # (parameter DW = 104, //memory width parameter DEPTH = 32, //memory depth parameter PROJ = "", //project name - parameter MCW = 8, //repair/config vector width + parameter MCW = 8, //repair/config vector width + parameter REG = 1, //register memory output parameter AW = $clog2(DEPTH) // address bus width ) (// Memory interface (dual port) @@ -37,8 +38,9 @@ module oh_memory_dp # (parameter DW = 104, //memory width `ifdef CFG_ASIC oh_memory_ram #(.DW(DW), - .DEPTH(DEPTH)) - memory_dp (//read port + .DEPTH(DEPTH), + .REG(REG)) + macro (//read port .rd_dout (rd_dout[DW-1:0]), .rd_clk (rd_clk), .rd_en (rd_en), @@ -51,8 +53,9 @@ module oh_memory_dp # (parameter DW = 104, //memory width .wr_din (wr_din[DW-1:0])); `else oh_memory_ram #(.DW(DW), - .DEPTH(DEPTH)) - memory_dp (//read port + .DEPTH(DEPTH), + .REG(REG)) + macro (//read port .rd_dout (rd_dout[DW-1:0]), .rd_clk (rd_clk), .rd_en (rd_en), diff --git a/common/hdl/oh_memory_ram.v b/common/hdl/oh_memory_ram.v index 10a387f..a789013 100644 --- a/common/hdl/oh_memory_ram.v +++ b/common/hdl/oh_memory_ram.v @@ -5,36 +5,58 @@ //# License: MIT (see LICENSE file in OH! repository) # //############################################################################# -module oh_memory_ram # (parameter DW = 104, //memory width - parameter DEPTH = 32, //memory depth +module oh_memory_ram # (parameter DW = 104, // memory width + parameter DEPTH = 32, // memory depth + parameter REG = 1, // register output parameter AW = $clog2(DEPTH) // address width ) (// read-port - input rd_clk,// rd clock - input rd_en, // memory access - input [AW-1:0] rd_addr, // address - output reg [DW-1:0] rd_dout, // data output + input rd_clk,// rd clock + input rd_en, // memory access + input [AW-1:0] rd_addr, // address + output [DW-1:0] rd_dout, // data output // write-port - input wr_clk,// wr clock - input wr_en, // memory access - input [AW-1:0] wr_addr, // address - input [DW-1:0] wr_wem, // write enable vector - input [DW-1:0] wr_din // data input + input wr_clk,// wr clock + input wr_en, // memory access + input [AW-1:0] wr_addr, // address + input [DW-1:0] wr_wem, // write enable vector + input [DW-1:0] wr_din // data input ); reg [DW-1:0] ram [DEPTH-1:0]; + wire [DW-1:0] rdata; integer i; - - //registered read port - always @ (posedge rd_clk) - if(rd_en) - rd_dout[DW-1:0] <= ram[rd_addr[AW-1:0]]; - - //write port with vector enable + + //######################################### + //write port + //######################################### always @(posedge wr_clk) for (i=0;i