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Working mailbox!

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- Gating mailbox_not empty with irq_en. bit [28] of RXCFG
- Changing elink output interrupt to "or" of not_empty and full
- Adding mailbox status register (mostly for debug)
- Moving register addresses to make space for mailbox status register
- Fixing wrappers for DV
- Updating README docs with new register map
- Removing mailbox from RX status reg. Doesn't belong there, should be coupled with mailbox for modularity.
This commit is contained in:
Andreas Olofsson 2015-11-29 12:20:17 -05:00
parent 711088a9e7
commit 3ce9b41726
12 changed files with 160 additions and 154 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

113
elink/README.md
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@ -177,30 +177,31 @@ elink
The full 32 bit physical address of an elink register is the address seen below added to the 12 bit elink ID that maps to address bits 31:20. As an example, if the elink ID is 0x810, then writing to the E_RESET register would be done to address 0x810F0200. Readback is done through the txrd channel with the source address sub field set to 810Dxxxx;
REGISTER | ACCESS | ADDRESS | DESCRIPTION
----------------|--------|---------|------------------
ELINK_RESET | -W | 0xF0200 | Soft reset
ELINK_CLK | -W | 0xF0204 | Clock configuration
ELINK_CHIPID | RW | 0xF0208 | Chip ID for Epiphany pins
ELINK_VERSION | RW | 0xF020C | Version number (static)
****************|********|*********|**************************
ELINK_TXCFG | RW | 0xF0210 | TX configuration
ELINK_TXSTATUS | R- | 0xF0214 | TX status
ELINK_TXGPIO | RW | 0xF0218 | TX data in GPIO mode
ELINK_TXMONITOR | RW | 0xF021C | TX transaction monitor
ELINK_TXPACKET | RW | 0xF0220 | TX packet sampler
ELINK_TXMMU | -W | 0xE0000 | TX MMU table
****************|******* |*********|********************
ELINK_RXCFG | RW | 0xF0300 | RX configuration
ELINK_RXSTATUS | R- | 0xF0304 | RX status register
ELINK_RXGPIO | R- | 0xF0308 | RX data in GPIO mode
ELINK_RXOFFSET | RW | 0xF030C | RX mem offset in remap mode
ELINK_MAILBOXLO | RW | 0xF0310 | RX mailbox (lower 32 bit)
ELINK_MAILBOXHI | RW | 0xF0314 | RX mailbox (upper 32 bits)
ELINK_RXDELAY0 | RW | 0xF0318 | RX idelays 4 bit values d[7:0]
ELINK_RXDELAY1 | RW | 0xF031C | RX idelay msbs and frametap lsbs
ELINK_RXTESTDATA| RW | 0xF0320 | RX sampled data
ELINK_RXMMU | -W | 0xE8000 | RX MMU table
REGISTER | ACCESS | ADDRESS | DESCRIPTION
-----------------|--------|---------|------------------
ELINK_RESET | -W | 0xF0200 | Soft reset
ELINK_CLK | -W | 0xF0204 | Clock configuration
ELINK_CHIPID | RW | 0xF0208 | Chip ID for Epiphany pins
ELINK_VERSION | RW | 0xF020C | Version number (static)
*****************|********|*********|**************************
ELINK_TXCFG | RW | 0xF0210 | TX configuration
ELINK_TXSTATUS | R- | 0xF0214 | TX status
ELINK_TXGPIO | RW | 0xF0218 | TX data in GPIO mode
ELINK_TXMONITOR | RW | 0xF021C | TX transaction monitor
ELINK_TXPACKET | RW | 0xF0220 | TX packet sampler
ELINK_TXMMU | -W | 0xE0000 | TX MMU table
*****************|******* |*********|********************
ELINK_RXCFG | RW | 0xF0300 | RX configuration
ELINK_RXSTATUS | R- | 0xF0304 | RX status register
ELINK_RXGPIO | R- | 0xF0308 | RX data in GPIO mode
ELINK_RXOFFSET | RW | 0xF030C | RX mem offset in remap mode
ELINK_RXDELAY0 | RW | 0xF0310 | RX idelays 4 bit values d[7:0]
ELINK_RXDELAY1 | RW | 0xF0314 | RX idelay msbs and frametap lsbs
ELINK_RXTESTDATA | RW | 0xF0318 | RX sampled data
ELINK_MAILBOXLO | RW | 0xF0320 | RX mailbox (lower 32 bit)
ELINK_MAILBOXHI | RW | 0xF0324 | RX mailbox (upper 32 bits)
ELINK_MAILBOXSTAT| RW | 0xF0328 | RX mailbox status
ELINK_RXMMU | -W | 0xE8000 | RX MMU table
## ELINK_RESET (0xF0200)
Reset control register for the elink and Epiphany chip
@ -374,13 +375,8 @@ FIELD | DESCRIPTION
[15:4] | Remap selection for "01" remap method
| "1" means remap bit is selected
[27:16] | Remap values (for addr[31:20)
[29:28] | Read request timeout counter configuration
| 00: Timeout counter turned off
| 01: Timeout value set to 000000FF
| 10: Timeout value set to 0000FFFF
| 11: Timeout value set to FFFFFFFF
-------------------------------
[28] | Enable mailbox interrupt
------------------------------
## ELINK_RXSTATUS (0xF0304)
RX status register. All bits are sticky.
@ -410,25 +406,7 @@ FIELD | DESCRIPTION
-------------------------------
## ELINK_MAILBOXLO (0xF0310)
Lower 32 bit word of current entry of RX 64-bit wide mailbox FIFO. Must be read before ELINK_MAILBOXHI is read
FIELD | DESCRIPTION
-------- |---------------------------------------------------
[31:0] | Upper data of RX FIFO
-------------------------------
## ELINK_MAILBOXHI (0xF0314)
Upper 32 bit word of current entry of RX 64-bit wide mailbox FIFO. Reading this register causes the RX FIFO read pointer to increment by one.
FIELD | DESCRIPTION
-------- |---------------------------------------------------
[31:0] | Upper data of RX FIFO
-------------------------------
## ELINK_RXDELAY0 (0xF0318)
## ELINK_RXDELAY0 (0xF0310)
Four bit LSB fields for the RX IDELAY of data bits [7:0]
FIELD | DESCRIPTION
@ -444,7 +422,7 @@ FIELD | DESCRIPTION
-------------------------------
## ELINK_RXDELAY1 (0xF031c)
## ELINK_RXDELAY1 (0xF0314)
MSB field for all RX IDELAY values and lsbs for frame signal
FIELD | DESCRIPTION
@ -462,6 +440,39 @@ FIELD | DESCRIPTION
-------------------------------
## ELINK_TESTDATA (0xF0318)
Debug register for monitoring incoming transctions.
FIELD | DESCRIPTION
--------|---------------------------------------------------
[31:0] | Updated with (old value + value of incoming RX transaction)
-------------------------------
## ELINK_MAILBOXLO (0xF0320)
Lower 32 bit word of current entry of RX 64-bit wide mailbox FIFO. Must be read before ELINK_MAILBOXHI is read
FIELD | DESCRIPTION
-------- |---------------------------------------------------
[31:0] | Upper data of RX FIFO
-------------------------------
## ELINK_MAILBOXHI (0xF0324)
Upper 32 bit word of current entry of RX 64-bit wide mailbox FIFO. Reading this register causes the RX FIFO read pointer to increment by one.
FIELD | DESCRIPTION
-------- |---------------------------------------------------
[31:0] | Upper data of RX FIFO
## ELINK_MAILBOXSTAT (0xF0328)
Status of mailbox
FIELD | DESCRIPTION
-------- |---------------------------------------------------
[0] | Mailbox is NOT empty
[1] | Mailbox is full
## ELINK_RXMMU (0xE8000)
A table of N entries for translating incoming 12 bit address to a new value. Entries are aligned on 8 byte boundaries.

10
elink/dv/dut_axi_elink.v
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@ -79,6 +79,7 @@ module dut(/*AUTOARG*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire elink0_chip_nreset; // From elink0 of elink.v
wire elink0_mailbox_irq; // From elink0 of elink.v
wire elink0_rxo_rd_wait_n; // From elink0 of elink.v
wire elink0_rxo_rd_wait_p; // From elink0 of elink.v
wire elink0_rxo_wr_wait_n; // From elink0 of elink.v
@ -137,6 +138,7 @@ module dut(/*AUTOARG*/
wire elink1_m_axi_wready; // From esaxi of esaxi.v
wire [7:0] elink1_m_axi_wstrb; // From elink1 of axi_elink.v
wire elink1_m_axi_wvalid; // From elink1 of axi_elink.v
wire elink1_mailbox_irq; // From elink1 of axi_elink.v
wire elink1_rxo_rd_wait_n; // From elink1 of axi_elink.v
wire elink1_rxo_rd_wait_p; // From elink1 of axi_elink.v
wire elink1_rxo_wr_wait_n; // From elink1 of axi_elink.v
@ -388,9 +390,7 @@ module dut(/*AUTOARG*/
.cclk_p (elink0_cclk_p), // Templated
.cclk_n (elink0_cclk_n), // Templated
.chip_nreset (elink0_chip_nreset), // Templated
.mailbox_not_empty (elink0_mailbox_not_empty), // Templated
.mailbox_full (elink0_mailbox_full), // Templated
.timeout (elink0_timeout), // Templated
.mailbox_irq (elink0_mailbox_irq), // Templated
.rxrr_access (elink0_rxrr_access), // Templated
.rxrr_packet (elink0_rxrr_packet[PW-1:0]), // Templated
.txwr_wait (elink0_txwr_wait), // Templated
@ -465,8 +465,7 @@ module dut(/*AUTOARG*/
.chip_nreset (elink1_chip_nreset), // Templated
.cclk_p (elink1_cclk_p), // Templated
.cclk_n (elink1_cclk_n), // Templated
.mailbox_not_empty (elink1_mailbox_not_empty), // Templated
.mailbox_full (elink1_mailbox_full), // Templated
.mailbox_irq (elink1_mailbox_irq), // Templated
.m_axi_awid (elink1_m_axi_awid[M_IDW-1:0]), // Templated
.m_axi_awaddr (elink1_m_axi_awaddr[31:0]), // Templated
.m_axi_awlen (elink1_m_axi_awlen[7:0]), // Templated
@ -505,7 +504,6 @@ module dut(/*AUTOARG*/
.s_axi_rresp (stub_m_axi_rresp[1:0]), // Templated
.s_axi_rvalid (stub_m_axi_rvalid), // Templated
.s_axi_wready (stub_m_axi_wready), // Templated
.timeout (elink1_timeout), // Templated
// Inputs
.sys_clk (clk), // Templated
.m_axi_awready (elink1_m_axi_awready), // Templated

5
elink/dv/dut_e16ref.v
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@ -94,6 +94,7 @@ module dut(/*AUTOARG*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire elink0_chip_nreset; // From elink0 of elink.v
wire elink0_mailbox_irq; // From elink0 of elink.v
wire elink0_rxo_rd_wait_n; // From elink0 of elink.v
wire elink0_rxo_rd_wait_p; // From elink0 of elink.v
wire elink0_rxo_wr_wait_n; // From elink0 of elink.v
@ -209,9 +210,7 @@ module dut(/*AUTOARG*/
.cclk_p (elink0_cclk_p), // Templated
.cclk_n (elink0_cclk_n), // Templated
.chip_nreset (elink0_chip_nreset), // Templated
.mailbox_not_empty (elink0_mailbox_not_empty), // Templated
.mailbox_full (elink0_mailbox_full), // Templated
.timeout (elink0_timeout), // Templated
.mailbox_irq (elink0_mailbox_irq), // Templated
.rxrr_access (elink0_rxrr_access), // Templated
.rxrr_packet (elink0_rxrr_packet[PW-1:0]), // Templated
.txwr_wait (elink0_txwr_wait), // Templated

10
elink/dv/dut_elink.v
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@ -79,6 +79,7 @@ module dut(/*AUTOARG*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire elink0_chip_nreset; // From elink0 of elink.v
wire elink0_mailbox_irq; // From elink0 of elink.v
wire elink0_rxo_rd_wait_n; // From elink0 of elink.v
wire elink0_rxo_rd_wait_p; // From elink0 of elink.v
wire elink0_rxo_wr_wait_n; // From elink0 of elink.v
@ -99,6 +100,7 @@ module dut(/*AUTOARG*/
wire elink0_txwr_wait; // From elink0 of elink.v
wire elink1_chip_nreset; // From elink1 of elink.v
wire elink1_elink_active; // From elink1 of elink.v
wire elink1_mailbox_irq; // From elink1 of elink.v
wire elink1_rxo_rd_wait_n; // From elink1 of elink.v
wire elink1_rxo_rd_wait_p; // From elink1 of elink.v
wire elink1_rxo_wr_wait_n; // From elink1 of elink.v
@ -206,9 +208,7 @@ module dut(/*AUTOARG*/
.cclk_p (elink0_cclk_p), // Templated
.cclk_n (elink0_cclk_n), // Templated
.chip_nreset (elink0_chip_nreset), // Templated
.mailbox_not_empty (elink0_mailbox_not_empty), // Templated
.mailbox_full (elink0_mailbox_full), // Templated
.timeout (elink0_timeout), // Templated
.mailbox_irq (elink0_mailbox_irq), // Templated
.rxrr_access (elink0_rxrr_access), // Templated
.rxrr_packet (elink0_rxrr_packet[PW-1:0]), // Templated
.txwr_wait (elink0_txwr_wait), // Templated
@ -279,9 +279,7 @@ module dut(/*AUTOARG*/
.cclk_p (elink1_cclk_p), // Templated
.cclk_n (elink1_cclk_n), // Templated
.chip_nreset (elink1_chip_nreset), // Templated
.mailbox_not_empty (elink1_mailbox_not_empty), // Templated
.mailbox_full (elink1_mailbox_full), // Templated
.timeout (elink1_timeout), // Templated
.mailbox_irq (elink1_mailbox_irq), // Templated
.rxwr_access (elink1_rxwr_access), // Templated
.rxwr_packet (elink1_rxwr_packet[PW-1:0]), // Templated
.rxrd_access (elink1_rxrd_access), // Templated

33
elink/hdl/axi_elink.v
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@ -1,17 +1,17 @@
module axi_elink(/*AUTOARG*/
// Outputs
timeout, elink_active, rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p,
elink_active, rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p,
rxo_rd_wait_n, txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n,
txo_data_p, txo_data_n, chipid, chip_nreset, cclk_p, cclk_n,
mailbox_not_empty, mailbox_full, m_axi_awid, m_axi_awaddr,
m_axi_awlen, m_axi_awsize, m_axi_awburst, m_axi_awlock,
m_axi_awcache, m_axi_awprot, m_axi_awqos, m_axi_awvalid, m_axi_wid,
m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wvalid, m_axi_bready,
m_axi_arid, m_axi_araddr, m_axi_arlen, m_axi_arsize, m_axi_arburst,
m_axi_arlock, m_axi_arcache, m_axi_arprot, m_axi_arqos,
m_axi_arvalid, m_axi_rready, s_axi_arready, s_axi_awready,
s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_rid, s_axi_rdata,
s_axi_rlast, s_axi_rresp, s_axi_rvalid, s_axi_wready,
mailbox_irq, m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize,
m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot,
m_axi_awqos, m_axi_awvalid, m_axi_wid, m_axi_wdata, m_axi_wstrb,
m_axi_wlast, m_axi_wvalid, m_axi_bready, m_axi_arid, m_axi_araddr,
m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arlock,
m_axi_arcache, m_axi_arprot, m_axi_arqos, m_axi_arvalid,
m_axi_rready, s_axi_arready, s_axi_awready, s_axi_bid, s_axi_bresp,
s_axi_bvalid, s_axi_rid, s_axi_rdata, s_axi_rlast, s_axi_rresp,
s_axi_rvalid, s_axi_wready,
// Inputs
sys_nreset, sys_clk, rxi_lclk_p, rxi_lclk_n, rxi_frame_p,
rxi_frame_n, rxi_data_p, rxi_data_n, txi_wr_wait_p, txi_wr_wait_n,
@ -70,8 +70,7 @@ module axi_elink(/*AUTOARG*/
/*****************************/
/*MAILBOX (interrupts) */
/*****************************/
output mailbox_not_empty;
output mailbox_full;
output mailbox_irq;
//########################
//AXI MASTER INTERFACE
@ -185,11 +184,7 @@ module axi_elink(/*AUTOARG*/
/*#############################################*/
/*AUTOINPUT*/
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output timeout; // From elink of elink.v
// End of automatics
/*AUTOOUTPUT*/
// End of automatics
/*AUTOWIRE*/
@ -241,9 +236,7 @@ module axi_elink(/*AUTOARG*/
.cclk_p (cclk_p),
.cclk_n (cclk_n),
.chip_nreset (chip_nreset),
.mailbox_not_empty (mailbox_not_empty),
.mailbox_full (mailbox_full),
.timeout (timeout),
.mailbox_irq (mailbox_irq),
.rxwr_access (rxwr_access),
.rxwr_packet (rxwr_packet[PW-1:0]),
.rxrd_access (rxrd_access),

17
elink/hdl/elink.v
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@ -3,9 +3,8 @@ module elink (/*AUTOARG*/
elink_active, rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p,
rxo_rd_wait_n, txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n,
txo_data_p, txo_data_n, chipid, cclk_p, cclk_n, chip_nreset,
mailbox_not_empty, mailbox_full, timeout, rxwr_access, rxwr_packet,
rxrd_access, rxrd_packet, rxrr_access, rxrr_packet, txwr_wait,
txrd_wait, txrr_wait,
mailbox_irq, rxwr_access, rxwr_packet, rxrd_access, rxrd_packet,
rxrr_access, rxrr_packet, txwr_wait, txrd_wait, txrr_wait,
// Inputs
sys_nreset, sys_clk, rxi_lclk_p, rxi_lclk_n, rxi_frame_p,
rxi_frame_n, rxi_data_p, rxi_data_n, txi_wr_wait_p, txi_wr_wait_n,
@ -55,14 +54,8 @@ module elink (/*AUTOARG*/
/*****************************/
/*MAILBOX INTERRUPTS */
/*****************************/
output mailbox_not_empty;
output mailbox_full;
output mailbox_irq;
/*****************************/
/*TIMEOUT */
/*****************************/
output timeout;
/*****************************/
/*SYSTEM SIDE INTERFACE */
/*****************************/
@ -173,9 +166,7 @@ module elink (/*AUTOARG*/
.erx_cfg_wait (erx_cfg_wait),
.rx_lclk_div4 (rx_lclk_div4),
.erx_nreset (erx_nreset),
.timeout (timeout),
.mailbox_full (mailbox_full),
.mailbox_not_empty (mailbox_not_empty),
.mailbox_irq (mailbox_irq),
// Inputs
.soft_reset (erx_soft_reset), // Templated
.sys_nreset (sys_nreset),

20
elink/hdl/elink_regmap.v
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@ -25,24 +25,22 @@
`define ETX_STATUS 6'd5 //F0214-tx status
`define ETX_GPIO 6'd6 //F0218-direct data for tx pins
`define ETX_MONITOR 6'd7 //F021C-transaction monitor
`define ETX_PACKET 6'd8 //F0220-packet sampler
`define ETX_PACKET 6'd8 //F0220-outgoing packet sampler
//ERX-REGS
`define ERX_CFG 6'd0 //F0300-config
`define ERX_STATUS 6'd1 //F0304-status register
`define ERX_GPIO 6'd2 //F0308-sampled data
`define ERX_OFFSET 6'd3 //F030C-memory base for remap
`define ERX_IDELAY0 6'd4 //F0310-tap delay for d[5:0]
`define ERX_IDELAY1 6'd5 //F0314-tap delays for {frame,d[7:6]}
`define ERX_TESTDATA 6'd6 //F0318-received test data
`define ERX_IDELAY0 6'd6 //F0318-tap delay for d[5:0]
`define ERX_IDELAY1 6'd7 //F031c-tap delays for {frame,d[7:6]}
`define ERX_TESTDATA 6'd8 //F0320-
//MAILBOX
`ifndef E_MAILBOXLO
`define E_MAILBOXLO 6'd4 //F0310-reserved
`endif
`ifndef E_MAILBOXHI
`define E_MAILBOXHI 6'd5 //F0314-reserved
//MAILBOX REGS
`ifndef E_MAILBOXLO
`define E_MAILBOXLO 6'd8 //F0320-reserved
`define E_MAILBOXHI 6'd9 //F0324-reserved
`define E_MAILBOXSTAT 6'd10 //F0328-reserved
`endif
//DMA (same numbering as in Epiphany, limit to 4 channels)

14
elink/hdl/erx.v
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@ -3,7 +3,7 @@ module erx (/*AUTOARG*/
rx_active, rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p,
rxo_rd_wait_n, rxwr_access, rxwr_packet, rxrd_access, rxrd_packet,
rxrr_access, rxrr_packet, erx_cfg_wait, rx_lclk_div4, erx_nreset,
timeout, mailbox_full, mailbox_not_empty,
mailbox_irq,
// Inputs
soft_reset, sys_nreset, sys_clk, tx_active, rxi_lclk_p, rxi_lclk_n,
rxi_frame_p, rxi_frame_n, rxi_data_p, rxi_data_n, rxwr_wait,
@ -55,14 +55,9 @@ module erx (/*AUTOARG*/
output erx_nreset;
//Readback timeout (synchronized to sys_c
output timeout;
output mailbox_full;
output mailbox_not_empty;
//Mailbox interrupt
output mailbox_irq;
//hack up for now
assign timeout = 1'b0;
/*AUTOOUTPUT*/
/*AUTOINPUT*/
@ -168,8 +163,7 @@ module erx (/*AUTOARG*/
.rxwr_access (rxwr_fifo_access), // Templated
.rxwr_packet (rxwr_fifo_packet[PW-1:0]), // Templated
.erx_cfg_wait (erx_cfg_wait), // Templated
.mailbox_full (mailbox_full),
.mailbox_not_empty(mailbox_not_empty),
.mailbox_irq (mailbox_irq),
// Inputs
.rx_packet (rx_packet[PW-1:0]), // Templated
.rx_access (rx_access), // Templated

30
elink/hdl/erx_cfg.v
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@ -7,6 +7,7 @@ module erx_cfg (/*AUTOARG*/
// Outputs
mi_dout, mmu_enable, remap_mode, remap_base, remap_pattern,
remap_sel, timer_cfg, idelay_value, load_taps, test_mode,
mailbox_irq_en,
// Inputs
nreset, clk, mi_en, mi_we, mi_addr, mi_din, erx_test_access,
erx_test_data, gpio_datain, rx_status
@ -41,9 +42,7 @@ module erx_cfg (/*AUTOARG*/
/*CONFIG SIGNALS */
/*****************************/
//rx
output mmu_enable; // enables MMU on rx path (static)
input [8:0] gpio_datain; // frame and data inputs (static)
input [15:0] rx_status; // etx status signals
output mmu_enable; // enables MMU on rx path (static)
output [1:0] remap_mode; // remap mode (static)
output [31:0] remap_base; // base for dynamic remap (static)
output [11:0] remap_pattern; // patter for static remap (static)
@ -52,6 +51,13 @@ module erx_cfg (/*AUTOARG*/
output [44:0] idelay_value; // tap values for erx idelay
output load_taps; // loads the idelay_value into IDELAY prim
output test_mode; // testmode blocks all rx ports to fifo
output mailbox_irq_en; // irq enable for mailbox
/*****************************/
/*STATUS SIGNALS */
/*****************************/
input [8:0] gpio_datain; // frame and data inputs (static)
input [15:0] rx_status; // etx status signals
/*------------------------CODE BODY---------------------------------------*/
@ -106,22 +112,22 @@ module erx_cfg (/*AUTOARG*/
assign remap_mode[1:0] = rx_cfg_reg[3:2];
assign remap_sel[11:0] = rx_cfg_reg[15:4];
assign remap_pattern[11:0] = rx_cfg_reg[27:16];
assign timer_cfg[1:0] = rx_cfg_reg[29:28];
assign mailbox_irq_en = rx_cfg_reg[28];
//###########################
//# DATAIN
//###########################
always @ (posedge clk)
rx_gpio_reg[8:0] <= gpio_datain[8:0];
//###########################1
//# DEBUG
//# STATUS
//###########################
always @ (posedge clk)
always @ (posedge clk)
if (rx_status_write)
rx_status_reg[15:0] <= mi_din[15:0];
else
rx_status_reg[15:0] <= rx_status_reg[15:0] | rx_status[15:0];
//###########################
//# GPIO-DATAIN
//###########################
always @ (posedge clk)
rx_gpio_reg[8:0] <= gpio_datain[8:0];
//###########################1
//# DYNAMIC REMAP BASE

18
elink/hdl/erx_core.v
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@ -2,7 +2,7 @@ module erx_core (/*AUTOARG*/
// Outputs
rx_rd_wait, rx_wr_wait, idelay_value, load_taps, rxrd_access,
rxrd_packet, rxrr_access, rxrr_packet, rxwr_access, rxwr_packet,
erx_cfg_wait, mailbox_full, mailbox_not_empty,
erx_cfg_wait, mailbox_irq,
// Inputs
nreset, clk, rx_packet, rx_access, rx_burst, rxrd_wait, rxrr_wait,
rxwr_wait, erx_cfg_access, erx_cfg_packet
@ -46,8 +46,7 @@ module erx_core (/*AUTOARG*/
output erx_cfg_wait;
//mailbox outputs
output mailbox_full; //need to sync to sys_clk
output mailbox_not_empty; //need to sync to sys_clk
output mailbox_irq;
/*AUTOINPUT*/
/*AUTOOUTPUT*/
@ -66,6 +65,7 @@ module erx_core (/*AUTOARG*/
wire erx_rr_access; // From erx_protocol of erx_protocol.v
wire erx_test_access; // From erx_protocol of erx_protocol.v
wire [31:0] erx_test_data; // From erx_protocol of erx_protocol.v
wire mailbox_irq_en; // From erx_cfg of erx_cfg.v
wire [14:0] mi_addr; // From erx_cfgif of ecfg_if.v
wire [DW-1:0] mi_cfg_dout; // From erx_cfg of erx_cfg.v
wire mi_cfg_en; // From erx_cfgif of ecfg_if.v
@ -203,8 +203,7 @@ module erx_core (/*AUTOARG*/
/*AUTOINST*/
// Outputs
.mi_dout (mi_mailbox_dout[63:0]), // Templated
.mailbox_full (mailbox_full),
.mailbox_not_empty(mailbox_not_empty),
.mailbox_irq (mailbox_irq),
// Inputs
.nreset (nreset),
.wr_clk (clk), // Templated
@ -213,9 +212,9 @@ module erx_core (/*AUTOARG*/
.emesh_packet (emmu_packet[PW-1:0]), // Templated
.mi_en (mi_cfg_en), // Templated
.mi_we (mi_we),
.mi_addr (mi_addr[RFAW+1:0]));
.mi_addr (mi_addr[RFAW+1:0]),
.mailbox_irq_en (mailbox_irq_en));
/************************************************************/
/* CONFIGURATION INTERFACE */
/************************************************************/
@ -268,7 +267,7 @@ module erx_core (/*AUTOARG*/
rx_wr_wait,
rxrr_wait,
rxrd_wait,
rxwr_wait
rxwr_wait
};
assign gpio_datain[8:0]=9'b0;
@ -299,6 +298,7 @@ module erx_core (/*AUTOARG*/
.idelay_value (idelay_value[44:0]),
.load_taps (load_taps),
.test_mode (test_mode),
.mailbox_irq_en (mailbox_irq_en),
// Inputs
.nreset (nreset),
.clk (clk),

33
emailbox/hdl/emailbox.v
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@ -21,10 +21,10 @@
`include "emailbox_regmap.v" // is there a better way?
module emailbox (/*AUTOARG*/
// Outputs
mi_dout, mailbox_full, mailbox_not_empty,
mi_dout, mailbox_irq,
// Inputs
nreset, wr_clk, rd_clk, emesh_access, emesh_packet, mi_en, mi_we,
mi_addr
mi_addr, mailbox_irq_en
);
parameter DW = 32; //data width of fifo
@ -42,7 +42,7 @@ module emailbox (/*AUTOARG*/
input nreset; //asynchronous active low reset
input wr_clk; //write clock
input rd_clk; //read clock
/*****************************/
/*WRITE INTERFACE */
/*****************************/
@ -58,10 +58,10 @@ module emailbox (/*AUTOARG*/
output [63:0] mi_dout;
/*****************************/
/*MAILBOX OUTPUTS */
/*MAILBOX CONTROl */
/*****************************/
output mailbox_full;
output mailbox_not_empty;
input mailbox_irq_en;
output mailbox_irq;
/*****************************/
/*REGISTERS */
@ -69,6 +69,7 @@ module emailbox (/*AUTOARG*/
reg mi_rd_reg;
reg [RFAW+1:2] mi_addr_reg;
reg read_hi;
reg read_status;
/*****************************/
/*WIRES */
@ -108,16 +109,18 @@ module emailbox (/*AUTOARG*/
assign mailbox_read = mi_rd & (mi_addr[RFAW+1:2]==`E_MAILBOXLO); //fifo read
always @ (posedge rd_clk)
read_hi <= mi_rd & (mi_addr[RFAW+1:2]==`E_MAILBOXHI);
assign mi_dout[31:0] = read_hi ? mailbox_data[63:32] : mailbox_data[31:0];
begin
read_hi <= mi_rd & (mi_addr[RFAW+1:2]==`E_MAILBOXHI);
read_status <= mi_rd & (mi_addr[RFAW+1:2]==`E_MAILBOXSTAT);
end
assign mi_dout[31:0] = read_status ? {30'b0,mailbox_full, mailbox_not_empty} :
read_hi ? mailbox_data[63:32] :
mailbox_data[31:0];
assign mi_dout[63:32] = mailbox_data[63:32];
/*****************************/
/*FIFO (64bit wide) */
/*****************************/
assign mailbox_not_empty = ~mailbox_empty;
defparam fifo.DW = MW;
defparam fifo.DEPTH = DEPTH;
//TODO: fix the width and depth
@ -136,6 +139,14 @@ module emailbox (/*AUTOARG*/
.wr_en (mailbox_write),
.wr_clk (wr_clk)
);
/*****************************/
/*FIFO (64bit wide) */
/*****************************/
assign mailbox_not_empty = ~mailbox_empty;
assign mailbox_irq = mailbox_irq_en & ( mailbox_not_empty | mailbox_full);
endmodule // emailbox

11
emailbox/hdl/emailbox_regmap.v
View File

@ -2,16 +2,23 @@
`define EMAILBOX_REGMAP_V_
`ifndef E_MAILBOXLO
`define E_MAILBOXLO 6'd4
`define E_MAILBOXLO 6'd8
`endif
`ifndef E_MAILBOXHI
`define E_MAILBOXHI 6'd5
`define E_MAILBOXHI 6'd9
`endif
`ifndef E_MAILBOXSTAT
`define E_MAILBOXSTAT 6'd10
`endif
`ifndef EGROUP_MMR
`define EGROUP_MMR 4'hF
`endif
`endif