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Making almost full programmable in oh_fifo_sync

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Andreas.Olofsson 2020-12-07 16:58:47 -05:00
parent 401d1c2e93
commit 3e49fa499f
1 changed files with 10 additions and 9 deletions
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19
common/hdl/oh_fifo_sync.v
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@ -6,13 +6,14 @@
//############################################################################# //#############################################################################
module oh_fifo_sync module oh_fifo_sync
#(parameter DW = 104, // FIFO width #(parameter DW = 104, // FIFO width
parameter DEPTH = 32, // FIFO depth parameter DEPTH = 32, // FIFO depth
parameter REG = 1, // Register fifo output parameter REG = 1, // Register fifo output
parameter AW = $clog2(DEPTH),// rd_count width (derived) parameter AW = $clog2(DEPTH),// rd_count width (derived)
parameter TYPE = "soft", // hard=hard macro,soft=synthesizable parameter PROGFULL = DEPTH-1, // programmable almost full level
parameter CONFIG = "default", // hard macro user config pass through parameter TYPE = "soft", // hard=hard macro,soft=synthesizable
parameter SHAPE = "square" // hard macro shape (square, tall, wide) parameter CONFIG = "default", // hard macro user config pass through
parameter SHAPE = "square" // hard macro shape (square, tall, wide)
) )
( (
//basic interface //basic interface
@ -24,7 +25,7 @@ module oh_fifo_sync
input [DW-1:0] din, // data to write input [DW-1:0] din, // data to write
input wr_en, // write fifo input wr_en, // write fifo
output full, // fifo full output full, // fifo full
output prog_full, // fifo is almost full output almost_full, //progfull level reached
//read port //read port
input rd_en, // read fifo input rd_en, // read fifo
output [DW-1:0] dout, // output data (next cycle) output [DW-1:0] dout, // output data (next cycle)
@ -56,7 +57,7 @@ module oh_fifo_sync
//############################ //############################
assign fifo_read = rd_en & ~empty; assign fifo_read = rd_en & ~empty;
assign fifo_write = wr_en & ~full; assign fifo_write = wr_en & ~full;
assign prog_full = (rd_count[AW-1:0] == (DEPTH-1)); assign almost_full = (rd_count[AW-1:0] == PROGFULL);
assign ptr_match = (wr_addr[AW-1:0] == rd_addr[AW-1:0]); assign ptr_match = (wr_addr[AW-1:0] == rd_addr[AW-1:0]);
assign full = ptr_match & (wr_addr[AW]==!rd_addr[AW]); assign full = ptr_match & (wr_addr[AW]==!rd_addr[AW]);
assign fifo_empty = ptr_match & (wr_addr[AW]==rd_addr[AW]); assign fifo_empty = ptr_match & (wr_addr[AW]==rd_addr[AW]);