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Moving models out of hdl
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Andreas Olofsson
parent
dbff2623c1
commit
3e78d06051
198
emesh/dv/ememory.v
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198
emesh/dv/ememory.v
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module ememory(/*AUTOARG*/
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// Outputs
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wait_out, access_out, packet_out,
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// Inputs
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clk, nreset, coreid, access_in, packet_in, wait_in
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);
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parameter PW = 104;
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parameter IDW = 12;
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parameter DW = 32;
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parameter AW = 32;
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parameter MAW = 16; //=64K words
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parameter NAME = "emem";
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//Basic Interface
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input clk;
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input nreset;
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input [IDW-1:0] coreid;
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//incoming read/write
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input access_in;
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input [PW-1:0] packet_in;
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output wait_out; //pushback
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//back to mesh (readback data)
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output access_out;
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output [PW-1:0] packet_out;
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input wait_in; //pushback
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wire [MAW-1:0] addr;
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wire [63:0] din;
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wire [63:0] dout;
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wire en;
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wire mem_rd;
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wire mem_wr;
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reg [7:0] wen;
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//State
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reg access_out;
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reg write_out;
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reg [1:0] datamode_out;
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reg [4:0] ctrlmode_out;
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reg [AW-1:0] dstaddr_out;
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wire [AW-1:0] srcaddr_out;
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wire [AW-1:0] data_out;
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reg hilo_sel;
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wire write_in;
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wire [1:0] datamode_in;
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wire [3:0] ctrlmode_in;
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wire [AW-1:0] dstaddr_in;
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wire [DW-1:0] data_in;
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wire [AW-1:0] srcaddr_in;
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packet2emesh #(.PW(PW))
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p2e (
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.write_out (write_in),
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.datamode_out (datamode_in[1:0]),
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.ctrlmode_out (ctrlmode_in[3:0]),
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.dstaddr_out (dstaddr_in[AW-1:0]),
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.data_out (data_in[DW-1:0]),
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.srcaddr_out (srcaddr_in[AW-1:0]),
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.packet_in (packet_in[PW-1:0])
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);
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//Access-in
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assign mem_rd = (access_in & ~write_in & ~wait_in);
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assign mem_wr = (access_in & write_in );
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assign en = mem_rd | mem_wr;
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//Pushback Circuit (pass through problems?)
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assign wait_out = access_in & wait_in;
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//Address-in (shifted by three bits, 64 bit wide memory)
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assign addr[MAW-1:0] = dstaddr_in[MAW+2:3];
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//Data-in (hardoded width)
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assign din[63:0] =(datamode_in[1:0]==2'b11) ? {srcaddr_in[31:0],data_in[31:0]}:
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{data_in[31:0],data_in[31:0]};
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//Write mask
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always@*
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casez({write_in, datamode_in[1:0],dstaddr_in[2:0]})
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//Byte
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6'b100000 : wen[7:0] = 8'b00000001;
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6'b100001 : wen[7:0] = 8'b00000010;
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6'b100010 : wen[7:0] = 8'b00000100;
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6'b100011 : wen[7:0] = 8'b00001000;
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6'b100100 : wen[7:0] = 8'b00010000;
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6'b100101 : wen[7:0] = 8'b00100000;
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6'b100110 : wen[7:0] = 8'b01000000;
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6'b100111 : wen[7:0] = 8'b10000000;
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//Short
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6'b10100? : wen[7:0] = 8'b00000011;
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6'b10101? : wen[7:0] = 8'b00001100;
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6'b10110? : wen[7:0] = 8'b00110000;
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6'b10111? : wen[7:0] = 8'b11000000;
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//Word
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6'b1100?? : wen[7:0] = 8'b00001111;
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6'b1101?? : wen[7:0] = 8'b11110000;
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//Double
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6'b111??? : wen[7:0] = 8'b11111111;
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default : wen[7:0] = 8'b00000000;
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endcase // casez ({write, datamode_in[1:0],addr_in[2:0]})
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//Single ported memory
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defparam mem.DW=2*DW;//TODO: really fixed to 64 bits
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defparam mem.AW=MAW;
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memory_sp mem(
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// Inputs
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.clk (clk),
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.en (en),
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.wen (wen[7:0]),
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.addr (addr[MAW-1:0]),
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.din (din[63:0]),
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.dout (dout[63:0])
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);
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//Outgoing transaction
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always @ (posedge clk or negedge nreset)
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if(!nreset)
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access_out <=1'b0;
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else if(~wait_in)
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access_out <= mem_rd;
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//Other emesh signals "dataload"
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always @ (posedge clk)
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if(mem_rd & ~wait_in)
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begin
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write_out <= 1'b1;
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hilo_sel <= dstaddr_in[2];
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datamode_out[1:0] <= datamode_in[1:0];
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ctrlmode_out[4:0] <= ctrlmode_in[3:0];
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dstaddr_out[AW-1:0] <= srcaddr_in[AW-1:0];
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end
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assign srcaddr_out[AW-1:0] = dout[63:32];
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//note sure about this???
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assign data_out[DW-1:0] = hilo_sel ? dout[63:32] :
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dout[31:0];
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//Concatenate
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emesh2packet #(.PW(PW))
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e2p (.packet_out (packet_out[PW-1:0]),
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.write_in (write_out),
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.datamode_in (datamode_out[1:0]),
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.ctrlmode_in (ctrlmode_out[3:0]),
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.dstaddr_in (dstaddr_out[AW-1:0]),
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.data_in (data_out[DW-1:0]),
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.srcaddr_in (srcaddr_out[AW-1:0])
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);
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//Write monitor
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emesh_monitor
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#(.PW(PW),
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.INDEX(1),
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.NAME(NAME)
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)
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emesh_monitor (.dut_access (access_in & write_in),
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.dut_packet (packet_in[PW-1:0]),
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.wait_in (1'b0),
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/*AUTOINST*/
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// Inputs
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.clk (clk),
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.nreset (nreset),
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.coreid (coreid[IDW-1:0]));
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endmodule // emesh_memory
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// Local Variables:
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// verilog-library-directories:("." "../dv" )
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// End:
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/*
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Copyright (C) 2015 Adapteva, Inc.
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Contributed by Andreas Olofsson <support@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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