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Register map twiddling..

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This commit is contained in:
Andreas Olofsson 2015-04-28 17:00:17 -04:00
parent d00d58d116
commit 3ef05ad63a
3 changed files with 34 additions and 36 deletions
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2
elink/hdl/elink.v
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@ -422,7 +422,7 @@ module elink(/*AUTOARG*/
) )
*/ */
defparam ecfg_base.GROUP=`EGROUP_CFG; defparam ecfg_base.GROUP=`EGROUP_TX;
ecfg_base ecfg_base( ecfg_base ecfg_base(
/*AUTOINST*/ /*AUTOINST*/
// Outputs // Outputs

57
elink/hdl/elink_regmap.v
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@ -8,36 +8,35 @@
//[1:0] = IGNORED (no byte access) //[1:0] = IGNORED (no byte access)
//Link register groups addr[19:16] //Link register groups addr[19:16]
`define EGROUP_CFG 4'hE `define EGROUP_CHIP 4'hF //reserved for chip MMR
`define EGROUP_TX 4'hD `define EGROUP_TX 4'hE
`define EGROUP_RX 4'hC `define EGROUP_RX 4'hD
`define EGROUP_READTAG 4'hB
//ELINK CONFIG REGISTERS
`define ELRESET 4'h0 //E0000-reset
`define ELCLK 4'h1 //E0004-clock configuration
`define ELCHIPID 4'h2 //E0008-Epiphany chip id for colid/rowid pins
`define ELVERSION 4'h3 //E000C-version
//ELINK TX registers //ELINK TX registers
`define ELTXCFG 4'h0 //D0000-config `define ELTXCFG 4'h0 //E0000-config
`define ELTXSTATUS 4'h1 //D0004-tx status `define ELTXSTATUS 4'h1 //E0004-tx status
`define ELTXGPIO 4'h2 //D0008-direct data for tx pins `define ELTXGPIO 4'h2 //E0008-direct data for tx pins
`define ELTXTEST 4'h3 //D000C-control for driving SERDES directly `define ELRESET 4'h3 //E000C-reset
`define ELTXDSTADDR 4'h5 //D0014-static addr (for testing) `define ELCLK 4'h4 //E0010-clock configuration
`define ELTXDATA 4'h4 //D0010-static data (for testing) `define ELCHIPID 4'h5 //E0014-Epiphany chip id for colid/rowid pins
`define ELTXSRCADDR 4'h6 //D0014-static source addr (for testing) `define ELVERSION 4'h6 //E0018-version #
`define ELTXTEST 4'h7 //E001C-control for driving SERDES directly
`define ELTXDSTADDR 4'h8 //E0020-static addr (for testing)
`define ELTXDATA 4'h9 //E0024-static data (for testing)
`define ELTXSRCADDR 4'hA //E0028-static source addr (for testing)
//ELINK RX registers //ELINK RX registers
`define ELRXCFG 4'h0 //C0000-config `define ELRXCFG 4'h0 //D0000-config
`define ELRXSTATUS 4'h1 //C0004-status register `define ELRXSTATUS 4'h1 //D0004-status register
`define ELRXGPIO 4'h2 //C0008-sampled data `define ELRXGPIO 4'h2 //D0008-sampled data
`define ELRXBASE 4'h3 //C000c-memory base for remap `define ELRXRR 4'h3 //D000C-read response address
`define EMAILBOXLO 4'h4 //C0010-mailbox `define ELRXBASE 4'h4 //D0010-memory base for remap
`define EMAILBOXHI 4'h5 //C0014-mailbox `define ELRESERVED 4'h5 //D0014-reserved
`define EDMACFG 4'h6 //C0018-dma `define EMAILBOXLO 4'h6 //D0018-mailbox
`define EDMASTATUS 4'h7 //C001C-dma `define EMAILBOXHI 4'h7 //D001c-mailbox
`define EDMASRC 4'h8 //C0020-dma `define EDMACFG 4'h8 //D0020-dma
`define EDMADST 4'h9 //C0024-dma `define EDMACOUNT 4'h9 //D0024-dma
`define EDMACOUNT 4'hA //C0028-dma `define EDMASTRIDE 4'hA //D0028-dma
`define EDMASRCADDR 4'hB //D002c-dma
`define EDMADSTADDR 4'hC //D0028-dma
`define EDMASTATUS 4'hD //D0030-dma

11
elink/hdl/erx.v
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@ -67,7 +67,6 @@ module erx (/*AUTOARG*/
wire [PW-1:0] emmu_packet; // From emmu of emmu.v wire [PW-1:0] emmu_packet; // From emmu of emmu.v
wire erx_access; // From erx_protocol of erx_protocol.v wire erx_access; // From erx_protocol of erx_protocol.v
wire [PW-1:0] erx_packet; // From erx_protocol of erx_protocol.v wire [PW-1:0] erx_packet; // From erx_protocol of erx_protocol.v
wire erx_rr; // From erx_protocol of erx_protocol.v
wire erx_wait; // From erx_disty of erx_disty.v wire erx_wait; // From erx_disty of erx_disty.v
wire [8:0] gpio_datain; // From erx_io of erx_io.v wire [8:0] gpio_datain; // From erx_io of erx_io.v
wire [DW-1:0] mi_rx_cfg_dout; // From ecfg_rx of ecfg_rx.v wire [DW-1:0] mi_rx_cfg_dout; // From ecfg_rx of ecfg_rx.v
@ -75,6 +74,7 @@ module erx (/*AUTOARG*/
wire [DW-1:0] mi_rx_emmu_dout; // From emmu of emmu.v wire [DW-1:0] mi_rx_emmu_dout; // From emmu of emmu.v
wire mmu_enable; // From ecfg_rx of ecfg_rx.v wire mmu_enable; // From ecfg_rx of ecfg_rx.v
wire [31:0] remap_base; // From ecfg_rx of ecfg_rx.v wire [31:0] remap_base; // From ecfg_rx of ecfg_rx.v
wire remap_bypass; // From erx_protocol of erx_protocol.v
wire [1:0] remap_mode; // From ecfg_rx of ecfg_rx.v wire [1:0] remap_mode; // From ecfg_rx of ecfg_rx.v
wire [11:0] remap_pattern; // From ecfg_rx of ecfg_rx.v wire [11:0] remap_pattern; // From ecfg_rx of ecfg_rx.v
wire [11:0] remap_sel; // From ecfg_rx of ecfg_rx.v wire [11:0] remap_sel; // From ecfg_rx of ecfg_rx.v
@ -343,7 +343,7 @@ module erx (/*AUTOARG*/
.emesh_clk (rx_lclk_div4), .emesh_clk (rx_lclk_div4),
.mi_dout (mi_rx_emmu_dout[DW-1:0]), .mi_dout (mi_rx_emmu_dout[DW-1:0]),
.emesh_packet_hi_out (), .emesh_packet_hi_out (),
.mmu_bp (erx_rr), .mmu_bp (remap_bypass),
.emesh_wait_in (erx_wait), .emesh_wait_in (erx_wait),
); );
*/ */
@ -360,7 +360,7 @@ module erx (/*AUTOARG*/
.reset (reset), .reset (reset),
.sys_clk (sys_clk), .sys_clk (sys_clk),
.mmu_en (mmu_enable), // Templated .mmu_en (mmu_enable), // Templated
.mmu_bp (erx_rr), // Templated .mmu_bp (remap_bypass), // Templated
.mi_en (mi_en), .mi_en (mi_en),
.mi_we (mi_we), .mi_we (mi_we),
.mi_addr (mi_addr[19:0]), .mi_addr (mi_addr[19:0]),
@ -383,7 +383,6 @@ module erx (/*AUTOARG*/
.clk (rx_lclk_div4), .clk (rx_lclk_div4),
.mi_dout (mi_rx_emmu_dout[DW-1:0]), .mi_dout (mi_rx_emmu_dout[DW-1:0]),
.emesh_packet_hi_out (), .emesh_packet_hi_out (),
.remap_bypass (erx_rr),
); );
*/ */
@ -401,7 +400,7 @@ module erx (/*AUTOARG*/
.remap_sel (remap_sel[11:0]), .remap_sel (remap_sel[11:0]),
.remap_pattern (remap_pattern[11:0]), .remap_pattern (remap_pattern[11:0]),
.remap_base (remap_base[31:0]), .remap_base (remap_base[31:0]),
.remap_bypass (erx_rr), // Templated .remap_bypass (remap_bypass),
.emesh_wait_in (erx_wait)); // Templated .emesh_wait_in (erx_wait)); // Templated
/**************************************************************/ /**************************************************************/
@ -413,7 +412,7 @@ module erx (/*AUTOARG*/
// Outputs // Outputs
.erx_access (erx_access), .erx_access (erx_access),
.erx_packet (erx_packet[PW-1:0]), .erx_packet (erx_packet[PW-1:0]),
.erx_rr (erx_rr), .remap_bypass (remap_bypass),
// Inputs // Inputs
.reset (reset), .reset (reset),
.rx_enable (rx_enable), .rx_enable (rx_enable),