Converting to synchronous reset

elink/hdl/ecfg_elink.v

@@ -98,7 +98,7 @@ module ecfg_elink (/*AUTOARG*/
    //###########################
    //# RESET REG
    //###########################
-    always @ (posedge clk or posedge reset)
+    always @ (posedge clk)
       if(reset)
 	ecfg_reset_reg <= 1'b0;         
       else if (ecfg_reset_write)
@@ -109,7 +109,7 @@ module ecfg_elink (/*AUTOARG*/
    //###########################
    //# CCLK/LCLK (PLL)
    //###########################
-    always @ (posedge clk or posedge reset)
+    always @ (posedge clk)
      if(reset)
        ecfg_clk_reg[15:0] <= 16'h573;//all clocks on at lowest speed   
      else if (ecfg_clk_write)
@@ -120,7 +120,7 @@ module ecfg_elink (/*AUTOARG*/
    //###########################
    //# CHIPID
    //###########################
-   always @ (posedge clk or posedge reset)
+   always @ (posedge clk)
      if(reset)
        ecfg_chipid_reg[11:0] <= DEFAULT_CHIPID;
      else if (ecfg_chipid_write)

elink/hdl/ecfg_if.v

@@ -135,7 +135,7 @@ module ecfg_if (/*AUTOARG*/
    //Access out packet  
    assign access_forward = (mi_rx_en | mi_rd);
 
-   always @ (posedge  clk or posedge reset)
+   always @ (posedge  clk)
      if(reset)
        access_out   <= 1'b0;
      else if(~wait_in)

elink/hdl/erx_cfg.v

@@ -78,7 +78,7 @@ module erx_cfg (/*AUTOARG*/
    //###########################
    //# RXCFG
    //###########################
-   always @ (posedge clk or posedge reset)
+   always @ (posedge clk)
      if(reset)
        ecfg_rx_reg[31:0] <= 'b0;
      else if (ecfg_rx_write)
@@ -100,7 +100,7 @@ module erx_cfg (/*AUTOARG*/
    //###########################1
    //# DEBUG
    //###########################   
-   always @ (posedge clk or posedge reset)
+   always @ (posedge clk)
      if(reset)
        ecfg_rx_status_reg[2:0] <= 'b0;   
      else

elink/hdl/erx_remap.v

@@ -70,7 +70,7 @@ module erx_remap (/*AUTOARG*/
 			     (remap_mode[1:0]==2'b01)    ? static_remap[31:0] :
 	  		                                   dynamic_remap[31:0];
       
-   always @ (posedge clk or posedge reset)
+   always @ (posedge clk)
      if (reset)
        begin
 	  emesh_access_out         <= 'b0;

elink/hdl/erx_timer.v

@@ -37,7 +37,7 @@ module erx_timer (/*AUTOARG*/
    assign timer_en = |(timer_cfg[1:0]);
    
   
-   always @ (posedge clk or posedge reset)
+   always @ (posedge clk)
      if(reset)
        begin
 	  do_count <=1'b0;	  

elink/hdl/etx_cfg.v

@@ -85,7 +85,7 @@ module etx_cfg (/*AUTOARG*/
    //###########################
    //# TX CONFIG
    //###########################
-   always @ (posedge clk or posedge reset)
+   always @ (posedge clk)
      if(reset)
        ecfg_tx_config_reg[10:0] <= 11'b0;
      else if (ecfg_tx_config_write)
@@ -101,7 +101,7 @@ module etx_cfg (/*AUTOARG*/
    //###########################
    //# STATUS REGISTER
    //###########################   
-   always @ (posedge clk or posedge reset)
+   always @ (posedge clk)
      if(reset)
        ecfg_tx_status_reg[2:0] <= 'd0;
      else

elink/hdl/etx_io.v

@@ -14,7 +14,7 @@ module etx_io (/*AUTOARG*/
    //###########
    //# reset, clocks
    //##########
-   input        reset;             //reset for io  
+   input        reset;               //reset for io  
    input 	tx_lclk;	     // fast clock for io
    input 	tx_lclk90;           // fast 90deg shifted lclk   
    input 	tx_lclk_div4;	     // slow clock for rest of logic   
@@ -61,7 +61,8 @@ module etx_io (/*AUTOARG*/
    wire [7:0] 	  txo_data;
    wire 	  txo_frame;   
    wire 	  txo_lclk90;
-   
+ 
+
    //#############################
    //# Disassemble packet (for clarity)
    //#############################  
@@ -77,7 +78,24 @@ module etx_io (/*AUTOARG*/
 		     // Inputs
 		     .packet_in		(tx_packet[PW-1:0]));
    
+   //#############################
+   //# RESET SYNCHRONIZER
+   //#############################  
+   reg 		  io_reset;
+   reg 		  io_reset_in;
    
+   always @ (posedge tx_lclk or posedge reset)
+     if(reset)
+       begin
+	  io_reset_in   <= 1'b1;
+	  io_reset      <= 1'b1;
+       end
+     else
+       begin
+	  io_reset_in  <= 1'b0;
+	  io_reset     <= io_reset_in; 
+       end
+      
    //#############################
    //# Transaction state machine
    //#############################  
@@ -95,7 +113,7 @@ module etx_io (/*AUTOARG*/
    //TODO: cleanup
    assign tx_io_wait = tx_access & ~tx_burst & ~tx_io_wait_reg;
       
-   always @ (posedge tx_lclk_div4 or posedge reset)
+   always @ (posedge tx_lclk_div4)
      if(reset)
        tx_io_wait_reg <= 1'b0;
      else	 
@@ -105,8 +123,8 @@ module etx_io (/*AUTOARG*/
    //# Frame Signal
    //#############################  
    
-   always @ (posedge tx_lclk or posedge reset)
-     if(reset)
+   always @ (posedge tx_lclk)
+     if(io_reset)
        tx_frame <= 1'b0;   
      else if(tx_pointer[0] & tx_access)
        tx_frame <= 1'b1;
@@ -166,7 +184,7 @@ module etx_io (/*AUTOARG*/
 	      .CE (1'b1),
 	      .D1 (tx_frame),
 	      .D2 (tx_frame),
-	      .R  (reset), //TODO: should this be buffered?
+	      .R  (io_reset), //TODO: should this be buffered?
 	      .S  (1'b0)
 	      );
    
@@ -178,7 +196,7 @@ module etx_io (/*AUTOARG*/
 	      .CE (1'b1),
 	      .D1 (1'b1),
 	      .D2 (1'b0),
-	      .R  (reset),//make TX clock quiet during reset
+	      .R  (io_reset),
 	      .S  (1'b0)
 	      );
 		  

elink/hdl/etx_protocol.v

@@ -75,7 +75,7 @@ module etx_protocol (/*AUTOARG*/
 			 );
    
    //Prepare transaction / with burst
-   always @ (posedge clk or posedge reset)
+   always @ (posedge clk)
      if(reset)
        begin
 	  tx_packet[PW-1:0] <= 'b0;