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Removing write decode from wait pushback
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@ -126,15 +126,18 @@ module etx_arbiter (/*AUTOARG*/
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//######################################################################
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//######################################################################
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//Write waits on pin wr wait or cfg_wait
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//Write waits on pin wr wait or cfg_wait
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assign txwr_wait = etx_wr_wait |
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assign txwr_wait = etx_wr_wait |
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etx_rd_wait |
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etx_cfg_wait;
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etx_cfg_wait;
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//Host read request (self throttling, one read at a time)
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//Host read request (self throttling, one read at a time)
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assign txrd_wait = etx_rd_wait |
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assign txrd_wait = etx_rd_wait |
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etx_wr_wait |
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etx_cfg_wait |
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etx_cfg_wait |
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txrd_arb_wait;
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txrd_arb_wait;
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//Read response
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//Read response
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assign txrr_wait = etx_wr_wait |
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assign txrr_wait = etx_wr_wait |
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etx_rd_wait |
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etx_cfg_wait |
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etx_cfg_wait |
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txrr_arb_wait;
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txrr_arb_wait;
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@ -162,15 +165,17 @@ module etx_arbiter (/*AUTOARG*/
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etx_access <= 1'b0;
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etx_access <= 1'b0;
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etx_rr <= 1'b0;
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etx_rr <= 1'b0;
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end
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end
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else if (access_in & (write_in & ~etx_wr_wait) | (~write_in & ~etx_rd_wait))
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else if (~(etx_wr_wait | etx_rd_wait))
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begin
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begin
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etx_access <= access_in;
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etx_access <= access_in;
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etx_rr <= txrr_grant;
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etx_rr <= txrr_grant;
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end
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end
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//packet
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//packet
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always @ (posedge clk)
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always @ (posedge clk)
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if (access_in & (write_in & ~etx_wr_wait) | (~write_in & ~etx_rd_wait))
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if (access_in & ~(etx_wr_wait | etx_rd_wait))
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etx_packet[PW-1:0] <= etx_mux[PW-1:0];
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etx_packet[PW-1:0] <= etx_mux[PW-1:0];
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endmodule // etx_arbiter
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endmodule // etx_arbiter
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