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New Vivado-friendly modules, testbench for elink gold-vs-new.

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Fred Huettig 2014-11-19 12:02:18 -05:00
parent 0ba677883d
commit 440d932794
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axi/hdl/axi_elink_if.v
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/*
File: axi_elink_if.v
This file is part of the Parallella FPGA Reference Design.
Copyright (C) 2013 Adapteva, Inc.
Contributed by Roman Trogan <support@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module axi_elink_if (/*AUTOARG*/
// Outputs
reset_chip, reset_fpga, emaxi_access_outb, emaxi_write_outb,
emaxi_datamode_outb, emaxi_ctrlmode_outb, emaxi_dstaddr_outb,
emaxi_srcaddr_outb, emaxi_data_outb, emaxi_wr_wait_outb,
esaxi_access_outb, esaxi_write_outb, esaxi_datamode_outb,
esaxi_ctrlmode_outb, esaxi_dstaddr_outb, esaxi_srcaddr_outb,
esaxi_data_outb, esaxi_wr_wait_outb, esaxi_rd_wait_outb,
elink_access_outb, elink_write_outb, elink_datamode_outb,
elink_ctrlmode_outb, elink_dstaddr_outb, elink_srcaddr_outb,
elink_data_outb, elink_wr_wait_outb, elink_rd_wait_outb,
elink_disable, elink_cclk_enb, elink_clk_div,
// Inputs
eclk, aclk, reset, emaxi_access_inb, emaxi_write_inb,
emaxi_datamode_inb, emaxi_ctrlmode_inb, emaxi_dstaddr_inb,
emaxi_srcaddr_inb, emaxi_data_inb, emaxi_wr_wait_inb,
emaxi_rd_wait_inb, esaxi_access_inb, esaxi_write_inb,
esaxi_datamode_inb, esaxi_ctrlmode_inb, esaxi_dstaddr_inb,
esaxi_srcaddr_inb, esaxi_data_inb, esaxi_wr_wait_inb,
esaxi_rd_wait_inb, elink_access_inb, elink_write_inb,
elink_datamode_inb, elink_ctrlmode_inb, elink_dstaddr_inb,
elink_srcaddr_inb, elink_data_inb, elink_wr_wait_inb,
elink_rd_wait_inb
);
//#########
//# Inputs
//#########
input eclk;
input aclk;
input reset;
//##############################
//# From axi_master
//##############################
input emaxi_access_inb;
input emaxi_write_inb;
input [1:0] emaxi_datamode_inb;
input [3:0] emaxi_ctrlmode_inb;
input [31:0] emaxi_dstaddr_inb;
input [31:0] emaxi_srcaddr_inb;
input [31:0] emaxi_data_inb;
input emaxi_wr_wait_inb;
input emaxi_rd_wait_inb;
//##############################
//# From axi_slave
//##############################
input esaxi_access_inb;
input esaxi_write_inb;
input [1:0] esaxi_datamode_inb;
input [3:0] esaxi_ctrlmode_inb;
input [31:0] esaxi_dstaddr_inb;
input [31:0] esaxi_srcaddr_inb;
input [31:0] esaxi_data_inb;
input esaxi_wr_wait_inb;
input esaxi_rd_wait_inb;
//##############################
//# From elink
//##############################
input elink_access_inb;
input elink_write_inb;
input [1:0] elink_datamode_inb;
input [3:0] elink_ctrlmode_inb;
input [31:0] elink_dstaddr_inb;
input [31:0] elink_srcaddr_inb;
input [31:0] elink_data_inb;
input elink_wr_wait_inb;
input elink_rd_wait_inb;
//##########
//# Outputs
//##########
output reset_chip;
output reset_fpga;
//##############################
//# To axi_master
//##############################
output emaxi_access_outb;
output emaxi_write_outb;
output [1:0] emaxi_datamode_outb;
output [3:0] emaxi_ctrlmode_outb;
output [31:0] emaxi_dstaddr_outb;
output [31:0] emaxi_srcaddr_outb;
output [31:0] emaxi_data_outb;
output emaxi_wr_wait_outb;
//##############################
//# To axi_slave
//##############################
output esaxi_access_outb;
output esaxi_write_outb;
output [1:0] esaxi_datamode_outb;
output [3:0] esaxi_ctrlmode_outb;
output [31:0] esaxi_dstaddr_outb;
output [31:0] esaxi_srcaddr_outb;
output [31:0] esaxi_data_outb;
output esaxi_wr_wait_outb;
output esaxi_rd_wait_outb;
//##############################
//# To elink
//##############################
output elink_access_outb;
output elink_write_outb;
output [1:0] elink_datamode_outb;
output [3:0] elink_ctrlmode_outb;
output [31:0] elink_dstaddr_outb;
output [31:0] elink_srcaddr_outb;
output [31:0] elink_data_outb;
output elink_wr_wait_outb;
output elink_rd_wait_outb;
// controls
output elink_disable;
output elink_cclk_enb;
output [1:0] elink_clk_div;
/*AUTOINPUT*/
/*AUTOWIRE*/
//#########
//# Regs
//#########
reg esaxi_access_en;
//#########
//# Wires
//#########
wire emaxi_sel;
wire route_to_slave;
wire axi_access_in;
wire axi_write_in;
wire [1:0] axi_datamode_in;
wire [3:0] axi_ctrlmode_in;
wire [31:0] axi_dstaddr_in;
wire [31:0] axi_srcaddr_in;
wire [31:0] axi_data_in;
wire axi_wr_wait_in;
wire axi_rd_wait_in;
wire axi_access_out;
wire axi_write_out;
wire [1:0] axi_datamode_out;
wire [3:0] axi_ctrlmode_out;
wire [31:0] axi_dstaddr_out;
wire [31:0] axi_srcaddr_out;
wire [31:0] axi_data_out;
wire axi_wr_wait_out;
wire axi_rd_wait_out;
//###################################
//# FPGACFG Instantiation
//###################################
/*fpgacfg AUTO_TEMPLATE (.elink_\(.*\)_in (elink_\1_inb[]),
.elink_\(.*\)_out (elink_\1_outb[]),
.axi_\(.*\)_in (axi_\1_in[]),
.axi_\(.*\)_out (axi_\1_out[]),
);
*/
fpgacfg fpgacfg
(/*AUTOINST*/
// Outputs
.reset_chip (reset_chip),
.reset_fpga (reset_fpga),
.elink_access_out (elink_access_outb), // Templated
.elink_write_out (elink_write_outb), // Templated
.elink_datamode_out (elink_datamode_outb[1:0]), // Templated
.elink_ctrlmode_out (elink_ctrlmode_outb[3:0]), // Templated
.elink_dstaddr_out (elink_dstaddr_outb[31:0]), // Templated
.elink_srcaddr_out (elink_srcaddr_outb[31:0]), // Templated
.elink_data_out (elink_data_outb[31:0]), // Templated
.elink_wr_wait_out (elink_wr_wait_outb), // Templated
.elink_rd_wait_out (elink_rd_wait_outb), // Templated
.elink_disable (elink_disable),
.elink_cclk_enb (elink_cclk_enb),
.elink_clk_div (elink_clk_div[1:0]),
.axi_access_out (axi_access_out), // Templated
.axi_write_out (axi_write_out), // Templated
.axi_datamode_out (axi_datamode_out[1:0]), // Templated
.axi_ctrlmode_out (axi_ctrlmode_out[3:0]), // Templated
.axi_dstaddr_out (axi_dstaddr_out[31:0]), // Templated
.axi_srcaddr_out (axi_srcaddr_out[31:0]), // Templated
.axi_data_out (axi_data_out[31:0]), // Templated
.axi_wr_wait_out (axi_wr_wait_out), // Templated
.axi_rd_wait_out (axi_rd_wait_out), // Templated
// Inputs
.eclk (eclk),
.aclk (aclk),
.reset (reset),
.elink_access_in (elink_access_inb), // Templated
.elink_write_in (elink_write_inb), // Templated
.elink_datamode_in (elink_datamode_inb[1:0]), // Templated
.elink_ctrlmode_in (elink_ctrlmode_inb[3:0]), // Templated
.elink_dstaddr_in (elink_dstaddr_inb[31:0]), // Templated
.elink_srcaddr_in (elink_srcaddr_inb[31:0]), // Templated
.elink_data_in (elink_data_inb[31:0]), // Templated
.elink_wr_wait_in (elink_wr_wait_inb), // Templated
.elink_rd_wait_in (elink_rd_wait_inb), // Templated
.axi_access_in (axi_access_in), // Templated
.axi_write_in (axi_write_in), // Templated
.axi_datamode_in (axi_datamode_in[1:0]), // Templated
.axi_ctrlmode_in (axi_ctrlmode_in[3:0]), // Templated
.axi_dstaddr_in (axi_dstaddr_in[31:0]), // Templated
.axi_srcaddr_in (axi_srcaddr_in[31:0]), // Templated
.axi_data_in (axi_data_in[31:0]), // Templated
.axi_wr_wait_in (axi_wr_wait_in), // Templated
.axi_rd_wait_in (axi_rd_wait_in)); // Templated
//####################################
//# Transactions from- AXI to- ELINK
//####################################
//# arbitration
always @ (posedge eclk or posedge reset)
if(reset)
esaxi_access_en <= 1'b0;
else
esaxi_access_en <= ~esaxi_access_en;
assign esaxi_wr_wait_outb = emaxi_access_inb & ~esaxi_access_en |
axi_wr_wait_out;
assign esaxi_rd_wait_outb = emaxi_access_inb & ~esaxi_access_en |
axi_rd_wait_out;
assign emaxi_wr_wait_outb = esaxi_access_inb & esaxi_access_en |
axi_wr_wait_out;
assign emaxi_sel = emaxi_access_inb & ~emaxi_wr_wait_outb;
//# selection mux
assign axi_access_in = emaxi_access_inb | esaxi_access_inb;
assign axi_write_in = emaxi_sel ? emaxi_write_inb :
esaxi_write_inb;
assign axi_datamode_in[1:0] = emaxi_sel ? emaxi_datamode_inb[1:0]:
esaxi_datamode_inb[1:0];
assign axi_ctrlmode_in[3:0] = emaxi_sel ? emaxi_ctrlmode_inb[3:0]:
esaxi_ctrlmode_inb[3:0];
assign axi_dstaddr_in[31:0] = emaxi_sel ? emaxi_dstaddr_inb[31:0]:
esaxi_dstaddr_inb[31:0];
assign axi_srcaddr_in[31:0] = emaxi_sel ? emaxi_srcaddr_inb[31:0]:
esaxi_srcaddr_inb[31:0];
assign axi_data_in[31:0] = emaxi_sel ? emaxi_data_inb[31:0]:
esaxi_data_inb[31:0];
//####################################
//# Transactions from- ELINK to- AXI
//####################################
//# AXI Slave port has a predefined read source address of `AXI_COORD
assign route_to_slave = (axi_dstaddr_out[31:20] == `AXI_COORD);
assign esaxi_access_outb = axi_access_out & route_to_slave;
assign emaxi_access_outb = axi_access_out & ~route_to_slave;
assign esaxi_write_outb = axi_write_out;
assign esaxi_datamode_outb[1:0] = axi_datamode_out[1:0];
assign esaxi_ctrlmode_outb[3:0] = axi_ctrlmode_out[3:0];
assign esaxi_dstaddr_outb[31:0] = axi_dstaddr_out[31:0];
assign esaxi_srcaddr_outb[31:0] = axi_srcaddr_out[31:0];
assign esaxi_data_outb[31:0] = axi_data_out[31:0];
assign emaxi_write_outb = axi_write_out;
assign emaxi_datamode_outb[1:0] = axi_datamode_out[1:0];
assign emaxi_ctrlmode_outb[3:0] = axi_ctrlmode_out[3:0];
assign emaxi_dstaddr_outb[31:0] = axi_dstaddr_out[31:0];
assign emaxi_srcaddr_outb[31:0] = axi_srcaddr_out[31:0];
assign emaxi_data_outb[31:0] = axi_data_out[31:0];
assign axi_wr_wait_in = route_to_slave & esaxi_wr_wait_inb |
~route_to_slave & emaxi_wr_wait_inb;
assign axi_rd_wait_in = route_to_slave & esaxi_rd_wait_inb |
~route_to_slave & emaxi_rd_wait_inb;
endmodule // axi_elink_if
// Local Variables:
// verilog-library-directories:("." "../elink" "../parallella-I")
// End:

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axi/hdl/axi_master.v
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/*
File: axi_master.v
This file is part of the Parallella FPGA Reference Design.
Copyright (C) 2013 Adapteva, Inc.
Contributed by Roman Trogan <support@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module axi_master (/*AUTOARG*/
// Outputs
awid, awaddr, awlen, awsize, awburst, awlock, awcache, awprot,
awvalid, wid, wdata, wstrb, wlast, wvalid, bready, arid, araddr,
arlen, arsize, arburst, arlock, arcache, arprot, arvalid, rready,
emesh_access_inb, emesh_write_inb, emesh_datamode_inb,
emesh_ctrlmode_inb, emesh_dstaddr_inb, emesh_srcaddr_inb,
emesh_data_inb, emesh_wr_wait_inb, emesh_rd_wait_inb, awqos, arqos,
// Inputs
aclk, eclk, reset, awready, wready, bid, bresp, bvalid, arready,
rid, rdata, rresp, rlast, rvalid, emesh_access_outb,
emesh_write_outb, emesh_datamode_outb, emesh_ctrlmode_outb,
emesh_dstaddr_outb, emesh_srcaddr_outb, emesh_data_outb,
emesh_wr_wait_outb
);
parameter MIDW = 6; //ID Width
parameter MAW = 32; //Address Bus Width
parameter MDW = 64; //Data Bus Width
parameter STW = 8; //Number of strobes
//#########
//# Inputs
//#########
// global signals
input aclk; // clock source of the axi bus
input eclk; // clock source of emesh interface
input reset; // reset
//########################
//# Write address channel
//########################
input awready; //write address ready
//########################
//# Write data channel
//########################
input wready; //write ready
//#########################
//# Write response channel
//#########################
input [MIDW-1:0] bid; //response ID tag
input [1:0] bresp; //write response
input bvalid;//write response valid
//########################
//# Read address channel
//########################
input arready;//read address ready
//########################
//# Read data channel
//########################
input [MIDW-1:0] rid; //read ID tag
input [MDW-1:0] rdata; //read data
input [1:0] rresp; //read response
input rlast; //read last, indicates the last transfer in burst
input rvalid;//read valid
//##############################
//# From the emesh interface
//##############################
input emesh_access_outb;
input emesh_write_outb;
input [1:0] emesh_datamode_outb;
input [3:0] emesh_ctrlmode_outb;
input [31:0] emesh_dstaddr_outb;
input [31:0] emesh_srcaddr_outb;
input [31:0] emesh_data_outb;
input emesh_wr_wait_outb;
//##########
//# Outputs
//##########
//########################
//# Write address channel
//########################
output [MIDW-1:0] awid; //write address ID
output [MAW-1:0] awaddr; //write address
output [3:0] awlen; //burst lenght (the number of data transfers)
output [2:0] awsize; //burst size (the size of each transfer)
output [1:0] awburst; //burst type
output [1:0] awlock; //lock type (atomic characteristics)
output [3:0] awcache; //memory type
output [2:0] awprot; //protection type
output awvalid; //write address valid
//########################
//# Write data channel
//########################
output [MIDW-1:0] wid; //write ID tag (supported only in AXI3)
output [MDW-1:0] wdata; //write data
output [STW-1:0] wstrb; //write strobes
output wlast; //write last, indicates the last transfer in burst
output wvalid;//write valid
//########################
// Write response channel
//########################
output bready;//response ready
//########################
//# Read address channel
//########################
output [MIDW-1:0] arid; //read address ID
output [MAW-1:0] araddr; //read address
output [3:0] arlen; //burst lenght (the number of data transfers)
output [2:0] arsize; //burst size (the size of each transfer)
output [1:0] arburst; //burst type
output [1:0] arlock; //lock type (atomic characteristics)
output [3:0] arcache; //memory type
output [2:0] arprot; //protection type
output arvalid; //write address valid
//########################
//# Read data channel
//########################
output rready; //read ready
//##############################
//# To the emesh interface
//##############################
output emesh_access_inb;
output emesh_write_inb;
output [1:0] emesh_datamode_inb;
output [3:0] emesh_ctrlmode_inb;
output [31:0] emesh_dstaddr_inb;
output [31:0] emesh_srcaddr_inb;
output [31:0] emesh_data_inb;
output emesh_wr_wait_inb;
output emesh_rd_wait_inb;
//#######################################################################
//# The following features are not supported (AXI4 only)
//# If un-commented, those signals have to be driven with default values
//#######################################################################
// input buser; //user signal (AXI4 only)
// input ruser; //user signal (AXI4 only)
output [3:0] awqos; //quality of service (AXI4 only) default 4'b0000
// output [3:0] awregion;//region identifier (AXI4 only)
// output awuser; //user signal (AXI4 only)
// output wuser; //user signal (AXI4 only)
output [3:0] arqos; //quality of service (AXI4 only) default 4'b0000
// output [3:0] arregion;//region identifier (AXI4 only)
// output aruser; //user signal (AXI4 only)
/*AUTOINPUT*/
/*AUTOWIRE*/
//############
//# Wires
//############
wire [MIDW-1:0] awid; //write address ID
wire [MAW-1:0] awaddr; //write address
wire [3:0] awlen; //burst lenght (the number of data transfers)
wire [2:0] awsize; //burst size (the size of each transfer)
wire [1:0] awburst; //burst type
wire [1:0] awlock; //lock type (atomic characteristics)
wire [3:0] awcache; //memory type
wire [2:0] awprot; //protection type
wire awvalid; //write address valid
wire [MIDW-1:0] wid; //write ID tag (supported only in AXI3)
wire [MDW-1:0] wdata; //write data
wire [STW-1:0] wstrb; //write strobes
wire wlast; //write last, indicates the last transfer in burst
wire wvalid; //write valid
wire bready; //response ready
wire [MIDW-1:0] arid; //read address ID
wire [MAW-1:0] araddr; //read address
wire [3:0] arlen; //burst lenght (the number of data transfers)
wire [2:0] arsize; //burst size (the size of each transfer)
wire [1:0] arburst; //burst type
wire [1:0] arlock; //lock type (atomic characteristics)
wire [3:0] arcache; //memory type
wire [2:0] arprot; //protection type
wire arvalid; //write address valid
wire rready; //read ready
wire emesh_access_inb;
wire emesh_write_inb;
wire [1:0] emesh_datamode_inb;
wire [3:0] emesh_ctrlmode_inb;
wire [31:0] emesh_dstaddr_inb;
wire [31:0] emesh_srcaddr_inb;
wire [31:0] emesh_data_inb;
wire emesh_wr_wait_inb;
wire emesh_rd_wait_inb;
//#######################
//# Defaults
//#######################
assign awqos[3:0] = 4'b0000;
assign arqos[3:0] = 4'b0000;
//##################################
//# Master Write Port Instantiation
//##################################
axi_master_wr axi_master_wr(/*AUTOINST*/
// Outputs
.awid (awid[MIDW-1:0]),
.awaddr (awaddr[MAW-1:0]),
.awlen (awlen[3:0]),
.awsize (awsize[2:0]),
.awburst (awburst[1:0]),
.awlock (awlock[1:0]),
.awcache (awcache[3:0]),
.awprot (awprot[2:0]),
.awvalid (awvalid),
.wid (wid[MIDW-1:0]),
.wdata (wdata[MDW-1:0]),
.wstrb (wstrb[STW-1:0]),
.wlast (wlast),
.wvalid (wvalid),
.bready (bready),
.emesh_wr_wait_inb(emesh_wr_wait_inb),
// Inputs
.aclk (aclk),
.eclk (eclk),
.reset (reset),
.awready (awready),
.wready (wready),
.bid (bid[MIDW-1:0]),
.bresp (bresp[1:0]),
.bvalid (bvalid),
.emesh_access_outb(emesh_access_outb),
.emesh_write_outb(emesh_write_outb),
.emesh_datamode_outb(emesh_datamode_outb[1:0]),
.emesh_ctrlmode_outb(emesh_ctrlmode_outb[3:0]),
.emesh_dstaddr_outb(emesh_dstaddr_outb[31:0]),
.emesh_srcaddr_outb(emesh_srcaddr_outb[31:0]),
.emesh_data_outb (emesh_data_outb[31:0]));
//##################################
//# Master Read Port Instantiation
//##################################
axi_master_rd axi_master_rd(/*AUTOINST*/
// Outputs
.arid (arid[MIDW-1:0]),
.araddr (araddr[MAW-1:0]),
.arlen (arlen[3:0]),
.arsize (arsize[2:0]),
.arburst (arburst[1:0]),
.arlock (arlock[1:0]),
.arcache (arcache[3:0]),
.arprot (arprot[2:0]),
.arvalid (arvalid),
.rready (rready),
.emesh_access_inb(emesh_access_inb),
.emesh_write_inb (emesh_write_inb),
.emesh_datamode_inb(emesh_datamode_inb[1:0]),
.emesh_ctrlmode_inb(emesh_ctrlmode_inb[3:0]),
.emesh_dstaddr_inb(emesh_dstaddr_inb[31:0]),
.emesh_srcaddr_inb(emesh_srcaddr_inb[31:0]),
.emesh_data_inb (emesh_data_inb[31:0]),
.emesh_rd_wait_inb(emesh_rd_wait_inb),
// Inputs
.aclk (aclk),
.eclk (eclk),
.reset (reset),
.arready (arready),
.rid (rid[MIDW-1:0]),
.rdata (rdata[MDW-1:0]),
.rresp (rresp[1:0]),
.rlast (rlast),
.rvalid (rvalid),
.emesh_access_outb(emesh_access_outb),
.emesh_write_outb(emesh_write_outb),
.emesh_datamode_outb(emesh_datamode_outb[1:0]),
.emesh_ctrlmode_outb(emesh_ctrlmode_outb[3:0]),
.emesh_dstaddr_outb(emesh_dstaddr_outb[31:0]),
.emesh_srcaddr_outb(emesh_srcaddr_outb[31:0]),
.emesh_data_outb (emesh_data_outb[31:0]),
.emesh_wr_wait_outb(emesh_wr_wait_outb));
endmodule // axi_master

422
axi/hdl/axi_master_rd.v
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@ -1,422 +0,0 @@
/*
File: axi_master_rd.v
This file is part of the Parallella FPGA Reference Design.
Copyright (C) 2013 Adapteva, Inc.
Contributed by Roman Trogan <support@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module axi_master_rd (/*AUTOARG*/
// Outputs
arid, araddr, arlen, arsize, arburst, arlock, arcache, arprot,
arvalid, rready, emesh_access_inb, emesh_write_inb,
emesh_datamode_inb, emesh_ctrlmode_inb, emesh_dstaddr_inb,
emesh_srcaddr_inb, emesh_data_inb, emesh_rd_wait_inb,
// Inputs
aclk, eclk, reset, arready, rid, rdata, rresp, rlast, rvalid,
emesh_access_outb, emesh_write_outb, emesh_datamode_outb,
emesh_ctrlmode_outb, emesh_dstaddr_outb, emesh_srcaddr_outb,
emesh_data_outb, emesh_wr_wait_outb
);
parameter MIDW = 6; //ID Width
parameter MAW = 32; //Address Bus Width
parameter MDW = 64; //Data Bus Width
parameter ACH = MAW+2; //Width of all used Read Address Signals
parameter AFW = 4; //Address channel FIFO address width
parameter DFW = 4; //Data channel FIFO address width
parameter DCH = MDW; //Width of all used Read Data Signals
parameter WB = MAW+9; //Width of all used Write Back Address Signals
parameter BFW = 4; //Write Backl FIFO address width
//#########
//# Inputs
//#########
// global signals
input aclk; // clock source of the axi bus
input eclk; // clock source of emesh interface
input reset; // reset
//########################
//# Read address channel
//########################
input arready;//read address ready
//########################
//# Read data channel
//########################
input [MIDW-1:0] rid; //read ID tag
input [MDW-1:0] rdata; //read data
input [1:0] rresp; //read response
input rlast; //read last, indicates the last transfer in burst
input rvalid;//read valid
//##############################
//# From the emesh interface
//##############################
input emesh_access_outb;
input emesh_write_outb;
input [1:0] emesh_datamode_outb;
input [3:0] emesh_ctrlmode_outb;
input [31:0] emesh_dstaddr_outb;
input [31:0] emesh_srcaddr_outb;
input [31:0] emesh_data_outb;
input emesh_wr_wait_outb;
//##########
//# Outputs
//##########
//########################
//# Read address channel
//########################
output [MIDW-1:0] arid; //read address ID
output [MAW-1:0] araddr; //read address
output [3:0] arlen; //burst lenght (the number of data transfers)
output [2:0] arsize; //burst size (the size of each transfer)
output [1:0] arburst; //burst type
output [1:0] arlock; //lock type (atomic characteristics)
output [3:0] arcache; //memory type
output [2:0] arprot; //protection type
output arvalid; //write address valid
//########################
//# Read data channel
//########################
output rready; //read ready
//##############################
//# To the emesh interface
//##############################
output emesh_access_inb;
output emesh_write_inb;
output [1:0] emesh_datamode_inb;
output [3:0] emesh_ctrlmode_inb;
output [31:0] emesh_dstaddr_inb;
output [31:0] emesh_srcaddr_inb;
output [31:0] emesh_data_inb;
output emesh_rd_wait_inb;
/*AUTOINPUT*/
/*AUTOWIRE*/
//#########
//# Regs
//#########
reg [33:0] dstaddr_reg;
reg [31:0] srcaddr_reg;
reg [3:0] ctrlmode_reg;
reg emesh_rd_access_reg;
reg ach_fifo_empty_reg;
reg [ACH-1:0] ach_fifo_reg;
reg [WB-1:0] wb_fifo_reg;
reg [WB-1:0] tran_addr_mode;
reg [DCH-1:0] dch_fifo_in;
reg rvalid_rready_reg;
reg [DCH-1:0] dch_fifo_reg;
reg [MDW-1:0] algn_byte;
reg [MDW-1:0] algn_hword;
reg [MDW-1:0] wdata_algn_reg;
reg tran_go;
reg tran_go_reg;
//#########
//# Wires
//#########
wire emesh_rd_access;
wire [ACH-1:0] ach_fifo_in;
wire ach_fifo_wr;
wire ach_fifo_rd;
wire ach_fifo_empty;
wire ach_fifo_full;
wire arvalid_arready;
wire ach_advance;
wire [ACH-1:0] ach_fifo_out;
wire [WB-1:0] wb_fifo_in;
wire [WB-1:0] wb_fifo_out;
wire wb_fifo_wr;
wire wb_fifo_rd;
wire wb_fifo_empty;
wire wb_fifo_full;
wire [DCH-1:0] dch_data_in;
wire dch_fifo_wr;
wire dch_fifo_rd;
wire [DCH-1:0] dch_fifo_out;
wire dch_fifo_empty;
wire dch_fifo_full;
wire rvalid_rready;
wire [2:0] dalgn_ctrl;
wire [MDW-1:0] algn_word;
wire [1:0] tran_mode;
wire byte_tran;
wire hword_tran;
wire word_tran;
wire [MDW-1:0] wdata_algn;
//# Incoming transaction should be sampled to prevent timing issues
assign emesh_rd_wait_inb = ach_fifo_full | wb_fifo_full;
assign emesh_rd_access = emesh_access_outb & ~emesh_write_outb &
~emesh_rd_wait_inb;
always @ (posedge eclk)
if (emesh_rd_access)
dstaddr_reg[33:0] <= {emesh_dstaddr_outb[31:0],emesh_datamode_outb[1:0]};
always @ (posedge eclk)
if (emesh_rd_access)
srcaddr_reg[31:0] <= emesh_srcaddr_outb[31:0];
always @ (posedge eclk)
if (emesh_rd_access)
ctrlmode_reg[3:0] <= emesh_ctrlmode_outb[3:0];
always @ (posedge eclk or posedge reset)
if(reset)
emesh_rd_access_reg <= 1'b0;
else if(~emesh_rd_wait_inb)
emesh_rd_access_reg <= emesh_rd_access;
//############################################
//# AXI Address channel synchronization FIFO
//############################################
assign ach_fifo_in[ACH-1:0] = dstaddr_reg[33:0];
assign ach_fifo_wr = emesh_rd_access_reg & ~emesh_rd_wait_inb;
assign ach_fifo_rd = ~ach_fifo_empty & (~arvalid | arvalid_arready);
assign ach_advance = arvalid_arready | ~arvalid;
/*fifo AUTO_TEMPLATE(.rd_clk (aclk),
.wr_clk (eclk),
.wr_data (ach_fifo_in[ACH-1:0]),
.rd_data (ach_fifo_out[ACH-1:0]),
.rd_fifo_empty (ach_fifo_empty),
.wr_fifo_full (ach_fifo_full),
.wr_write (ach_fifo_wr),
.rd_read (ach_fifo_rd),
);
*/
fifo #(.DW(ACH), .AW(AFW)) fifo_ach(/*AUTOINST*/
// Outputs
.rd_data (ach_fifo_out[ACH-1:0]), // Templated
.rd_fifo_empty (ach_fifo_empty), // Templated
.wr_fifo_full (ach_fifo_full), // Templated
// Inputs
.reset (reset),
.wr_clk (eclk), // Templated
.rd_clk (aclk), // Templated
.wr_write (ach_fifo_wr), // Templated
.wr_data (ach_fifo_in[ACH-1:0]), // Templated
.rd_read (ach_fifo_rd)); // Templated
//# The data is sampled after exiting FIFO to prevent timing issues
always @ (posedge aclk or posedge reset)
if(reset)
ach_fifo_empty_reg <= 1'b1;
else if(ach_advance)
ach_fifo_empty_reg <= ach_fifo_empty;
always @ (posedge aclk)
if (ach_advance)
ach_fifo_reg[ACH-1:0] <= ach_fifo_out[ACH-1:0];
assign arid[MIDW-1:0] = {(MIDW){1'b0}};
assign araddr[MAW-1:0] = ach_fifo_reg[ACH-1:2];
assign arlen[3:0] = 4'b0000;
assign arsize[2:0] = {1'b0,ach_fifo_reg[1:0]};
assign arburst[1:0] = 2'b01;
assign arlock[1:0] = 2'b00;
assign arcache[3:0] = 4'b0000;
assign arprot[2:0] = 3'b000; //unprivileged, secured
assign arvalid = ~ach_fifo_empty_reg;
assign arvalid_arready = arvalid & arready;
//############################################
//# Address FIFO of the returning transaction
//############################################
assign wb_fifo_in[WB-1:0] = {ctrlmode_reg[3:0],srcaddr_reg[31:0],dstaddr_reg[4:0]};
assign wb_fifo_wr = emesh_rd_access_reg & ~emesh_rd_wait_inb;
assign wb_fifo_rd = dch_fifo_rd;
/*fifo AUTO_TEMPLATE(.rd_clk (eclk),
.wr_clk (eclk),
.wr_data (wb_fifo_in[WB-1:0]),
.rd_data (wb_fifo_out[WB-1:0]),
.rd_fifo_empty (wb_fifo_empty),
.wr_fifo_full (wb_fifo_full),
.wr_write (wb_fifo_wr),
.rd_read (wb_fifo_rd),
);
*/
fifo #(.DW(WB), .AW(BFW)) fifo_wb(/*AUTOINST*/
// Outputs
.rd_data (wb_fifo_out[WB-1:0]), // Templated
.rd_fifo_empty (wb_fifo_empty), // Templated
.wr_fifo_full (wb_fifo_full), // Templated
// Inputs
.reset (reset),
.wr_clk (eclk), // Templated
.rd_clk (eclk), // Templated
.wr_write (wb_fifo_wr), // Templated
.wr_data (wb_fifo_in[WB-1:0]), // Templated
.rd_read (wb_fifo_rd)); // Templated
//# The data is sampled after exiting FIFO to prevent timing issues
always @ (posedge eclk)
if(~emesh_wr_wait_outb)
wb_fifo_reg[WB-1:0] <= wb_fifo_out[WB-1:0];
//# To synchronize the address with the data
always @ (posedge eclk)
if(tran_go & ~emesh_wr_wait_outb)
tran_addr_mode[WB-1:0] <= wb_fifo_reg[WB-1:0];
//#######################################
//# AXI Data channel synchronization FIFO
//#######################################
assign rready = ~dch_fifo_full;
assign rvalid_rready = rvalid & rready;
assign dch_data_in[DCH-1:0] = rdata[MDW-1:0];
assign dch_fifo_wr = rvalid_rready_reg & ~dch_fifo_full;
assign dch_fifo_rd = ~(dch_fifo_empty | emesh_wr_wait_outb);
//# The data is sampled before entering FIFO to prevent timing issues
always @ (posedge aclk)
if(~dch_fifo_full)
dch_fifo_in[DCH-1:0] <= dch_data_in[DCH-1:0];
always @ (posedge aclk or posedge reset)
if(reset)
rvalid_rready_reg <= 1'b0;
else if(~dch_fifo_full)
rvalid_rready_reg <= rvalid_rready;
/*fifo AUTO_TEMPLATE(.rd_clk (eclk),
.wr_clk (aclk),
.wr_data (dch_fifo_in[DCH-1:0]),
.rd_data (dch_fifo_out[DCH-1:0]),
.rd_fifo_empty (dch_fifo_empty),
.wr_fifo_full (dch_fifo_full),
.wr_write (dch_fifo_wr),
.rd_read (dch_fifo_rd),
);
*/
fifo #(.DW(DCH), .AW(DFW)) fifo_dch(/*AUTOINST*/
// Outputs
.rd_data (dch_fifo_out[DCH-1:0]), // Templated
.rd_fifo_empty (dch_fifo_empty), // Templated
.wr_fifo_full (dch_fifo_full), // Templated
// Inputs
.reset (reset),
.wr_clk (aclk), // Templated
.rd_clk (eclk), // Templated
.wr_write (dch_fifo_wr), // Templated
.wr_data (dch_fifo_in[DCH-1:0]), // Templated
.rd_read (dch_fifo_rd)); // Templated
//# The data is sampled after exiting FIFO to prevent timing issues
always @ (posedge eclk)
if(~emesh_wr_wait_outb)
dch_fifo_reg[DCH-1:0] <= dch_fifo_out[DCH-1:0];
//########################
//# AXI-EMESH conversion
//########################
assign dalgn_ctrl[2:0] = wb_fifo_reg[4:2];
assign tran_mode[1:0] = wb_fifo_reg[1:0];
//# Data Alignment for the EMESH protocol
always @ (dalgn_ctrl[2:0] or dch_fifo_reg[63:0])
begin
casez (dalgn_ctrl[2:0])
3'b000 : algn_byte[MDW-1:0] = {{(MDW-8){1'b0}},dch_fifo_reg[7:0]};
3'b001 : algn_byte[MDW-1:0] = {{(MDW-8){1'b0}},dch_fifo_reg[15:8]};
3'b010 : algn_byte[MDW-1:0] = {{(MDW-8){1'b0}},dch_fifo_reg[23:16]};
3'b011 : algn_byte[MDW-1:0] = {{(MDW-8){1'b0}},dch_fifo_reg[31:24]};
3'b100 : algn_byte[MDW-1:0] = {{(MDW-8){1'b0}},dch_fifo_reg[39:32]};
3'b101 : algn_byte[MDW-1:0] = {{(MDW-8){1'b0}},dch_fifo_reg[47:40]};
3'b110 : algn_byte[MDW-1:0] = {{(MDW-8){1'b0}},dch_fifo_reg[55:48]};
3'b111 : algn_byte[MDW-1:0] = {{(MDW-8){1'b0}},dch_fifo_reg[63:56]};
default: algn_byte[MDW-1:0] = {{(MDW-8){1'b0}},dch_fifo_reg[7:0]};
endcase // casez (dalgn_ctrl[2:0])
end // always @ (dalgn_ctrl[2:0])
always @ (dalgn_ctrl[2:1] or dch_fifo_reg[63:0])
begin
casez (dalgn_ctrl[2:1])
2'b00 : algn_hword[MDW-1:0] = {{(MDW-16){1'b0}},dch_fifo_reg[15:0]};
2'b01 : algn_hword[MDW-1:0] = {{(MDW-16){1'b0}},dch_fifo_reg[31:16]};
2'b10 : algn_hword[MDW-1:0] = {{(MDW-16){1'b0}},dch_fifo_reg[47:32]};
2'b11 : algn_hword[MDW-1:0] = {{(MDW-16){1'b0}},dch_fifo_reg[63:48]};
default: algn_hword[MDW-1:0] = {{(MDW-16){1'b0}},dch_fifo_reg[15:0]};
endcase // casez (dalgn_ctrl[2:1])
end
assign algn_word[MDW-1:0] = dalgn_ctrl[2] ?
{{(MDW/2){1'b0}},dch_fifo_reg[63:32]}:
{{(MDW/2){1'b0}},dch_fifo_reg[31:0]};
assign byte_tran = (tran_mode[1:0] == 2'b00);
assign hword_tran = (tran_mode[1:0] == 2'b01);
assign word_tran = (tran_mode[1:0] == 2'b10);
assign wdata_algn[MDW-1:0] = byte_tran ? algn_byte[MDW-1:0] :
hword_tran ? algn_hword[MDW-1:0]:
word_tran ? algn_word[MDW-1:0] :
dch_fifo_reg[MDW-1:0];
always @ (posedge eclk)
if(tran_go & ~emesh_wr_wait_outb)
wdata_algn_reg[MDW-1:0] <= wdata_algn[MDW-1:0];
always @ (posedge eclk or posedge reset)
if(reset)
begin
tran_go <= 1'b0;
tran_go_reg <= 1'b0;
end
else if(~emesh_wr_wait_outb)
begin
tran_go <= dch_fifo_rd;
tran_go_reg <= tran_go;
end
//#############################
//# Emesh transaction creation
//#############################
assign emesh_dstaddr_inb[31:0] = tran_addr_mode[WB-5:5];
assign emesh_srcaddr_inb[31:0] = wdata_algn_reg[MDW-1:32];
assign emesh_data_inb[31:0] = wdata_algn_reg[31:0];
assign emesh_datamode_inb[1:0] = tran_addr_mode[1:0];
assign emesh_ctrlmode_inb[3:0] = tran_addr_mode[WB-1:WB-4];
assign emesh_write_inb = 1'b1;
assign emesh_access_inb = tran_go_reg & ~emesh_wr_wait_outb;
endmodule // axi_master_rd

368
axi/hdl/axi_master_wr.v
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@ -1,368 +0,0 @@
/*
File: axi_master_wr.v
This file is part of the Parallella FPGA Reference Design.
Copyright (C) 2013 Adapteva, Inc.
Contributed by Roman Trogan <support@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module axi_master_wr (/*AUTOARG*/
// Outputs
awid, awaddr, awlen, awsize, awburst, awlock, awcache, awprot,
awvalid, wid, wdata, wstrb, wlast, wvalid, bready,
emesh_wr_wait_inb,
// Inputs
aclk, eclk, reset, awready, wready, bid, bresp, bvalid,
emesh_access_outb, emesh_write_outb, emesh_datamode_outb,
emesh_ctrlmode_outb, emesh_dstaddr_outb, emesh_srcaddr_outb,
emesh_data_outb
);
parameter MIDW = 6; //ID Width
parameter MAW = 32; //Address Bus Width
parameter MDW = 64; //Data Bus Width
parameter ACH = MAW+2; //Width of all used Write Address Signals
parameter AFW = 4; //Address channel Fifo address width
parameter DFW = 4; //Data channel Fifo address width
parameter DCH = MDW+8; //Width of all used Write Data Signals
parameter STW = 8; //Number of strobes
//#########
//# Inputs
//#########
// global signals
input aclk; // clock source of the axi bus
input eclk; // clock source of emesh interface
input reset; // reset
//########################
//# Write address channel
//########################
input awready; //write address ready
//########################
//# Write data channel
//########################
input wready; //write ready
//#########################
//# Write response channel
//#########################
input [MIDW-1:0] bid; //response ID tag
input [1:0] bresp; //write response
input bvalid;//write response valid
//##############################
//# From the emesh interface
//##############################
input emesh_access_outb;
input emesh_write_outb;
input [1:0] emesh_datamode_outb;
input [3:0] emesh_ctrlmode_outb;
input [31:0] emesh_dstaddr_outb;
input [31:0] emesh_srcaddr_outb;
input [31:0] emesh_data_outb;
//##########
//# Outputs
//##########
//########################
//# Write address channel
//########################
output [MIDW-1:0] awid; //write address ID
output [MAW-1:0] awaddr; //write address
output [3:0] awlen; //burst lenght (the number of data transfers)
output [2:0] awsize; //burst size (the size of each transfer)
output [1:0] awburst; //burst type
output [1:0] awlock; //lock type (atomic characteristics)
output [3:0] awcache; //memory type
output [2:0] awprot; //protection type
output awvalid; //write address valid
//########################
//# Write data channel
//########################
output [MIDW-1:0] wid; //write ID tag (supported only in AXI3)
output [MDW-1:0] wdata; //write data
output [STW-1:0] wstrb; //write strobes
output wlast; //write last, indicates the last transfer in burst
output wvalid;//write valid
//########################
// Write response channel
//########################
output bready;//response ready
//##############################
//# To the emesh interface
//##############################
output emesh_wr_wait_inb;
/*AUTOINPUT*/
/*AUTOWIRE*/
//#########
//# Regs
//#########
reg [33:0] addr_reg;
reg [63:0] data_reg;
reg emesh_wr_access_reg;
reg ach_fifo_empty_reg;
reg [ACH-1:0] ach_fifo_reg;
reg [63:0] realgn_byte;
reg [63:0] realgn_hword;
reg dch_fifo_empty_reg;
reg [DCH-1:0] dch_fifo_reg;
reg [7:0] wstrb_hword;
reg [7:0] wstrb_byte;
//#########
//# Wires
//#########
wire emesh_wr_access;
wire [ACH-1:0] ach_fifo_in;
wire [ACH-1:0] ach_fifo_out;
wire ach_fifo_wr;
wire ach_fifo_rd;
wire ach_fifo_full;
wire ach_fifo_empty;
wire ach_advance;
wire awvalid_awready;
wire [2:0] realgn_ctrl;
wire byte_realgn;
wire hword_realgn;
wire word_realgn;
wire [63:0] realgn_word;
wire [63:0] data_realgn;
wire [DCH-1:0] dch_fifo_in;
wire [DCH-1:0] dch_fifo_out;
wire dch_fifo_wr;
wire dch_fifo_rd;
wire dch_fifo_empty;
wire dch_advance;
wire wvalid_wready;
wire [7:0] wstrb_realgn;
wire [7:0] wstrb_word;
wire dch_fifo_full;
//# Incoming transaction should be sampled to prevent timing issues
assign emesh_wr_wait_inb = ach_fifo_full | dch_fifo_full;
assign emesh_wr_access = emesh_access_outb & emesh_write_outb &
~emesh_wr_wait_inb;
always @ (posedge eclk)
if (emesh_wr_access)
addr_reg[33:0] <= {emesh_dstaddr_outb[31:0],emesh_datamode_outb[1:0]};
always @ (posedge eclk)
if (emesh_wr_access)
data_reg[63:0] <= {emesh_srcaddr_outb[31:0],emesh_data_outb[31:0]};
always @ (posedge eclk or posedge reset)
if(reset)
emesh_wr_access_reg <= 1'b0;
else if(~emesh_wr_wait_inb)
emesh_wr_access_reg <= emesh_wr_access;
//#######################################
//# Address channel synchronization FIFO
//#######################################
assign ach_fifo_in[ACH-1:0] = addr_reg[33:0];
assign ach_fifo_wr = emesh_wr_access_reg & ~emesh_wr_wait_inb;
assign ach_fifo_rd = ~ach_fifo_empty & (~awvalid | awvalid_awready);
assign ach_advance = awvalid_awready | ~awvalid;
/*fifo AUTO_TEMPLATE(.rd_clk (aclk),
.wr_clk (eclk),
.wr_data (ach_fifo_in[ACH-1:0]),
.rd_data (ach_fifo_out[ACH-1:0]),
.rd_fifo_empty (ach_fifo_empty),
.wr_fifo_full (ach_fifo_full),
.wr_write (ach_fifo_wr),
.rd_read (ach_fifo_rd),
);
*/
fifo #(.DW(ACH), .AW(AFW)) fifo_ach(/*AUTOINST*/
// Outputs
.rd_data (ach_fifo_out[ACH-1:0]), // Templated
.rd_fifo_empty (ach_fifo_empty), // Templated
.wr_fifo_full (ach_fifo_full), // Templated
// Inputs
.reset (reset),
.wr_clk (eclk), // Templated
.rd_clk (aclk), // Templated
.wr_write (ach_fifo_wr), // Templated
.wr_data (ach_fifo_in[ACH-1:0]), // Templated
.rd_read (ach_fifo_rd)); // Templated
//# The data is sampled after exiting FIFO to prevent timing issues
always @ (posedge aclk or posedge reset)
if(reset)
ach_fifo_empty_reg <= 1'b1;
else if(ach_advance)
ach_fifo_empty_reg <= ach_fifo_empty;
always @ (posedge aclk)
if (ach_advance)
ach_fifo_reg[ACH-1:0] <= ach_fifo_out[ACH-1:0];
assign awid[MIDW-1:0] = {(MIDW){1'b0}};
assign awaddr[MAW-1:0] = ach_fifo_reg[ACH-1:2];
assign awlen[3:0] = 4'b0000;
assign awsize[2:0] = {1'b0,ach_fifo_reg[1:0]};
assign awburst[1:0] = 2'b01;
assign awlock[1:0] = 2'b00;
assign awcache[3:0] = 4'b0000;
assign awprot[2:0] = 3'b000; //unprivileged, secured
assign awvalid = ~ach_fifo_empty_reg;
assign awvalid_awready = awvalid & awready;
//#######################################
//# Data channel synchronization FIFO
//#######################################
assign realgn_ctrl[2:0] = addr_reg[4:2];
assign byte_realgn = (addr_reg[1:0] == 2'b00);
assign hword_realgn = (addr_reg[1:0] == 2'b01);
assign word_realgn = (addr_reg[1:0] == 2'b10);
always @ (realgn_ctrl[2:0] or data_reg[7:0])
begin
casez (realgn_ctrl[2:0])
3'b000 : realgn_byte[63:0] = {{(56){1'b0}},data_reg[7:0] };
3'b001 : realgn_byte[63:0] = {{(48){1'b0}},data_reg[7:0],{( 8){1'b0}}};
3'b010 : realgn_byte[63:0] = {{(40){1'b0}},data_reg[7:0],{(16){1'b0}}};
3'b011 : realgn_byte[63:0] = {{(32){1'b0}},data_reg[7:0],{(24){1'b0}}};
3'b100 : realgn_byte[63:0] = {{(24){1'b0}},data_reg[7:0],{(32){1'b0}}};
3'b101 : realgn_byte[63:0] = {{(16){1'b0}},data_reg[7:0],{(40){1'b0}}};
3'b110 : realgn_byte[63:0] = {{(8){1'b0}},data_reg[7:0] ,{(48){1'b0}}};
3'b111 : realgn_byte[63:0] = { data_reg[7:0] ,{(56){1'b0}}};
default: realgn_byte[63:0] = {{(56){1'b0}},data_reg[7:0]};
endcase // casez (realgn_ctrl[2:0])
end // always @ (realgn_ctrl[2:0])
always @ (realgn_ctrl[2:1] or data_reg[15:0])
begin
casez (realgn_ctrl[2:1])
2'b00 : realgn_hword[63:0] = {{(48){1'b0}},data_reg[15:0]};
2'b01 : realgn_hword[63:0] = {{(32){1'b0}},data_reg[15:0],{(16){1'b0}}};
2'b10 : realgn_hword[63:0] = {{(16){1'b0}},data_reg[15:0],{(32){1'b0}}};
2'b11 : realgn_hword[63:0] = { data_reg[15:0],{(48){1'b0}}};
default: realgn_hword[63:0] = {{(48){1'b0}},data_reg[15:0]};
endcase // casez (realgn_ctrl[2:1])
end
assign realgn_word[63:0] = realgn_ctrl[2] ? {data_reg[31:0],{(32){1'b0}}} :
{{(32){1'b0}},data_reg[31:0]};
assign data_realgn[63:0] = byte_realgn ? realgn_byte[63:0] :
hword_realgn ? realgn_hword[63:0]:
word_realgn ? realgn_word[63:0] :
data_reg[63:0];
//Write Strobes creation
always @ (realgn_ctrl[2:0])
begin
casez (realgn_ctrl[2:0])
3'b000 : wstrb_byte[7:0] = 8'b00000001;
3'b001 : wstrb_byte[7:0] = 8'b00000010;
3'b010 : wstrb_byte[7:0] = 8'b00000100;
3'b011 : wstrb_byte[7:0] = 8'b00001000;
3'b100 : wstrb_byte[7:0] = 8'b00010000;
3'b101 : wstrb_byte[7:0] = 8'b00100000;
3'b110 : wstrb_byte[7:0] = 8'b01000000;
3'b111 : wstrb_byte[7:0] = 8'b10000000;
default: wstrb_byte[7:0] = 8'b00000001;
endcase // casez (realgn_ctrl[2:0])
end // always @ (realgn_ctrl[2:0])
always @ (realgn_ctrl[2:1])
begin
casez (realgn_ctrl[2:1])
2'b00 : wstrb_hword[7:0] = 8'b00000011;
2'b01 : wstrb_hword[7:0] = 8'b00001100;
2'b10 : wstrb_hword[7:0] = 8'b00110000;
2'b11 : wstrb_hword[7:0] = 8'b11000000;
default: wstrb_hword[7:0] = 8'b00000011;
endcase // casez (realgn_ctrl[2:1])
end
assign wstrb_word[7:0] = realgn_ctrl[2] ? 8'b11110000 : 8'b00001111;
assign wstrb_realgn[7:0] = byte_realgn ? wstrb_byte[7:0] :
hword_realgn ? wstrb_hword[7:0]:
word_realgn ? wstrb_word[7:0] : {(8){1'b1}};
assign dch_fifo_in[DCH-1:0] = {data_realgn[63:0],wstrb_realgn[7:0]};
assign dch_fifo_wr = emesh_wr_access_reg & ~emesh_wr_wait_inb;
assign dch_fifo_rd = ~dch_fifo_empty & (~wvalid | wvalid_wready);
assign dch_advance = wvalid_wready | ~wvalid;
/*fifo AUTO_TEMPLATE(.rd_clk (aclk),
.wr_clk (eclk),
.wr_data (dch_fifo_in[DCH-1:0]),
.rd_data (dch_fifo_out[DCH-1:0]),
.rd_fifo_empty (dch_fifo_empty),
.wr_fifo_full (dch_fifo_full),
.wr_write (dch_fifo_wr),
.rd_read (dch_fifo_rd),
);
*/
fifo #(.DW(DCH), .AW(DFW)) fifo_dch(/*AUTOINST*/
// Outputs
.rd_data (dch_fifo_out[DCH-1:0]), // Templated
.rd_fifo_empty (dch_fifo_empty), // Templated
.wr_fifo_full (dch_fifo_full), // Templated
// Inputs
.reset (reset),
.wr_clk (eclk), // Templated
.rd_clk (aclk), // Templated
.wr_write (dch_fifo_wr), // Templated
.wr_data (dch_fifo_in[DCH-1:0]), // Templated
.rd_read (dch_fifo_rd)); // Templated
//# The data is sampled after exiting FIFO to prevent timing issues
always @ (posedge aclk or posedge reset)
if(reset)
dch_fifo_empty_reg <= 1'b1;
else if(dch_advance)
dch_fifo_empty_reg <= dch_fifo_empty;
always @ (posedge aclk)
if (dch_advance)
dch_fifo_reg[DCH-1:0] <= dch_fifo_out[DCH-1:0];
assign wid[MIDW-1:0] = {(MIDW){1'b0}};
assign wdata[MDW-1:0] = dch_fifo_reg[DCH-1:8];
assign wstrb[STW-1:0] = dch_fifo_reg[7:0];
assign wlast = 1'b1;
assign wvalid = ~dch_fifo_empty_reg;
assign wvalid_wready = wvalid & wready;
assign bready = 1'b1;
endmodule // axi_master_wr

348
axi/hdl/axi_slave.v
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@ -1,348 +0,0 @@
/*
File: axi_slave.v
This file is part of the Parallella FPGA Reference Design.
Copyright (C) 2013 Adapteva, Inc.
Contributed by Roman Trogan <support@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module axi_slave (/*AUTOARG*/
// Outputs
csysack, cactive, awready, wready, bid, bresp, bvalid, arready,
rid, rdata, rresp, rlast, rvalid, emesh_access_inb,
emesh_write_inb, emesh_datamode_inb, emesh_ctrlmode_inb,
emesh_dstaddr_inb, emesh_srcaddr_inb, emesh_data_inb,
emesh_wr_wait_inb, emesh_rd_wait_inb,
// Inputs
aclk, eclk, reset, csysreq, awid, awaddr, awlen, awsize, awburst,
awlock, awcache, awprot, awvalid, wid, wdata, wstrb, wlast, wvalid,
bready, arid, araddr, arlen, arsize, arburst, arlock, arcache,
arprot, arvalid, rready, emesh_access_outb, emesh_write_outb,
emesh_datamode_outb, emesh_ctrlmode_outb, emesh_dstaddr_outb,
emesh_srcaddr_outb, emesh_data_outb, emesh_wr_wait_outb,
emesh_rd_wait_outb, awqos, arqos
);
parameter SIDW = 12; //ID Width
parameter SAW = 32; //Address Bus Width
parameter SDW = 32; //Data Bus Width
//#########
//# Inputs
//#########
// global signals
input aclk; // clock source of the axi bus
input eclk; // clock source of emesh interface
input reset; // reset
input csysreq;// system exit low-power state request
//########################
//# Write address channel
//########################
input [SIDW-1:0] awid; //write address ID
input [SAW-1:0] awaddr; //write address
input [3:0] awlen; //burst lenght (the number of data transfers)
input [2:0] awsize; //burst size (the size of each transfer)
input [1:0] awburst; //burst type
input [1:0] awlock; //lock type (atomic characteristics)
input [3:0] awcache; //memory type
input [2:0] awprot; //protection type
input awvalid; //write address valid
//########################
//# Write data channel
//########################
input [SIDW-1:0] wid; //write ID tag (supported only in AXI3)
input [SDW-1:0] wdata; //write data
input [3:0] wstrb; //write strobes
input wlast; //write last. Indicates the last transfer in burst
input wvalid;//write valid
//########################
// Write response channel
//########################
input bready;//response ready
//########################
//# Read address channel
//########################
input [SIDW-1:0] arid; //read address ID
input [SAW-1:0] araddr; //read address
input [3:0] arlen; //burst lenght (the number of data transfers)
input [2:0] arsize; //burst size (the size of each transfer)
input [1:0] arburst; //burst type
input [1:0] arlock; //lock type (atomic characteristics)
input [3:0] arcache; //memory type
input [2:0] arprot; //protection type
input arvalid; //write address valid
//########################
//# Read data channel
//########################
input rready; //read ready
//##############################
//# From the emesh interface
//##############################
input emesh_access_outb;
input emesh_write_outb;
input [1:0] emesh_datamode_outb;
input [3:0] emesh_ctrlmode_outb;
input [31:0] emesh_dstaddr_outb;
input [31:0] emesh_srcaddr_outb;
input [31:0] emesh_data_outb;
input emesh_wr_wait_outb;
input emesh_rd_wait_outb;
//##########
//# Outputs
//##########
// global signals
output csysack;//exit low-power state acknowledgement
output cactive;//clock active
//########################
//# Write address channel
//########################
output awready; //write address ready
//########################
//# Write data channel
//########################
output wready; //write ready
//########################
// Write response channel
//########################
output [SIDW-1:0] bid; //response ID tag
output [1:0] bresp; //write response
output bvalid;//write response valid
//########################
//# Read address channel
//########################
output arready;//read address ready
//########################
//# Read data channel
//########################
output [SIDW-1:0] rid; //read ID tag (must match arid of the transaction)
output [SDW-1:0] rdata; //read data
output [1:0] rresp; //read response
output rlast; //read last, indicates the last transfer in burst
output rvalid;//read valid
//##############################
//# To the emesh interface
//##############################
output emesh_access_inb;
output emesh_write_inb;
output [1:0] emesh_datamode_inb;
output [3:0] emesh_ctrlmode_inb;
output [31:0] emesh_dstaddr_inb;
output [31:0] emesh_srcaddr_inb;
output [31:0] emesh_data_inb;
output emesh_wr_wait_inb;
output emesh_rd_wait_inb;
//#######################################################################
//# The following feature are not supported (AXI4 only)
//# If un-commented, those signals have to be driven with default values
//#######################################################################
input [3:0] awqos; //Quality of Service (AXI4 only) default 4'b0000
// input [3:0] awregion;//region identifier (AXI4 only)
// input awuser; //user signal (AXI4 only)
// input wuser; //user signal (AXI4 only)
input [3:0] arqos; //quality of service (AXI4 only) default 4'b0000
// input [3:0] arregion;//region identifier (AXI4 only)
// input aruser; //user signal (AXI4 only)
// output buser; //user signal (AXI4 only)
// output ruser; //user signal (AXI4 only)
//#########
//# Regs
//#########
reg csysack;
//#########
//# Wires
//#########
wire emesh_wr_access_inb;
wire emesh_wr_write_inb;
wire [1:0] emesh_wr_datamode_inb;
wire [3:0] emesh_wr_ctrlmode_inb;
wire [31:0] emesh_wr_dstaddr_inb;
wire [31:0] emesh_wr_srcaddr_inb;
wire [31:0] emesh_wr_data_inb;
wire emesh_rd_access_inb;
wire emesh_rd_write_inb;
wire [1:0] emesh_rd_datamode_inb;
wire [3:0] emesh_rd_ctrlmode_inb;
wire [31:0] emesh_rd_dstaddr_inb;
wire [31:0] emesh_rd_srcaddr_inb;
wire [31:0] emesh_rd_data_inb;
wire emesh_rd_wait;
/*AUTOINPUT*/
/*AUTOWIRE*/
//##################################################
//# This block doesn't accept read transactions
//# from emesh.
//##################################################
assign emesh_rd_wait_inb = 1'b0;
//##################################################
//# Low Power State
//# We don't support low power state
//##################################################
assign cactive = 1'b1;
always @ (posedge eclk or posedge reset)
if(reset)
csysack <= 1'b1;
else
csysack <= csysreq;
//##################################################
//# RD/WR transaction selection
//# *Write transactions are of the higher priority
//##################################################
assign emesh_rd_wait = emesh_rd_wait_outb | emesh_wr_access_inb;
assign emesh_access_inb = emesh_wr_access_inb | emesh_rd_access_inb;
assign emesh_write_inb = emesh_wr_access_inb ? emesh_wr_write_inb :
emesh_rd_write_inb;
assign emesh_datamode_inb[1:0] = emesh_wr_access_inb ?
emesh_wr_datamode_inb[1:0] :
emesh_rd_datamode_inb[1:0];
assign emesh_ctrlmode_inb[3:0] = emesh_wr_access_inb ?
emesh_wr_ctrlmode_inb[3:0] :
emesh_rd_ctrlmode_inb[3:0];
assign emesh_dstaddr_inb[31:0] = emesh_wr_access_inb ?
emesh_wr_dstaddr_inb[31:0] :
emesh_rd_dstaddr_inb[31:0];
assign emesh_srcaddr_inb[31:0] = emesh_wr_access_inb ?
emesh_wr_srcaddr_inb[31:0] :
emesh_rd_srcaddr_inb[31:0];
assign emesh_data_inb[31:0] = emesh_wr_access_inb ?
emesh_wr_data_inb[31:0] :
emesh_rd_data_inb[31:0];
//##################################
//# Slave Write Port Instantiation
//##################################
/*axi_slave_wr AUTO_TEMPLATE(.emesh_wr_wait_outb (emesh_wr_wait_outb),
.emesh_\(.*\)_inb (emesh_wr_\1_inb[]),
);
*/
axi_slave_wr axi_slave_wr(/*AUTOINST*/
// Outputs
.awready (awready),
.wready (wready),
.bid (bid[SIDW-1:0]),
.bresp (bresp[1:0]),
.bvalid (bvalid),
.emesh_access_inb (emesh_wr_access_inb), // Templated
.emesh_write_inb (emesh_wr_write_inb), // Templated
.emesh_datamode_inb(emesh_wr_datamode_inb[1:0]), // Templated
.emesh_ctrlmode_inb(emesh_wr_ctrlmode_inb[3:0]), // Templated
.emesh_dstaddr_inb (emesh_wr_dstaddr_inb[31:0]), // Templated
.emesh_srcaddr_inb (emesh_wr_srcaddr_inb[31:0]), // Templated
.emesh_data_inb (emesh_wr_data_inb[31:0]), // Templated
// Inputs
.aclk (aclk),
.eclk (eclk),
.reset (reset),
.awid (awid[SIDW-1:0]),
.awaddr (awaddr[SAW-1:0]),
.awlen (awlen[3:0]),
.awsize (awsize[2:0]),
.awburst (awburst[1:0]),
.awlock (awlock[1:0]),
.awcache (awcache[3:0]),
.awprot (awprot[2:0]),
.awvalid (awvalid),
.wid (wid[SIDW-1:0]),
.wdata (wdata[SDW-1:0]),
.wstrb (wstrb[3:0]),
.wlast (wlast),
.wvalid (wvalid),
.bready (bready),
.emesh_wr_wait_outb(emesh_wr_wait_outb)); // Templated
//##################################
//# Slave Read Port Instantiation
//##################################
/*axi_slave_rd AUTO_TEMPLATE(.emesh_rd_wait_outb (emesh_rd_wait),
.emesh_wr_wait_inb (emesh_wr_wait_inb),
.emesh_\(.*\)_inb (emesh_rd_\1_inb[]),
);
*/
axi_slave_rd axi_slave_rd(/*AUTOINST*/
// Outputs
.arready (arready),
.rid (rid[SIDW-1:0]),
.rdata (rdata[SDW-1:0]),
.rresp (rresp[1:0]),
.rlast (rlast),
.rvalid (rvalid),
.emesh_access_inb (emesh_rd_access_inb), // Templated
.emesh_write_inb (emesh_rd_write_inb), // Templated
.emesh_datamode_inb(emesh_rd_datamode_inb[1:0]), // Templated
.emesh_ctrlmode_inb(emesh_rd_ctrlmode_inb[3:0]), // Templated
.emesh_dstaddr_inb (emesh_rd_dstaddr_inb[31:0]), // Templated
.emesh_srcaddr_inb (emesh_rd_srcaddr_inb[31:0]), // Templated
.emesh_data_inb (emesh_rd_data_inb[31:0]), // Templated
.emesh_wr_wait_inb (emesh_wr_wait_inb), // Templated
// Inputs
.aclk (aclk),
.eclk (eclk),
.reset (reset),
.arid (arid[SIDW-1:0]),
.araddr (araddr[SAW-1:0]),
.arlen (arlen[3:0]),
.arsize (arsize[2:0]),
.arburst (arburst[1:0]),
.arlock (arlock[1:0]),
.arcache (arcache[3:0]),
.arprot (arprot[2:0]),
.arvalid (arvalid),
.rready (rready),
.emesh_access_outb (emesh_access_outb),
.emesh_write_outb (emesh_write_outb),
.emesh_datamode_outb(emesh_datamode_outb[1:0]),
.emesh_ctrlmode_outb(emesh_ctrlmode_outb[3:0]),
.emesh_dstaddr_outb(emesh_dstaddr_outb[31:0]),
.emesh_srcaddr_outb(emesh_srcaddr_outb[31:0]),
.emesh_data_outb (emesh_data_outb[31:0]),
.emesh_rd_wait_outb(emesh_rd_wait)); // Templated
endmodule // axi_slave

225
axi/hdl/axi_slave_addrch.v
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@ -1,225 +0,0 @@
/*
File: axi_slave_addrch.v
This file is part of the Parallella FPGA Reference Design.
Copyright (C) 2013 Adapteva, Inc.
Contributed by Roman Trogan <support@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module axi_slave_addrch (/*AUTOARG*/
// Outputs
aready, ach_fifo_empty, tran_addr, tran_mode, dalgn_ctrl,
byte_tran, hword_tran, word_tran, aid_ec, alen_ec, new_addr_sel,
// Inputs
aclk, eclk, reset, avalid, addr, aid, alen, asize, aburst,
tran_last, tran_stall, tran_go
);
parameter SAW = 32; //Address Bus Width
parameter SIDW = 12; //ID Width
parameter ACH = SAW+SIDW+9; //Width of all used Address Signals
parameter AFW = 4; //Address channel FIFO address width
//#########
//# Inputs
//#########
// global signals
input aclk; //clock source of the axi bus
input eclk; //clock source of emesh interface
input reset; //reset
input avalid; //address valid
input [SAW-1:0] addr; //address
input [SIDW-1:0] aid; //address ID
input [3:0] alen; //burst lenght (the number of data transfers)
input [2:0] asize; //burst size (the size of each transfer)
input [1:0] aburst; //burst type
input tran_last; //Last data of burst
input tran_stall; //Transaction stall
input tran_go; //Transaction is "dispatching"
//##########
//# Outputs
//##########
output aready; //address ready
output ach_fifo_empty;
output [SAW-1:0] tran_addr;
output [1:0] tran_mode;
output [2:0] dalgn_ctrl;
output byte_tran;
output hword_tran;
output word_tran;
output [SIDW-1:0] aid_ec;
output [3:0] alen_ec;
output new_addr_sel;
/*AUTOINPUT*/
/*AUTOWIRE*/
//#########
//# Regs
//#########
reg [ACH-1:0] ach_fifo_in;
reg avalid_aready_reg;
reg [ACH-1:0] ach_fifo_reg;
reg ach_fifo_rd_reg;
reg [SAW-1:0] tran_addr;
reg [1:0] tran_mode;
reg ach_fifo_empty_reg;
//#########
//# Wires
//#########
wire [ACH-1:0] ach_data_in;
wire [ACH-1:0] ach_fifo_out;
wire aready;
wire avalid_aready;
wire ach_fifo_full;
wire ach_fifo_rd;
wire ach_fifo_wr;
wire ach_fifo_empty;
wire [SAW-1:0] addr_ec; // "_ec" indicates an eclk domain signal
wire [SIDW-1:0] aid_ec;
wire [3:0] alen_ec;
wire [2:0] asize_ec;
wire [1:0] aburst_ec;
wire incr_burst;
wire byte_tran;
wire hword_tran;
wire word_tran;
wire [3:0] addr_incr;
wire [SAW-1:0] addr_upd;
wire [SAW-1:0] addr_mask;
wire [SAW-1:0] addr_algn;
wire [SAW-1:0] addr_new;
wire [2:0] dalgn_ctrl;
wire new_addr_sel;
//# The data is sampled before entering FIFO to prevent timing issues
assign ach_data_in[ACH-1:0] = {addr[SAW-1:0],aid[SIDW-1:0],alen[3:0],
asize[2:0],aburst[1:0]};
always @ (posedge aclk)
if(~ach_fifo_full)
ach_fifo_in[ACH-1:0] <= ach_data_in[ACH-1:0];
always @ (posedge aclk or posedge reset)
if(reset)
avalid_aready_reg <= 1'b0;
else if(~ach_fifo_full)
avalid_aready_reg <= avalid_aready;
assign aready = ~ach_fifo_full;
assign avalid_aready = avalid & aready;
assign ach_fifo_rd = ~(ach_fifo_empty | ~tran_last | tran_stall);
assign ach_fifo_wr = avalid_aready_reg & ~ach_fifo_full;
/*fifo AUTO_TEMPLATE(.rd_clk (eclk),
.wr_clk (aclk),
.wr_data (ach_fifo_in[ACH-1:0]),
.rd_data (ach_fifo_out[ACH-1:0]),
.rd_fifo_empty (ach_fifo_empty),
.wr_fifo_full (ach_fifo_full),
.wr_write (ach_fifo_wr),
.rd_read (ach_fifo_rd),
);
*/
fifo #(.DW(ACH), .AW(AFW)) fifo_ach(/*AUTOINST*/
// Outputs
.rd_data (ach_fifo_out[ACH-1:0]), // Templated
.rd_fifo_empty (ach_fifo_empty), // Templated
.wr_fifo_full (ach_fifo_full), // Templated
// Inputs
.reset (reset),
.wr_clk (aclk), // Templated
.rd_clk (eclk), // Templated
.wr_write (ach_fifo_wr), // Templated
.wr_data (ach_fifo_in[ACH-1:0]), // Templated
.rd_read (ach_fifo_rd)); // Templated
//# The data is sampled after exiting FIFO to prevent timing issues
always @ (posedge eclk)
if(~tran_stall)
ach_fifo_reg[ACH-1:0] <= ach_fifo_out[ACH-1:0];
always @ (posedge eclk or posedge reset)
if(reset)
ach_fifo_rd_reg <= 1'b0;
else if(~tran_stall)
ach_fifo_rd_reg <= ach_fifo_rd;
//# Address info decode
assign addr_ec[SAW-1:0] = ach_fifo_reg[ACH-1:ACH-SAW];
assign aid_ec[SIDW-1:0] = ach_fifo_reg[ACH-SAW-1:9];
assign alen_ec[3:0] = ach_fifo_reg[8:5] + 4'b0001;
assign asize_ec[2:0] = ach_fifo_reg[4:2];
assign aburst_ec[1:0] = ach_fifo_reg[1:0];
//# currently only INCR and FIXED bursts are supported
//# WRAP type burst will be treated as FIXED type
assign incr_burst = (aburst_ec[1:0] == 2'b01);
//# size decode
assign byte_tran = (asize_ec[2:0] == 3'b000);
assign hword_tran = (asize_ec[2:0] == 3'b001);
assign word_tran = (asize_ec[2:0] == 3'b010);
//# new address calculation
assign addr_incr[3:0] = byte_tran ? {3'b000,incr_burst}:
hword_tran ? {2'b00, incr_burst,1'b0}:
word_tran ? {1'b0, incr_burst,2'b00} :
{ incr_burst,3'b000};
assign addr_upd[SAW-1:0] = tran_addr[SAW-1:0] +{{(SAW-4){1'b0}},addr_incr[3:0]};
//# Since we don't support unaligned transfers, a special masking
//# mechanism is implemented to "turn" an illegal transfer into legal.
assign addr_mask[SAW-1:0] = byte_tran ? {{(SAW-3){1'b1}},3'b111}:
hword_tran ? {{(SAW-3){1'b1}},3'b110}:
word_tran ? {{(SAW-3){1'b1}},3'b100}:
{{(SAW-3){1'b1}},3'b000};
assign addr_algn[SAW-1:0] = addr_ec[SAW-1:0] & addr_mask[SAW-1:0];
assign addr_new[SAW-1:0] = new_addr_sel ? addr_algn[SAW-1:0] :
addr_upd[SAW-1:0];
always @ (posedge eclk)
if(tran_go & ~tran_stall)
begin
tran_addr[SAW-1:0] <= addr_new[SAW-1:0];
tran_mode[1:0] <= asize_ec[1:0];
end
assign dalgn_ctrl[2:0] = addr_new[2:0];
always @ (posedge eclk or posedge reset)
if (reset)
ach_fifo_empty_reg <= 1'b1;
else if((ach_fifo_empty | tran_go) & ~tran_stall)
ach_fifo_empty_reg <= ach_fifo_empty;
assign new_addr_sel = (ach_fifo_empty_reg | ach_fifo_rd_reg) &
~ach_fifo_empty;
endmodule // axi_slave_addrch

377
axi/hdl/axi_slave_rd.v
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@ -1,377 +0,0 @@
/*
File: axi_slave_rd.v
This file is part of the Parallella FPGA Reference Design.
Copyright (C) 2013 Adapteva, Inc.
Contributed by Roman Trogan <support@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
//# Limitations:
//# 1. Read burst cannot cross single core boundaries
module axi_slave_rd (/*AUTOARG*/
// Outputs
arready, rid, rdata, rresp, rlast, rvalid, emesh_access_inb,
emesh_write_inb, emesh_datamode_inb, emesh_ctrlmode_inb,
emesh_dstaddr_inb, emesh_srcaddr_inb, emesh_data_inb,
emesh_wr_wait_inb,
// Inputs
aclk, eclk, reset, arid, araddr, arlen, arsize, arburst, arlock,
arcache, arprot, arvalid, rready, emesh_access_outb,
emesh_write_outb, emesh_datamode_outb, emesh_ctrlmode_outb,
emesh_dstaddr_outb, emesh_srcaddr_outb, emesh_data_outb,
emesh_rd_wait_outb
);
parameter SIDW = 12; //ID Width
parameter SAW = 32; //Address Bus Width
parameter SDW = 32; //Data Bus Width
parameter ACH = SAW+SIDW+5; //Width of all used Read Address Signals
parameter DFW = 4; //Data channel Fifo address width
parameter DCH = SDW+SIDW+1; //Width of all used Read Data Signals
//#########
//# Inputs
//#########
// global signals
input aclk; // clock source of the axi bus
input eclk; // clock source of emesh interface
input reset; // reset
//########################
//# Read address channel
//########################
input [SIDW-1:0] arid; //read address ID
input [SAW-1:0] araddr; //read address
input [3:0] arlen; //burst lenght (the number of data transfers)
input [2:0] arsize; //burst size (the size of each transfer)
input [1:0] arburst; //burst type
input [1:0] arlock; //lock type (atomic characteristics)
input [3:0] arcache; //memory type
input [2:0] arprot; //protection type
input arvalid; //write address valid
//########################
//# Read data channel
//########################
input rready; //read ready
//##############################
//# From the emesh interface
//##############################
input emesh_access_outb;
input emesh_write_outb;
input [1:0] emesh_datamode_outb;
input [3:0] emesh_ctrlmode_outb;
input [31:0] emesh_dstaddr_outb;
input [31:0] emesh_srcaddr_outb;
input [31:0] emesh_data_outb;
input emesh_rd_wait_outb;
//##########
//# Outputs
//##########
//########################
//# Read address channel
//########################
output arready;//read address ready
//########################
//# Read data channel
//########################
output [SIDW-1:0] rid; //read ID tag (must match arid of the transaction)
output [SDW-1:0] rdata;//read data
output [1:0] rresp; //read response
output rlast; //read last, indicates the last transfer in burst
output rvalid;//read valid
//##############################
//# To the emesh interface
//##############################
output emesh_access_inb;
output emesh_write_inb;
output [1:0] emesh_datamode_inb;
output [3:0] emesh_ctrlmode_inb;
output [31:0] emesh_dstaddr_inb;
output [31:0] emesh_srcaddr_inb;
output [31:0] emesh_data_inb;
output emesh_wr_wait_inb;
/*AUTOINPUT*/
/*AUTOWIRE*/
//#########
//# Regs
//#########
reg [3:0] tran_len;
reg tran_go_reg;
reg [SIDW+5:0] tran_info_reg;
reg tran_last_reg;
reg [31:0] dstaddr_reg;
reg [31:0] data_reg;
reg emesh_wr_access_reg;
reg [31:0] realgn_byte;
reg dch_fifo_empty_reg;
reg [DCH-1:0] dch_fifo_reg;
//#########
//# Wires
//#########
wire arready;
wire tran_go;
wire tran_stall;
wire tran_last_int;
wire tran_last;//Indicates last data of burst (out of fifo_dch)
wire [SAW-1:0] tran_addr;
wire [1:0] tran_mode;
wire [SIDW-1:0] arid_ec;
wire [3:0] arlen_ec;
wire [3:0] arlen_new;
wire arlen_dec;
wire [3:0] arlen_upd;
wire rd_last;
wire [2:0] dalgn_ctrl;
wire byte_tran;
wire hword_tran;
wire word_tran;
wire [SIDW+5:0] tran_info;
wire emesh_wr_access;
wire dch_fifo_full;
wire [2:0] realgn_ctrl;
wire [31:0] realgn_hword;
wire byte_realgn;
wire hword_realgn;
// wire word_realgn;
wire [31:0] data_realgn;
wire [SIDW-1:0] tran_id;
wire last_tran;
wire [DCH-1:0] dch_fifo_in;
wire dch_fifo_wr;
wire dch_fifo_rd;
wire dch_fifo_empty;
wire [DCH-1:0] dch_fifo_out;
wire rvalid_rready;
wire dch_advance;
wire new_burst;
//#######################################
//# Address channel synchronization FIFO
//#######################################
/*axi_slave_addrch AUTO_TEMPLATE(.aclk (aclk),
.addr (araddr[]),
.ach_fifo_empty (),
.a\(.*\) (ar\1[]),
.new_addr_sel (new_burst),
);
*/
axi_slave_addrch axi_slave_addrch(/*AUTOINST*/
// Outputs
.aready (arready), // Templated
.ach_fifo_empty (), // Templated
.tran_addr (tran_addr[SAW-1:0]),
.tran_mode (tran_mode[1:0]),
.dalgn_ctrl (dalgn_ctrl[2:0]),
.byte_tran (byte_tran),
.hword_tran (hword_tran),
.word_tran (word_tran),
.aid_ec (arid_ec[SIDW-1:0]), // Templated
.alen_ec (arlen_ec[3:0]), // Templated
.new_addr_sel (new_burst), // Templated
// Inputs
.aclk (aclk), // Templated
.eclk (eclk),
.reset (reset),
.avalid (arvalid), // Templated
.addr (araddr[SAW-1:0]), // Templated
.aid (arid[SIDW-1:0]), // Templated
.alen (arlen[3:0]), // Templated
.asize (arsize[2:0]), // Templated
.aburst (arburst[1:0]), // Templated
.tran_last (tran_last),
.tran_stall (tran_stall),
.tran_go (tran_go));
//########################
//# AXI-EMESH conversion
//########################
assign tran_go = |(arlen_new[3:0]);
assign tran_last_int = dch_fifo_wr & last_tran;
assign tran_last = tran_last_reg & ~tran_stall;
always @ (posedge eclk or posedge reset)
if(reset)
tran_last_reg <= 1'b0;
else if(tran_last_int | ~tran_stall)
tran_last_reg <= tran_last_int;
always @ (posedge eclk or posedge reset)
if(reset)
tran_len[3:0] <= 4'b0000;
else if(tran_go & ~tran_stall)
tran_len[3:0] <= arlen_new[3:0];
always @ (posedge eclk or posedge reset)
if(reset)
tran_go_reg <= 1'b0;
else if(~tran_stall)
tran_go_reg <= tran_go;
assign arlen_dec = |(tran_len[3:0]);
assign arlen_upd[3:0] = {(4){arlen_dec}} & (tran_len[3:0] - 4'b0001);
assign arlen_new[3:0] = new_burst ? arlen_ec[3:0] : arlen_upd[3:0];
assign rd_last = (tran_len[3:0] == 4'b0001);
assign tran_info[SIDW+5:0] = {arid_ec[SIDW-1:0],dalgn_ctrl[2:0],byte_tran,
hword_tran,word_tran};
always @ (posedge eclk)
if(tran_go & ~tran_stall)
tran_info_reg[SIDW+5:0] <= tran_info[SIDW+5:0];
//#############################
//# Emesh transaction creation
//#############################
assign emesh_dstaddr_inb[31:0] = tran_addr[SAW-1:0];
assign emesh_srcaddr_inb[31:0] = {`AXI_COORD,{(13-SIDW){1'b0}},
tran_info_reg[SIDW+5:0], rd_last};
assign emesh_data_inb[31:0] = 32'h00000000;
assign emesh_datamode_inb[1:0] = tran_mode[1:0];
assign emesh_ctrlmode_inb[3:0] = 4'b0000;
assign emesh_write_inb = 1'b0;
assign emesh_access_inb = tran_go_reg & ~tran_stall;
//#######################################
//# Data channel synchronization FIFO
//#######################################
assign emesh_wr_wait_inb = dch_fifo_full;
//# Incoming transaction should be sampled to prevent timing issues
assign emesh_wr_access = emesh_access_outb & emesh_write_outb &
~emesh_wr_wait_inb;
always @ (posedge eclk)
if (emesh_wr_access)
dstaddr_reg[31:0] <= emesh_dstaddr_outb[31:0];
always @ (posedge eclk)
if (emesh_wr_access)
data_reg[31:0] <= emesh_data_outb[31:0];
always @ (posedge eclk or posedge reset)
if(reset)
emesh_wr_access_reg <= 1'b0;
else if(~emesh_wr_wait_inb)
emesh_wr_access_reg <= emesh_wr_access;
//# RID
assign tran_id[SIDW-1:0] = dstaddr_reg[SIDW+6:7];
//# Data Re-alignment from the EMESH protocol
assign realgn_ctrl[2:0] = dstaddr_reg[6:4];
assign byte_realgn = dstaddr_reg[3];
assign hword_realgn = dstaddr_reg[2];
// assign word_realgn = dstaddr_reg[1];
//# Last transfer
assign last_tran = dstaddr_reg[0];
always @ (realgn_ctrl[1:0] or data_reg[7:0])
begin
casez (realgn_ctrl[1:0])
2'b00 : realgn_byte[31:0] = {{(24){1'b0}},data_reg[7:0] };
2'b01 : realgn_byte[31:0] = {{(16){1'b0}},data_reg[7:0],{( 8){1'b0}}};
2'b10 : realgn_byte[31:0] = {{(8){1'b0}},data_reg[7:0],{(16){1'b0}}};
2'b11 : realgn_byte[31:0] = {data_reg[7:0],{(24){1'b0}}};
default: realgn_byte[31:0] = {{(24){1'b0}},data_reg[7:0]};
endcase // casez (realgn_ctrl[1:0])
end
assign realgn_hword[31:0] = realgn_ctrl[1] ? {data_reg[15:0],{(16){1'b0}}} :
{{(16){1'b0}},data_reg[15:0]};
assign data_realgn[31:0] = byte_realgn ? realgn_byte[31:0] :
hword_realgn ? realgn_hword[31:0]:
data_reg[31:0];
assign dch_fifo_in[DCH-1:0] = {data_realgn[31:0],tran_id[SIDW-1:0],last_tran};
assign dch_fifo_wr = emesh_wr_access_reg & ~dch_fifo_full;
assign dch_fifo_rd = ~dch_fifo_empty & (~rvalid | rvalid_rready);
assign dch_advance = rvalid_rready | ~rvalid;
/*fifo AUTO_TEMPLATE(.rd_clk (aclk),
.wr_clk (eclk),
.wr_data (dch_fifo_in[DCH-1:0]),
.rd_data (dch_fifo_out[DCH-1:0]),
.rd_fifo_empty (dch_fifo_empty),
.wr_fifo_full (dch_fifo_full),
.wr_write (dch_fifo_wr),
.rd_read (dch_fifo_rd),
);
*/
fifo #(.DW(DCH), .AW(DFW)) fifo_dch(/*AUTOINST*/
// Outputs
.rd_data (dch_fifo_out[DCH-1:0]), // Templated
.rd_fifo_empty (dch_fifo_empty), // Templated
.wr_fifo_full (dch_fifo_full), // Templated
// Inputs
.reset (reset),
.wr_clk (eclk), // Templated
.rd_clk (aclk), // Templated
.wr_write (dch_fifo_wr), // Templated
.wr_data (dch_fifo_in[DCH-1:0]), // Templated
.rd_read (dch_fifo_rd)); // Templated
//# The data is sampled after exiting FIFO to prevent timing issues
always @ (posedge aclk or posedge reset)
if(reset)
dch_fifo_empty_reg <= 1'b1;
else if(dch_advance)
dch_fifo_empty_reg <= dch_fifo_empty;
always @ (posedge aclk)
if (dch_advance)
dch_fifo_reg[DCH-1:0] <= dch_fifo_out[DCH-1:0];
assign rid[SIDW-1:0] = dch_fifo_reg[SIDW:1];
assign rresp[1:0] = 2'b00;
assign rvalid = ~dch_fifo_empty_reg;
assign rvalid_rready = rvalid & rready;
assign rdata[SDW-1:0] = dch_fifo_reg[DCH-1:SIDW+1];
assign rlast = dch_fifo_reg[0];
//# Transaction Stall
assign tran_stall = emesh_rd_wait_outb;
endmodule // axi_slave_rd

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/*
File: axi_slave_wr.v
This file is part of the Parallella FPGA Reference Design.
Copyright (C) 2013 Adapteva, Inc.
Contributed by Roman Trogan <support@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
//######################################################################
//# According to the standard (IHI0022D_amba_axi_protocol_spec):
//# If the interconnect combines write transactions from
//# different masters to one slave, it must ensure that it
//# forwards the write data in address order.
//#
//# This block was implemented based on the above statement and won't
//# work properly if the interconnect doesn't follow this rule.
//######################################################################
//# Currently not supported:
//# 1. non-valid data bytes in a given data size
//# 2. unaligned transfers
//# 3. WRAP burst type (is treated as FIXED)
//# 4. write data interleaving
//# 5. protection types
//# 6. atomic accesses
//# 7. memory types through AxCACHE encoding
//# !!! The block is implemented in a way it "ignores" any
//# !!! unsupported features, and produces uninterrupted
//# !!! conversion of the transfers. As a result, the AXI bus
//# !!! should always operate without deadlocks.
//# !!! If the master issues unsupported transfer, the data written
//# !!! into the destination is unpredictable.
module axi_slave_wr (/*AUTOARG*/
// Outputs
awready, wready, bid, bresp, bvalid, emesh_access_inb,
emesh_write_inb, emesh_datamode_inb, emesh_ctrlmode_inb,
emesh_dstaddr_inb, emesh_srcaddr_inb, emesh_data_inb,
// Inputs
aclk, eclk, reset, awid, awaddr, awlen, awsize, awburst, awlock,
awcache, awprot, awvalid, wid, wdata, wstrb, wlast, wvalid, bready,
emesh_wr_wait_outb
);
parameter SIDW = 12; //ID Width
parameter SAW = 32; //Address Bus Width
parameter SDW = 32; //Data Bus Width
parameter STW = 8; //Number of strobes
parameter ACH = SAW+SIDW+5; //Width of all used Write Address Signals
parameter AFW = 4; //Address channel Fifo address width
parameter DFW = 4; //Data channel Fifo address width
parameter BFW = 4; //Response channel Fifo address width
parameter DCH = SDW+1; //Width of all used Write Data Signals
//#########
//# Inputs
//#########
// global signals
input aclk; //clock source of the axi bus
input eclk; //clock source of emesh interface
input reset; //reset
//########################
//# Write address channel
//########################
input [SIDW-1:0] awid; //write address ID
input [SAW-1:0] awaddr; //write address
input [3:0] awlen; //burst lenght (the number of data transfers)
input [2:0] awsize; //burst size (the size of each transfer)
input [1:0] awburst; //burst type
input [1:0] awlock; //lock type (atomic characteristics)
input [3:0] awcache; //memory type
input [2:0] awprot; //protection type
input awvalid; //write address valid
//########################
//# Write data channel
//########################
input [SIDW-1:0] wid; //write ID tag (supported only in AXI3)
input [SDW-1:0] wdata;//write data
input [3:0] wstrb;//write strobes
input wlast; //write last. Indicates the last transfer in burst
input wvalid;//write valid
//########################
// Write response channel
//########################
input bready;//response ready
//##############################
//# From the emesh interface
//##############################
input emesh_wr_wait_outb;
//##########
//# Outputs
//##########
//########################
//# Write address channel
//########################
output awready; //write address ready
//########################
//# Write data channel
//########################
output wready; //write ready
//########################
// Write response channel
//########################
output [SIDW-1:0] bid; //response ID tag
output [1:0] bresp; //write response
output bvalid;//write response valid
//##############################
//# To the emesh interface
//##############################
output emesh_access_inb;
output emesh_write_inb;
output [1:0] emesh_datamode_inb;
output [3:0] emesh_ctrlmode_inb;
output [31:0] emesh_dstaddr_inb;
output [31:0] emesh_srcaddr_inb;
output [31:0] emesh_data_inb;
/*AUTOINPUT*/
/*AUTOWIRE*/
//#########
//# Regs
//#########
reg dch_wlast_reg;
reg [DCH-1:0] dch_fifo_in;
reg wvalid_wready_reg;
reg [DCH-1:0] dch_fifo_reg;
reg tran_go;
reg tran_go_reg;
reg [SDW-1:0] wdata_algn_reg;
reg [SAW-1:0] tran_addr_reg;
reg [1:0] tran_mode_reg;
reg [SDW-1:0] algn_byte;
reg [SIDW-1:0] bch_fifo_reg;
reg bch_fifo_empty_reg;
//#########
//# Wires
//#########
wire awready;
wire ach_fifo_empty;
wire [2:0] dalgn_ctrl;
wire wready;
wire wvalid_wready;
wire [DCH-1:0] dch_data_in;
wire [DCH-1:0] dch_fifo_out;
wire dch_fifo_empty;
wire dch_fifo_full;
wire dch_fifo_wr;
wire dch_fifo_rd;
wire dch_wlast; //Indicates last data of burst (out of fifo_dch)
wire [SIDW-1:0] bch_data_in;
wire [SIDW-1:0] bch_fifo_out;
wire bch_fifo_empty;
wire bch_fifo_full;
wire bch_fifo_wr;
wire bch_fifo_rd;
wire bch_advance;
wire bvalid_bready;
wire [SDW-1:0] wdata_ec;
wire [SDW-1:0] algn_hword;
wire [SDW-1:0] wdata_algn;
wire tran_stall;
wire byte_tran;
wire hword_tran;
wire [SAW-1:0] tran_addr;
wire [1:0] tran_mode;
wire [SIDW-1:0] awid_ec;
//#######################################
//# Address channel synchronization FIFO
//#######################################
/*axi_slave_addrch AUTO_TEMPLATE(.aclk (aclk),
.addr (awaddr[]),
.ach_fifo_empty (ach_fifo_empty),
.alen_ec (),
.a\(.*\) (aw\1[]),
.tran_last (dch_wlast),
.new_addr_sel (),
.tran_go (dch_fifo_rd),
.byte_tran (),
.hword_tran (),
.word_tran (),
.dalgn_ctrl (),
);
*/
axi_slave_addrch axi_slave_addrch(/*AUTOINST*/
// Outputs
.aready (awready), // Templated
.ach_fifo_empty (ach_fifo_empty), // Templated
.tran_addr (tran_addr[SAW-1:0]),
.tran_mode (tran_mode[1:0]),
.dalgn_ctrl (), // Templated
.byte_tran (), // Templated
.hword_tran (), // Templated
.word_tran (), // Templated
.aid_ec (awid_ec[SIDW-1:0]), // Templated
.alen_ec (), // Templated
.new_addr_sel (), // Templated
// Inputs
.aclk (aclk), // Templated
.eclk (eclk),
.reset (reset),
.avalid (awvalid), // Templated
.addr (awaddr[SAW-1:0]), // Templated
.aid (awid[SIDW-1:0]), // Templated
.alen (awlen[3:0]), // Templated
.asize (awsize[2:0]), // Templated
.aburst (awburst[1:0]), // Templated
.tran_last (dch_wlast), // Templated
.tran_stall (tran_stall),
.tran_go (dch_fifo_rd)); // Templated
//#######################################
//# Data channel synchronization FIFO
//#######################################
assign wready = ~dch_fifo_full;
assign wvalid_wready = wvalid & wready;
assign dch_data_in[DCH-1:0] = {wdata[SDW-1:0],wlast};
//# Since according to the standard it is possible that
//# data will arive before the address, we are checking address
//# availability prior to reading the data from the fifo.
assign dch_fifo_rd = ~(dch_fifo_empty | ach_fifo_empty | tran_stall);
//# The data is sampled before entering FIFO to prevent timing issues
always @ (posedge aclk)
if(~dch_fifo_full)
dch_fifo_in[DCH-1:0] <= dch_data_in[DCH-1:0];
always @ (posedge aclk or posedge reset)
if(reset)
wvalid_wready_reg <= 1'b0;
else if(~dch_fifo_full)
wvalid_wready_reg <= wvalid_wready;
assign dch_fifo_wr = wvalid_wready_reg & ~dch_fifo_full;
assign dch_wlast = dch_fifo_rd & dch_fifo_out[0];
always @ (posedge eclk or posedge reset)
if(reset)
dch_wlast_reg <= 1'b0;
else if(~tran_stall)
dch_wlast_reg <= dch_wlast;
/*fifo AUTO_TEMPLATE(.rd_clk (eclk),
.wr_clk (aclk),
.wr_data (dch_fifo_in[DCH-1:0]),
.rd_data (dch_fifo_out[DCH-1:0]),
.rd_fifo_empty (dch_fifo_empty),
.wr_fifo_full (dch_fifo_full),
.wr_write (dch_fifo_wr),
.rd_read (dch_fifo_rd),
);
*/
fifo #(.DW(DCH), .AW(DFW)) fifo_dch(/*AUTOINST*/
// Outputs
.rd_data (dch_fifo_out[DCH-1:0]), // Templated
.rd_fifo_empty (dch_fifo_empty), // Templated
.wr_fifo_full (dch_fifo_full), // Templated
// Inputs
.reset (reset),
.wr_clk (aclk), // Templated
.rd_clk (eclk), // Templated
.wr_write (dch_fifo_wr), // Templated
.wr_data (dch_fifo_in[DCH-1:0]), // Templated
.rd_read (dch_fifo_rd)); // Templated
//# The data is sampled after exiting FIFO to prevent timing issues
always @ (posedge eclk)
if(~tran_stall)
dch_fifo_reg[DCH-1:0] <= dch_fifo_out[DCH-1:0];
always @ (posedge eclk or posedge reset)
if(reset)
begin
tran_go <= 1'b0;
tran_go_reg <= 1'b0;
end
else if(~tran_stall)
begin
tran_go <= dch_fifo_rd;
tran_go_reg <= tran_go;
end
//########################
//# AXI-EMESH conversion
//########################
//# Data Alignment for the EMESH protocol
assign wdata_ec[SDW-1:0] = dch_fifo_reg[DCH-1:DCH-SDW];
always @ (dalgn_ctrl[1:0] or wdata_ec[31:0])
begin
casez (dalgn_ctrl[1:0])
2'b00 : algn_byte[SDW-1:0] = {{(SDW-8){1'b0}},wdata_ec[7:0]};
2'b01 : algn_byte[SDW-1:0] = {{(SDW-8){1'b0}},wdata_ec[15:8]};
2'b10 : algn_byte[SDW-1:0] = {{(SDW-8){1'b0}},wdata_ec[23:16]};
2'b11 : algn_byte[SDW-1:0] = {{(SDW-8){1'b0}},wdata_ec[31:24]};
default: algn_byte[SDW-1:0] = {{(SDW-8){1'b0}},wdata_ec[7:0]};
endcase // casez (dalgn_ctrl[1:0])
end
assign algn_hword[SDW-1:0] = dalgn_ctrl[1] ? {{(SDW/2){1'b0}},wdata_ec[31:16]} :
{{(SDW/2){1'b0}},wdata_ec[15:0]};
assign wdata_algn[SDW-1:0] = byte_tran ? algn_byte[SDW-1:0] :
hword_tran ? algn_hword[SDW-1:0] :
wdata_ec[SDW-1:0];
assign byte_tran = (tran_mode[1:0] == 2'b00);
assign hword_tran = (tran_mode[1:0] == 2'b01);
assign dalgn_ctrl[2:0] = tran_addr[2:0];
always @ (posedge eclk)
if(tran_go & ~tran_stall)
begin
wdata_algn_reg[SDW-1:0] <= wdata_algn[SDW-1:0];
tran_addr_reg[SAW-1:0] <= tran_addr[SAW-1:0];
tran_mode_reg[1:0] <= tran_mode[1:0];
end
//#############################
//# Emesh transaction creation
//#############################
assign emesh_dstaddr_inb[31:0] = tran_addr_reg[SAW-1:0];
assign emesh_srcaddr_inb[31:0] = {(32){1'b0}};
assign emesh_data_inb[31:0] = wdata_algn_reg[31:0];
assign emesh_datamode_inb[1:0] = tran_mode_reg[1:0];
assign emesh_ctrlmode_inb[3:0] = 4'b0000;
assign emesh_write_inb = 1'b1;
assign emesh_access_inb = tran_go_reg & ~tran_stall;
//#########################################
//# Response channel synchronization FIFO
//#########################################
assign bid[SIDW-1:0] = bch_fifo_reg[SIDW-1:0];
assign bresp[1:0] = 2'b00;
assign bvalid = ~bch_fifo_empty_reg;
assign bvalid_bready = bvalid & bready;
assign bch_data_in[SIDW-1:0] = awid_ec[SIDW-1:0];
assign bch_fifo_wr = dch_wlast_reg & ~tran_stall;
assign bch_fifo_rd = ~bch_fifo_empty & (~bvalid | bvalid_bready);
assign bch_advance = bvalid_bready | ~bvalid;
/*fifo AUTO_TEMPLATE(.rd_clk (aclk),
.wr_clk (eclk),
.wr_data (bch_data_in[SIDW-1:0]),
.rd_data (bch_fifo_out[SIDW-1:0]),
.rd_fifo_empty (bch_fifo_empty),
.wr_fifo_full (bch_fifo_full),
.wr_write (bch_fifo_wr),
.rd_read (bch_fifo_rd),
);
*/
fifo #(.DW(SIDW), .AW(BFW)) fifo_bch(/*AUTOINST*/
// Outputs
.rd_data (bch_fifo_out[SIDW-1:0]), // Templated
.rd_fifo_empty (bch_fifo_empty), // Templated
.wr_fifo_full (bch_fifo_full), // Templated
// Inputs
.reset (reset),
.wr_clk (eclk), // Templated
.rd_clk (aclk), // Templated
.wr_write (bch_fifo_wr), // Templated
.wr_data (bch_data_in[SIDW-1:0]), // Templated
.rd_read (bch_fifo_rd)); // Templated
//# The data is sampled after exiting FIFO to prevent timing issues
always @ (posedge aclk or posedge reset)
if(reset)
bch_fifo_empty_reg <= 1'b1;
else if(bch_advance)
bch_fifo_empty_reg <= bch_fifo_empty;
always @ (posedge aclk)
if (bch_advance)
bch_fifo_reg[SIDW-1:0] <= bch_fifo_out[SIDW-1:0];
//##################################################
//# Both Address and Data channels can be "stalled"
//# as a result of emesh_wait or non-ready response
//# channel
//##################################################
assign tran_stall = emesh_wr_wait_outb | bch_fifo_full;
endmodule // axi_slave_wr

205
clocks/hdl/io_clock_gen_600mhz.v
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@ -1,205 +0,0 @@
// file: io_clock_gen_600mhz.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1___600.000______0.000______50.0_______83.768_____87.180
// CLK_OUT2___300.000______0.000______50.0_______94.862_____87.180
// CLK_OUT3____75.000______0.000______50.0______122.158_____87.180
// CLK_OUT4___300.000_____90.000______50.0_______94.862_____87.180
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "io_clock_gen_600mhz,clk_wiz_v3_6,{component_name=io_clock_gen_600mhz,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=4,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}" *)
module io_clock_gen_600mhz
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
output CLK_OUT2,
output CLK_OUT3,
output CLK_OUT4,
// Status and control signals
input RESET,
output LOCKED
);
// Input buffering
//------------------------------------
BUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));
// Clocking primitive
//------------------------------------
// Instantiation of the MMCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire clkfbout;
wire clkfbout_buf;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1b_unused;
wire clkout2b_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (12.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (2.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (4),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKOUT2_DIVIDE (16),
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT2_USE_FINE_PS ("FALSE"),
.CLKOUT3_DIVIDE (4),
.CLKOUT3_PHASE (90.000),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKOUT3_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (10.0),
.REF_JITTER1 (0.010))
mmcm_adv_inst
// Output clocks
(.CLKFBOUT (clkfbout),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clkout0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf),
.CLKIN1 (clkin1),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (LOCKED),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (RESET));
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf),
.I (clkfbout));
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkout0));
BUFG clkout2_buf
(.O (CLK_OUT2),
.I (clkout1));
BUFG clkout3_buf
(.O (CLK_OUT3),
.I (clkout2));
BUFG clkout4_buf
(.O (CLK_OUT4),
.I (clkout3));
endmodule

56
common/hdl/debouncer.v
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@ -1,56 +0,0 @@
/*
Copyright (C) 2013 Adapteva, Inc.
Contributed by Andreas Olofsson <support@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module debouncer (/*AUTOARG*/
// Outputs
clean_out,
// Inputs
clk, noisy_in
);
parameter N = 20; //debouncer counter width
input clk; //system clock
input noisy_in; //bouncy input (convention says it goes low when button is pressed)
output clean_out; //clean output (positive polarity)
wire expired;
wire sync_in;
reg [N-1:0] counter;
wire filtering;
synchronizer #(1) synchronizer(.out (sync_in),
.in (noisy_in),
.clk (clk),
.reset (1'b0));
//Counter that resets when sync_in is low
always @ (posedge clk)
if(sync_in)
counter[N-1:0]={(N){1'b1}};
else if(filtering)
counter[N-1:0]=counter[N-1:0]-1'b1;
assign filtering =|counter[N-1:0];
assign clean_out = filtering | sync_in;
endmodule // debouncer

49
common/hdl/mux4.v
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/*
Copyright (C) 2013 Adapteva, Inc.
Contributed by Andreas Olofsson <support@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module mux4(/*AUTOARG*/
// Outputs
out,
// Inputs
in0, in1, in2, in3, sel0, sel1, sel2, sel3
);
parameter DW=99;
//data inputs
input [DW-1:0] in0;
input [DW-1:0] in1;
input [DW-1:0] in2;
input [DW-1:0] in3;
//select inputs
input sel0;
input sel1;
input sel2;
input sel3;
output [DW-1:0] out;
assign out[DW-1:0] = ({(DW){sel0}} & in0[DW-1:0] |
{(DW){sel1}} & in1[DW-1:0] |
{(DW){sel2}} & in2[DW-1:0] |
{(DW){sel3}} & in3[DW-1:0]);
endmodule // mux4

77
common/hdl/pulse2pulse.v
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/*
Copyright (C) 2013 Adapteva, Inc.
Contributed by Andreas Olofsson <support@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module pulse2pulse(/*AUTOARG*/
// Outputs
out,
// Inputs
inclk, outclk, in, reset
);
//clocks
input inclk;
input outclk;
input in;
output out;
//reset
input reset;
wire intoggle;
wire insync;
//pulse to toggle
pulse2toggle pulse2toggle(
// Outputs
.out (intoggle),
// Inputs
.clk (inclk),
.in (in),
.reset (reset));
//metastability synchronizer
synchronizer #(1) synchronizer(
// Outputs
.out (insync),
// Inputs
.in (intoggle),
.clk (outclk),
.reset (reset));
//toogle to pulse
toggle2pulse toggle2pulse(
// Outputs
.out (out),
// Inputs
.clk (outclk),
.in (insync),
.reset (reset));
endmodule // pulse2pulse

58
common/hdl/pulse2toggle.v
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@ -1,58 +0,0 @@
/*
Copyright (C) 2013 Adapteva, Inc.
Contributed by Andreas Olofsson <support@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module pulse2toggle(/*AUTOARG*/
// Outputs
out,
// Inputs
clk, in, reset
);
//clocks
input clk;
input in;
output out;
//reset
input reset;
reg out;
wire toggle;
//if input goes high, toggle output
//note1: input can only be high for one clock cycle
//note2: be careful with clock gating
assign toggle = in ? ~out :
out;
always @ (posedge clk or posedge reset)
if(reset)
out <= 1'b0;
else
out <= toggle;
endmodule // pulse2toggle

58
common/hdl/synchronizer.v
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/*
Copyright (C) 2013 Adapteva, Inc.
Contributed by Andreas Olofsson <support@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module synchronizer #(parameter DW=32) (/*AUTOARG*/
// Outputs
out,
// Inputs
in, clk, reset
);
//Input Side
input [DW-1:0] in;
input clk;
input reset;//asynchronous signal
//Output Side
output [DW-1:0] out;
reg [DW-1:0] sync_reg0;
reg [DW-1:0] sync_reg1;
reg [DW-1:0] out;
//Synchronization between clock domain
//We use two flip-flops for metastability improvement
always @ (posedge clk or posedge reset)
if(reset)
begin
sync_reg0[DW-1:0] <= {(DW){1'b0}};
sync_reg1[DW-1:0] <= {(DW){1'b0}};
out[DW-1:0] <= {(DW){1'b0}};
end
else
begin
sync_reg0[DW-1:0] <= in[DW-1:0];
sync_reg1[DW-1:0] <= sync_reg0[DW-1:0];
out[DW-1:0] <= sync_reg1[DW-1:0];
end
endmodule // clock_synchronizer

50
common/hdl/toggle2pulse.v
View File

@ -1,50 +0,0 @@
/*
Copyright (C) 2013 Adapteva, Inc.
Contributed by Andreas Olofsson <support@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module toggle2pulse(/*AUTOARG*/
// Outputs
out,
// Inputs
clk, in, reset
);
//clocks
input clk;
input in;
output out;
//reset
input reset;
reg out_reg;
always @ (posedge clk or posedge reset)
if(reset)
out_reg <= 1'b0;
else
out_reg <= in;
assign out = in ^ out_reg;
endmodule

637
earb/component.xml Normal file
View File

@ -0,0 +1,637 @@
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<spirit:displayName>Component Name</spirit:displayName>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">edistrib_v1_0</spirit:value>
</spirit:parameter>
</spirit:parameters>
<spirit:vendorExtensions>
<xilinx:coreExtensions>
<xilinx:supportedFamilies>
<xilinx:family xilinx:lifeCycle="Pre-Production">zynq</xilinx:family>
</xilinx:supportedFamilies>
<xilinx:taxonomies>
<xilinx:taxonomy>/BaseIP</xilinx:taxonomy>
</xilinx:taxonomies>
<xilinx:displayName>earb_v1_0</xilinx:displayName>
<xilinx:vendorDisplayName>Adapteva, Inc.</xilinx:vendorDisplayName>
<xilinx:vendorURL>http://www.adapteva.com</xilinx:vendorURL>
<xilinx:coreRevision>4</xilinx:coreRevision>
<xilinx:upgrades>
<xilinx:canUpgradeFrom>user.org:user:edistrib:1.0</xilinx:canUpgradeFrom>
</xilinx:upgrades>
<xilinx:coreCreationDateTime>2014-11-17T20:37:04Z</xilinx:coreCreationDateTime>
<xilinx:tags>
<xilinx:tag xilinx:name="adapteva.com:Adapteva:earb:1.0_ARCHIVE_LOCATION">/mnt/windowsC/Adapteva/Parallella/parallella-hwelink/fpga/src/earb/ip</xilinx:tag>
</xilinx:tags>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2014.3</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="0910adfc"/>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="bd7329d4"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="ced5cce0"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="194e166d"/>
</xilinx:packagingInfo>
</spirit:vendorExtensions>
</spirit:component>

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/*
File: earb.v
This file is part of the Parallella Project.
Copyright (C) 2014 Adapteva, Inc.
Contributed by Fred Huettig <fred@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
/*
########################################################################
EPIPHANY eMesh Arbiter
########################################################################
This block takes three FIFO inputs (write, read request, read response),
arbitrates between the active channels, and forwards the result on to
the transmit channel.
The arbitration order is (fixed, highest to lowest)
1) read responses
2) read requests
3) writes
*/
module earb (/*AUTOARG*/
// Outputs
emwr_rd_en, emrq_rd_en, emrr_rd_en, emm_tx_access, emm_tx_write,
emm_tx_datamode, emm_tx_ctrlmode, emm_tx_dstaddr, emm_tx_srcaddr,
emm_tx_data,
// Inputs
clock, reset, emwr_rd_data, emwr_empty, emrq_rd_data, emrq_empty,
emrr_rd_data, emrr_empty, emm_tx_rd_wait, emm_tx_wr_wait, emtx_ack
);
// TX clock
input clock;
input reset;
// FIFO slave port, writes
input [102:0] emwr_rd_data;
output emwr_rd_en;
input emwr_empty;
// FIFO slave port, read requests
input [102:0] emrq_rd_data;
output emrq_rd_en;
input emrq_empty;
// FIFO slave port, read responses
input [102:0] emrr_rd_data;
output emrr_rd_en;
input emrr_empty;
// eMesh master port, to TX
output emm_tx_access;
output emm_tx_write;
output [1:0] emm_tx_datamode;
output [3:0] emm_tx_ctrlmode;
output [31:0] emm_tx_dstaddr;
output [31:0] emm_tx_srcaddr;
output [31:0] emm_tx_data;
input emm_tx_rd_wait;
input emm_tx_wr_wait;
// Ack from TX protocol module
input emtx_ack;
// Control bits inputs (none)
// output wires
wire emm_tx_access;
wire emm_tx_write;
wire [1:0] emm_tx_datamode;
wire [3:0] emm_tx_ctrlmode;
wire [31:0] emm_tx_dstaddr;
wire [31:0] emm_tx_srcaddr;
wire [31:0] emm_tx_data;
//############
//# Arbitrate & forward
//############
reg ready;
reg [102:0] fifo_data;
// priority-based ready signals
wire rr_ready = ~emrr_empty & ~emm_tx_wr_wait;
wire rq_ready = ~emrq_empty & ~emm_tx_rd_wait & ~rr_ready;
wire wr_ready = ~emwr_empty & ~emm_tx_wr_wait & ~rr_ready & ~rq_ready;
// FIFO read enables, when we're idle or done with the current datum
wire emrr_rd_en = rr_ready & (~ready | emtx_ack);
wire emrq_rd_en = rq_ready & (~ready | emtx_ack);
wire emwr_rd_en = wr_ready & (~ready | emtx_ack);
always @ (posedge clock) begin
if( reset ) begin
ready <= 1'b0;
fifo_data <= 'd0;
end else begin
if( emrr_rd_en ) begin
ready <= 1'b1;
fifo_data <= emrr_rd_data;
end else if( emrq_rd_en ) begin
ready <= 1'b1;
fifo_data <= emrq_rd_data;
end else if( emwr_rd_en ) begin
ready <= 1'b1;
fifo_data <= emwr_rd_data;
end else if( emtx_ack ) begin
ready <= 1'b0;
end
end // else: !if( reset )
end // always @ (posedge clock)
//#############################
//# Break-out the emesh signals
//#############################
assign emm_tx_access = ready;
assign emm_tx_write = fifo_data[102];
assign emm_tx_datamode = fifo_data[101:100];
assign emm_tx_ctrlmode = fifo_data[99:96];
assign emm_tx_dstaddr = fifo_data[95:64];
assign emm_tx_srcaddr = fifo_data[63:32];
assign emm_tx_data = fifo_data[31:0];
endmodule // earb

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earb/ip_prj/ip_prj.xpr Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2014.3 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="2" Path="/mnt/windowsC/Adapteva/Parallella/parallella-hwelink/fpga/src/earb/ip_prj/ip_prj.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="e4973d5c008040ea80e0cdca971adde3"/>
<Option Name="Part" Val="xc7z020clg400-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="BoardPart" Val=""/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="IPRepoPath" Val="$PPRDIR/../../../src"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../hdl/earb.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../component.xml">
<FileInfo SFType="IPXACT"/>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="earb"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Filter Type="Srcs"/>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="earb"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="QuestaSim/ModelSim Simulator"/>
</Simulator>
<Simulator Name="IES">
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
</Simulator>
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="9">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2014"/>
<Step Id="synth_design"/>
</Strategy>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" State="current" SynthRun="synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
</Run>
</Runs>
</Project>

12
earb/xgui/earb_v1_0.tcl Normal file
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# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
set Component_Name [ ipgui::add_param $IPINST -name "Component_Name" -display_name {Component Name}]
set_property tooltip {Component Name} ${Component_Name}
#Adding Page
set Page_0 [ ipgui::add_page $IPINST -name "Page 0" -display_name {Page 0}]
set_property tooltip {Page 0} ${Page_0}
}

12
earb/xgui/edistrib_v1_0.tcl Normal file
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# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
set Component_Name [ ipgui::add_param $IPINST -name "Component_Name" -display_name {Component Name}]
set_property tooltip {Component Name} ${Component_Name}
#Adding Page
set Page_0 [ ipgui::add_page $IPINST -name "Page 0" -display_name {Page 0}]
set_property tooltip {Page 0} ${Page_0}
}

773
ecfg/component.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>adapteva.com</spirit:vendor>
<spirit:library>Adapteva</spirit:library>
<spirit:name>eCfg</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>signal_reset</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>reset</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>POLARITY</spirit:name>
<spirit:value spirit:format="string" spirit:resolve="immediate" spirit:id="BUSIFPARAM_VALUE.SIGNAL_RESET.POLARITY" spirit:choiceRef="choices_1">ACTIVE_HIGH</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>ecfg_cclk</spirit:name>
<spirit:busType spirit:vendor="adapteva.com" spirit:library="Adapteva" spirit:name="eClockCfg" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="adapteva.com" spirit:library="Adapteva" spirit:name="eClockCfg_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>div</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ecfg_cclk_div</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>pllcfg</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ecfg_cclk_pllcfg</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>en</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ecfg_cclk_en</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>ecfg</spirit:name>
<spirit:busType spirit:vendor="adapteva.com" spirit:library="Adapteva" spirit:name="eConfig" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="adapteva.com" spirit:library="Adapteva" spirit:name="eConfig_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>sw_reset</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ecfg_sw_reset</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>tx_enable</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ecfg_tx_enable</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>tx_mmu_mode</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ecfg_tx_mmu_mode</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>tx_gpio_mode</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ecfg_tx_gpio_mode</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>tx_ctrl_mode</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ecfg_tx_ctrl_mode</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>tx_clkdiv</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ecfg_tx_clkdiv</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>rx_enable</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ecfg_rx_enable</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>rx_mmu_mode</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ecfg_rx_mmu_mode</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>rx_gpio_mode</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ecfg_rx_gpio_mode</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>rx_loopback_mode</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ecfg_rx_loopback_mode</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>coreid</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ecfg_coreid</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>datain</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ecfg_datain</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>dataout</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ecfg_dataout</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>mi</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="bram_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>EN</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>mi_en</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DOUT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>mi_dout</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DIN</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>mi_din</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WE</spirit:name>
</spirit:logicalPort>
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<spirit:name>mi_we</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>mi_addr</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>mi_clk</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>mi_rst</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>xilinx_verilogsynthesis</spirit:name>
<spirit:displayName>Verilog Synthesis</spirit:displayName>
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
<spirit:language>verilog</spirit:language>
<spirit:modelName>ecfg</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_verilogsynthesis_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>d52c2edc</spirit:value>
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<spirit:displayName>Verilog Simulation</spirit:displayName>
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
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<spirit:view>
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<spirit:displayName>UI Layout</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
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<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
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<spirit:value>cab9d07b</spirit:value>
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</spirit:parameters>
</spirit:view>
</spirit:views>
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<spirit:port>
<spirit:name>mi_dout</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="immediate">31</spirit:left>
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>reg</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>ecfg_sw_reset</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>ecfg_tx_enable</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>ecfg_tx_mmu_mode</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>ecfg_tx_gpio_mode</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>ecfg_tx_ctrl_mode</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="immediate">3</spirit:left>
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
</spirit:vector>
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<spirit:wireTypeDef>
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<spirit:name>mi_rst</spirit:name>
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<spirit:name>reset</spirit:name>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:name>mi_en</spirit:name>
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<spirit:name>mi_we</spirit:name>
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</spirit:port>
<spirit:port>
<spirit:name>mi_addr</spirit:name>
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<spirit:direction>in</spirit:direction>
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<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.RFAW&apos;)) - 1)">11</spirit:left>
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</spirit:vector>
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<spirit:wireTypeDef>
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</spirit:port>
<spirit:port>
<spirit:name>mi_din</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="immediate">31</spirit:left>
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
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<spirit:driver>
<spirit:defaultValue>8</spirit:defaultValue>
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<spirit:port>
<spirit:name>ecfg_datain</spirit:name>
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</spirit:vector>
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<spirit:modelParameters>
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
<spirit:name>E_VERSION</spirit:name>
<spirit:displayName>E Version</spirit:displayName>
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.E_VERSION" spirit:bitStringLength="32">0x00000000</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>IDW</spirit:name>
<spirit:displayName>Idw</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IDW">12</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>RFAW</spirit:name>
<spirit:displayName>Rfaw</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RFAW">12</spirit:value>
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<spirit:choices>
<spirit:choice>
<spirit:name>choices_0</spirit:name>
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<spirit:choice>
<spirit:name>choices_1</spirit:name>
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
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<spirit:parameter>
<spirit:name>E_VERSION</spirit:name>
<spirit:displayName>E Version</spirit:displayName>
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.E_VERSION" spirit:order="1600" spirit:bitStringLength="32">0x00000000</spirit:value>
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<spirit:parameter>
<spirit:name>Component_Name</spirit:name>
<spirit:displayName>Component Name</spirit:displayName>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">ecfg_v1_0</spirit:value>
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156
ecfg/hdl/ecfg.v
View File

@ -32,10 +32,9 @@
10 - reserved
11 - reserved
[7:4] Transmit control mode for eMesh
[9:8] 00 - No division, full speed
01 - Divide by 2
10 - Reserved
11 - Reserved
[11:8] 0000 - No division, full speed
0001 - Divide by 2
Others - Reserved
-------------------------------------------------------------
ESYSCFGRX ***Elink receiver configuration***
[0] 0 - link RX disable
@ -51,7 +50,7 @@
-------------------------------------------------------------
ESYSCFGCLK ***Epiphany clock frequency setting***
[3:0] Output divider
0000 - CLock turned off
0000 - Clock turned off
0001 - CLKIN/64
0010 - CLKIN/32
0011 - CLKIN/16
@ -86,25 +85,26 @@
########################################################################
*/
`define E_REG_SYSRESET 20'hf0340
`define E_REG_SYSCFGTX 20'hf0344
`define E_REG_SYSCFGRX 20'hf0348
`define E_REG_SYSCFGCLK 20'hf034c
`define E_REG_SYSCOREID 20'hf0350
`define E_REG_SYSVERSION 20'hf0354
`define E_REG_SYSDATAIN 20'hf0358
`define E_REG_SYSDATAOUT 20'hf035c
`define E_VERSION 32'h01_02_03_04
// These are WORD addresses
`define E_REG_SYSRESET 10'h010
`define E_REG_SYSCFGTX 10'h011
`define E_REG_SYSCFGRX 10'h012
`define E_REG_SYSCFGCLK 10'h013
`define E_REG_SYSCOREID 10'h014
`define E_REG_SYSVERSION 10'h015
`define E_REG_SYSDATAIN 10'h016
`define E_REG_SYSDATAOUT 10'h017
module ecfg (/*AUTOARG*/
// Outputs
mi_data_out, ecfg_sw_reset, ecfg_tx_enable, ecfg_tx_mmu_mode,
mi_dout, ecfg_sw_reset, ecfg_tx_enable, ecfg_tx_mmu_mode,
ecfg_tx_gpio_mode, ecfg_tx_ctrl_mode, ecfg_tx_clkdiv,
ecfg_rx_enable, ecfg_rx_mmu_mode, ecfg_rx_gpio_mode,
ecfg_rx_loopback_mode, ecfg_cclk_en, ecfg_cclk_div,
ecfg_cclk_pllcfg, ecfg_coreid, ecfg_dataout,
// Inputs
param_coreid, clk, reset, mi_access, mi_write, mi_addr, mi_data_in
param_coreid, mi_clk, mi_rst, mi_en, mi_we, mi_addr, mi_din, reset,
ecfg_datain
);
//Register file parameters
@ -113,12 +113,11 @@ module ecfg (/*AUTOARG*/
COMPILE TIME PARAMETERS
######################################################################
*/
parameter EMAW = 12; //mmu table address width
parameter EDW = 32; //Epiphany native data width
parameter EAW = 32; //Epiphany native address width
parameter IDW = 12; //Elink ID (row,column coordinate)
parameter RFAW = 5; //Number of registers=2^RFAW
parameter E_VERSION = 32'h00_00_00_00; // FPGA gen:plat:type:rev
parameter IDW = 12; // Elink ID (row,column coordinate)
parameter RFAW = 12; // Register file address width
// NB: The BRAM interface seems to provide BYTE addresses!
/*****************************/
/*STATIC CONFIG SIGNALS */
@ -128,14 +127,16 @@ parameter RFAW = 5; //Number of registers=2^RFAW
/*****************************/
/*SIMPLE MEMORY INTERFACE */
/*****************************/
input clk;
input mi_clk;
input mi_rst; // Not used
input mi_en;
input mi_we; // Single WE, must write full words!
input [RFAW-1:0] mi_addr;
input [31:0] mi_din;
output [31:0] mi_dout;
input reset;
input mi_access;
input mi_write;
input [19:0] mi_addr;
input [31:0] mi_data_in;
output [31:0] mi_data_out;
/*****************************/
/*ELINK CONTROL SIGNALS */
/*****************************/
@ -164,7 +165,8 @@ parameter RFAW = 5; //Number of registers=2^RFAW
output [11:0] ecfg_coreid; //core-id of fpga elink
//gpio
output [11:0] ecfg_dataout; //data for elink outputs {rd_wait,wr_wait,frame,data[7:0}
input [10:0] ecfg_datain; // data from elink inputs
output [10:0] ecfg_dataout; //data for elink outputs {rd_wait,wr_wait,frame,data[7:0]}
/*------------------------BODY CODE---------------------------------------*/
@ -174,11 +176,10 @@ parameter RFAW = 5; //Number of registers=2^RFAW
reg [4:0] ecfg_cfgrx_reg;
reg [7:0] ecfg_cfgclk_reg;
reg [11:0] ecfg_coreid_reg;
wire [31:0] ecfg_version_reg; //fixed read only constant
reg ecfg_reset_reg;
reg [11:0] ecfg_datain_reg;
reg [11:0] ecfg_dataout_reg;
reg [31:0] mi_data_out;
reg [31:0] mi_dout;
//wires
wire ecfg_read;
@ -188,7 +189,6 @@ parameter RFAW = 5; //Number of registers=2^RFAW
wire ecfg_cfgrx_match;
wire ecfg_cfgclk_match;
wire ecfg_coreid_match;
wire ecfg_version_match;
wire ecfg_datain_match;
wire ecfg_dataout_match;
wire ecfg_regmux;
@ -197,8 +197,6 @@ parameter RFAW = 5; //Number of registers=2^RFAW
wire ecfg_cfgrx_write;
wire ecfg_cfgclk_write;
wire ecfg_coreid_write;
wire ecfg_version_write;
wire ecfg_datain_write;
wire ecfg_dataout_write;
wire ecfg_rx_monitor_mode;
wire ecfg_reset_write;
@ -208,18 +206,18 @@ parameter RFAW = 5; //Number of registers=2^RFAW
/*****************************/
//read/write decode
assign ecfg_write = mi_access & mi_write;
assign ecfg_read = mi_access & ~mi_write;
assign ecfg_write = mi_en & mi_we;
assign ecfg_read = mi_en & ~mi_we;
//address match signals
assign ecfg_reset_match = mi_addr[19:0]==`E_REG_SYSRESET;
assign ecfg_cfgtx_match = mi_addr[19:0]==`E_REG_SYSCFGTX;
assign ecfg_cfgrx_match = mi_addr[19:0]==`E_REG_SYSCFGRX;
assign ecfg_cfgclk_match = mi_addr[19:0]==`E_REG_SYSCFGCLK;
assign ecfg_coreid_match = mi_addr[19:0]==`E_REG_SYSCOREID;
assign ecfg_version_match = mi_addr[19:0]==`E_REG_SYSVERSION;
assign ecfg_datain_match = mi_addr[19:0]==`E_REG_SYSDATAIN;
assign ecfg_dataout_match = mi_addr[19:0]==`E_REG_SYSDATAOUT;
assign ecfg_reset_match = mi_addr[RFAW-1:2]==`E_REG_SYSRESET;
assign ecfg_cfgtx_match = mi_addr[RFAW-1:2]==`E_REG_SYSCFGTX;
assign ecfg_cfgrx_match = mi_addr[RFAW-1:2]==`E_REG_SYSCFGRX;
assign ecfg_cfgclk_match = mi_addr[RFAW-1:2]==`E_REG_SYSCFGCLK;
assign ecfg_coreid_match = mi_addr[RFAW-1:2]==`E_REG_SYSCOREID;
assign ecfg_version_match = mi_addr[RFAW-1:2]==`E_REG_SYSVERSION;
assign ecfg_datain_match = mi_addr[RFAW-1:2]==`E_REG_SYSDATAIN;
assign ecfg_dataout_match = mi_addr[RFAW-1:2]==`E_REG_SYSDATAOUT;
//Write enables
assign ecfg_reset_write = ecfg_reset_match & ecfg_write;
@ -227,18 +225,16 @@ parameter RFAW = 5; //Number of registers=2^RFAW
assign ecfg_cfgrx_write = ecfg_cfgrx_match & ecfg_write;
assign ecfg_cfgclk_write = ecfg_cfgclk_match & ecfg_write;
assign ecfg_coreid_write = ecfg_coreid_match & ecfg_write;
assign ecfg_version_write = ecfg_version_match & ecfg_write;
assign ecfg_datain_write = ecfg_datain_match & ecfg_write;
assign ecfg_dataout_write = ecfg_dataout_match & ecfg_write;
//###########################
//# ESYSCFGTX
//###########################
always @ (posedge clk)
always @ (posedge mi_clk)
if(reset)
ecfg_cfgtx_reg[11:0] <= 12'b0;
else if (ecfg_cfgtx_write)
ecfg_cfgtx_reg[11:0] <= mi_data_in[11:0];
ecfg_cfgtx_reg[11:0] <= mi_din[11:0];
assign ecfg_tx_enable = ecfg_cfgtx_reg[0];
assign ecfg_tx_mmu_mode = ecfg_cfgtx_reg[1];
@ -249,11 +245,11 @@ parameter RFAW = 5; //Number of registers=2^RFAW
//###########################
//# ESYSCFGRX
//###########################
always @ (posedge clk)
always @ (posedge mi_clk)
if(reset)
ecfg_cfgrx_reg[4:0] <= 5'b0;
else if (ecfg_cfgrx_write)
ecfg_cfgrx_reg[4:0] <= mi_data_in[4:0];
ecfg_cfgrx_reg[4:0] <= mi_din[4:0];
assign ecfg_rx_enable = ecfg_cfgrx_reg[0];
assign ecfg_rx_mmu_mode = ecfg_cfgrx_reg[1];
@ -264,11 +260,11 @@ parameter RFAW = 5; //Number of registers=2^RFAW
//###########################
//# ESYSCFGCLK
//###########################
always @ (posedge clk)
always @ (posedge mi_clk)
if(reset)
ecfg_cfgclk_reg[7:0] <= 8'b0;
else if (ecfg_cfgclk_write)
ecfg_cfgclk_reg[7:0] <= mi_data_in[7:0];
ecfg_cfgclk_reg[7:0] <= mi_din[7:0];
assign ecfg_cclk_en = ~(ecfg_cfgclk_reg[3:0]==4'b0000);
assign ecfg_cclk_div[3:0] = ecfg_cfgclk_reg[3:0];
@ -277,47 +273,39 @@ parameter RFAW = 5; //Number of registers=2^RFAW
//###########################
//# ESYSCOREID
//###########################
always @ (posedge clk)
always @ (posedge mi_clk)
if(reset)
ecfg_coreid_reg[IDW-1:0] <= param_coreid[IDW-1:0];
else if (ecfg_coreid_write)
ecfg_coreid_reg[IDW-1:0] <= mi_data_in[IDW-1:0];
ecfg_coreid_reg[IDW-1:0] <= mi_din[IDW-1:0];
assign ecfg_coreid[IDW-1:0] = ecfg_coreid_reg[IDW-1:0];
//###########################
//# ESYSVERSION
//###########################
assign ecfg_version_reg[31:0] = `E_VERSION;
//###########################
//# ESYSDATAIN
//###########################
always @ (posedge clk)
if(reset)
ecfg_datain_reg[11:0] <= 12'b0;
else if (ecfg_datain_write)
ecfg_datain_reg[11:0] <= mi_data_in[11:0];
always @ (posedge mi_clk)
ecfg_datain_reg <= ecfg_datain;
//###########################
//# ESYSDATAOUT
//###########################
always @ (posedge clk)
always @ (posedge mi_clk)
if(reset)
ecfg_dataout_reg[11:0] <= 12'b0;
ecfg_dataout_reg <= 'd0;
else if (ecfg_dataout_write)
ecfg_dataout_reg[11:0] <= mi_data_in[11:0];
ecfg_dataout_reg <= mi_din[10:0];
assign ecfg_dataout[11:0] = ecfg_dataout_reg[11:0];
assign ecfg_dataout[10:0] = ecfg_dataout_reg[10:0];
//###########################
//# ESYSRESET
//###########################
always @ (posedge clk)
always @ (posedge mi_clk)
if(reset)
ecfg_reset_reg <= 1'b0;
else if (ecfg_reset_write)
ecfg_reset_reg <= mi_data_in[0];
ecfg_reset_reg <= mi_din[0];
assign ecfg_sw_reset = ecfg_reset_reg;
@ -325,18 +313,20 @@ parameter RFAW = 5; //Number of registers=2^RFAW
//# DATA READBACK MUX
//###############################
assign ecfg_reg_mux[31:0] = ({(32){ecfg_cfgtx_match}} & {20'b0,ecfg_cfgtx_reg[11:0]}) |
({(32){ecfg_cfgrx_match}} & {27'b0,ecfg_cfgrx_reg[4:0]}) |
({(32){ecfg_cfgclk_match}} & {24'b0,ecfg_cfgclk_reg[7:0]}) |
({(32){ecfg_coreid_match}} & {20'b0,ecfg_coreid_reg[11:0]}) |
({(32){ecfg_version_match}} & ecfg_version_reg[31:0]) |
({(32){ecfg_datain_match}} & {20'b0,ecfg_datain_reg[11:0]}) |
({(32){ecfg_dataout_match}} & {20'b0,ecfg_dataout_reg[11:0]}) ;
//Pipelineing readback
always @ (posedge clk)
always @ (posedge mi_clk)
if(ecfg_read)
mi_data_out[31:0] <= ecfg_reg_mux[31:0];
case(mi_addr[RFAW-1:2])
`E_REG_SYSRESET: mi_dout <= {31'b0, ecfg_reset_reg};
`E_REG_SYSCFGTX: mi_dout <= {20'b0, ecfg_cfgtx_reg[11:0]};
`E_REG_SYSCFGRX: mi_dout <= {27'b0, ecfg_cfgrx_reg[4:0]};
`E_REG_SYSCFGCLK: mi_dout <= {24'b0, ecfg_cfgclk_reg[7:0]};
`E_REG_SYSCOREID: mi_dout <= {{(32-IDW){1'b0}}, ecfg_coreid_reg[IDW-1:0]};
`E_REG_SYSVERSION: mi_dout <= E_VERSION;
`E_REG_SYSDATAIN: mi_dout <= {20'b0, ecfg_datain_reg[11:0]};
`E_REG_SYSDATAOUT: mi_dout <= {20'b0, ecfg_dataout_reg[11:0]};
default: mi_dout <= 32'd0;
endcase
endmodule // para_config

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ecfg/ip_prj/ip_prj.xpr Normal file
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@ -0,0 +1,88 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2014.3 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="2" Path="/mnt/windowsC/Adapteva/Parallella/parallella-hwelink/fpga/src/ecfg/ip_prj/ip_prj.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="f3ed1a6c6f154a94bb6f4e98e1dbccb6"/>
<Option Name="Part" Val="xc7z020clg400-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="BoardPart" Val=""/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="IPRepoPath" Val="$PPRDIR/../../../src"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../hdl/ecfg.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../component.xml">
<FileInfo SFType="IPXACT"/>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="ecfg"/>
<Option Name="TopRTLFile" Val="$PPRDIR/../hdl/ecfg.v"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Filter Type="Srcs"/>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="ecfg"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="QuestaSim/ModelSim Simulator"/>
</Simulator>
<Simulator Name="IES">
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
</Simulator>
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="9">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2014"/>
<Step Id="synth_design"/>
</Strategy>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" State="current" SynthRun="synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
</Run>
</Runs>
</Project>

60
ecfg/xgui/eCfg_v1_0.tcl Normal file
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@ -0,0 +1,60 @@
# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
set Component_Name [ ipgui::add_param $IPINST -name "Component_Name" -display_name {Component Name}]
set_property tooltip {Component Name} ${Component_Name}
#Adding Page
set Page_0 [ ipgui::add_page $IPINST -name "Page 0" -display_name {Page 0}]
set_property tooltip {Page 0} ${Page_0}
set RFAW [ ipgui::add_param $IPINST -name "RFAW" -parent ${Page_0} -display_name {Rfaw}]
set_property tooltip {Rfaw} ${RFAW}
set IDW [ ipgui::add_param $IPINST -name "IDW" -parent ${Page_0} -display_name {Idw}]
set_property tooltip {Idw} ${IDW}
set E_VERSION [ ipgui::add_param $IPINST -name "E_VERSION" -parent ${Page_0} -display_name {E Version}]
set_property tooltip {E Version} ${E_VERSION}
}
proc update_PARAM_VALUE.RFAW { PARAM_VALUE.RFAW } {
# Procedure called to update RFAW when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.RFAW { PARAM_VALUE.RFAW } {
# Procedure called to validate RFAW
return true
}
proc update_PARAM_VALUE.IDW { PARAM_VALUE.IDW } {
# Procedure called to update IDW when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.IDW { PARAM_VALUE.IDW } {
# Procedure called to validate IDW
return true
}
proc update_PARAM_VALUE.E_VERSION { PARAM_VALUE.E_VERSION } {
# Procedure called to update E_VERSION when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.E_VERSION { PARAM_VALUE.E_VERSION } {
# Procedure called to validate E_VERSION
return true
}
proc update_MODELPARAM_VALUE.E_VERSION { MODELPARAM_VALUE.E_VERSION PARAM_VALUE.E_VERSION } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.E_VERSION}] ${MODELPARAM_VALUE.E_VERSION}
}
proc update_MODELPARAM_VALUE.IDW { MODELPARAM_VALUE.IDW PARAM_VALUE.IDW } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.IDW}] ${MODELPARAM_VALUE.IDW}
}
proc update_MODELPARAM_VALUE.RFAW { MODELPARAM_VALUE.RFAW PARAM_VALUE.RFAW } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.RFAW}] ${MODELPARAM_VALUE.RFAW}
}

1973
ecfg_split/component.xml Normal file
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286
ecfg_split/hdl/ecfg_split.v Normal file
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@ -0,0 +1,286 @@
/*
Copyright (C) 2014 Adapteva, Inc.
Contributed by Fred Huettig <fred@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
//########################################################################
// EPIPHANY CONFIGURATION BUS SPLITTER
//########################################################################
/*
NOTE: This module is (hopefully) temporary, until Vivado gains the
ability (or I learn how) to have a custom interface with multiple
slaves. This issue has been raised with Xilinx.
*/
module ecfg_split(/*AUTOARG*/
// Outputs
slvcfg_datain, mcfg0_sw_reset, mcfg0_tx_enable, mcfg0_tx_mmu_mode,
mcfg0_tx_gpio_mode, mcfg0_tx_ctrl_mode, mcfg0_tx_clkdiv,
mcfg0_rx_enable, mcfg0_rx_mmu_mode, mcfg0_rx_gpio_mode,
mcfg0_rx_loopback_mode, mcfg0_coreid, mcfg0_dataout,
mcfg1_sw_reset, mcfg1_tx_enable, mcfg1_tx_mmu_mode,
mcfg1_tx_gpio_mode, mcfg1_tx_ctrl_mode, mcfg1_tx_clkdiv,
mcfg1_rx_enable, mcfg1_rx_mmu_mode, mcfg1_rx_gpio_mode,
mcfg1_rx_loopback_mode, mcfg1_coreid, mcfg1_dataout,
mcfg2_sw_reset, mcfg2_tx_enable, mcfg2_tx_mmu_mode,
mcfg2_tx_gpio_mode, mcfg2_tx_ctrl_mode, mcfg2_tx_clkdiv,
mcfg2_rx_enable, mcfg2_rx_mmu_mode, mcfg2_rx_gpio_mode,
mcfg2_rx_loopback_mode, mcfg2_coreid, mcfg2_dataout,
mcfg3_sw_reset, mcfg3_tx_enable, mcfg3_tx_mmu_mode,
mcfg3_tx_gpio_mode, mcfg3_tx_ctrl_mode, mcfg3_tx_clkdiv,
mcfg3_rx_enable, mcfg3_rx_mmu_mode, mcfg3_rx_gpio_mode,
mcfg3_rx_loopback_mode, mcfg3_coreid, mcfg3_dataout,
mcfg4_sw_reset, mcfg4_tx_enable, mcfg4_tx_mmu_mode,
mcfg4_tx_gpio_mode, mcfg4_tx_ctrl_mode, mcfg4_tx_clkdiv,
mcfg4_rx_enable, mcfg4_rx_mmu_mode, mcfg4_rx_gpio_mode,
mcfg4_rx_loopback_mode, mcfg4_coreid, mcfg4_dataout,
// Inputs
slvcfg_sw_reset, slvcfg_tx_enable, slvcfg_tx_mmu_mode,
slvcfg_tx_gpio_mode, slvcfg_tx_ctrl_mode, slvcfg_tx_clkdiv,
slvcfg_rx_enable, slvcfg_rx_mmu_mode, slvcfg_rx_gpio_mode,
slvcfg_rx_loopback_mode, slvcfg_coreid, slvcfg_dataout,
mcfg0_datain, mcfg1_datain, mcfg2_datain, mcfg3_datain,
mcfg4_datain
);
/*****************************/
/* Slave (input) Port */
/*****************************/
//RESET
input slvcfg_sw_reset;
//tx
input slvcfg_tx_enable; //enable signal for TX
input slvcfg_tx_mmu_mode; //enables MMU on transnmit path
input slvcfg_tx_gpio_mode; //forces TX input pins to constants
input [3:0] slvcfg_tx_ctrl_mode; //value for emesh ctrlmode tag
input [3:0] slvcfg_tx_clkdiv; //transmit clock divider
//rx
input slvcfg_rx_enable; //enable signal for rx
input slvcfg_rx_mmu_mode; //enables MMU on rx path
input slvcfg_rx_gpio_mode; //forces rx wait pins to constants
input slvcfg_rx_loopback_mode; //loops back tx to rx receiver (after serdes)
//coreid
input [11:0] slvcfg_coreid; //core-id of fpga elink
//gpio
output [10:0] slvcfg_datain; // data from elink inputs
input [10:0] slvcfg_dataout; //data for elink outputs {rd_wait,wr_wait,frame,data[7:0]}
/*************************************************/
/* Master (output) Port #0 */
/* NOTE: This is the only port that takes input */
/*************************************************/
//RESET
output mcfg0_sw_reset;
//tx
output mcfg0_tx_enable;
output mcfg0_tx_mmu_mode;
output mcfg0_tx_gpio_mode;
output [3:0] mcfg0_tx_ctrl_mode;
output [3:0] mcfg0_tx_clkdiv;
//rx
output mcfg0_rx_enable;
output mcfg0_rx_mmu_mode;
output mcfg0_rx_gpio_mode;
output mcfg0_rx_loopback_mode;
//coreid
output [11:0] mcfg0_coreid;
//gpio
input [10:0] mcfg0_datain;
output [10:0] mcfg0_dataout;
/*****************************/
/* Master (output) Port #1 */
/*****************************/
//RESET
output mcfg1_sw_reset;
//tx
output mcfg1_tx_enable;
output mcfg1_tx_mmu_mode;
output mcfg1_tx_gpio_mode;
output [3:0] mcfg1_tx_ctrl_mode;
output [3:0] mcfg1_tx_clkdiv;
//rx
output mcfg1_rx_enable;
output mcfg1_rx_mmu_mode;
output mcfg1_rx_gpio_mode;
output mcfg1_rx_loopback_mode;
//coreid
output [11:0] mcfg1_coreid;
//gpio
input [10:0] mcfg1_datain;
output [10:0] mcfg1_dataout;
/*****************************/
/* Master (output) Port #2 */
/*****************************/
//RESET
output mcfg2_sw_reset;
//tx
output mcfg2_tx_enable;
output mcfg2_tx_mmu_mode;
output mcfg2_tx_gpio_mode;
output [3:0] mcfg2_tx_ctrl_mode;
output [3:0] mcfg2_tx_clkdiv;
//rx
output mcfg2_rx_enable;
output mcfg2_rx_mmu_mode;
output mcfg2_rx_gpio_mode;
output mcfg2_rx_loopback_mode;
//coreid
output [11:0] mcfg2_coreid;
//gpio
input [10:0] mcfg2_datain;
output [10:0] mcfg2_dataout;
/*****************************/
/* Master (output) Port #3 */
/*****************************/
//RESET
output mcfg3_sw_reset;
//tx
output mcfg3_tx_enable;
output mcfg3_tx_mmu_mode;
output mcfg3_tx_gpio_mode;
output [3:0] mcfg3_tx_ctrl_mode;
output [3:0] mcfg3_tx_clkdiv;
//rx
output mcfg3_rx_enable;
output mcfg3_rx_mmu_mode;
output mcfg3_rx_gpio_mode;
output mcfg3_rx_loopback_mode;
//coreid
output [11:0] mcfg3_coreid;
//gpio
input [10:0] mcfg3_datain;
output [10:0] mcfg3_dataout;
/*****************************/
/* Master (output) Port #4 */
/*****************************/
//RESET
output mcfg4_sw_reset;
//tx
output mcfg4_tx_enable;
output mcfg4_tx_mmu_mode;
output mcfg4_tx_gpio_mode;
output [3:0] mcfg4_tx_ctrl_mode;
output [3:0] mcfg4_tx_clkdiv;
//rx
output mcfg4_rx_enable;
output mcfg4_rx_mmu_mode;
output mcfg4_rx_gpio_mode;
output mcfg4_rx_loopback_mode;
//coreid
output [11:0] mcfg4_coreid;
//gpio
input [10:0] mcfg4_datain;
output [10:0] mcfg4_dataout;
/*******************************/
/* Copy port0 input to master */
/*******************************/
assign slvcfg_datain = mcfg0_datain;
/*******************************/
/* Split inputs to all outputs */
/*******************************/
assign mcfg0_sw_reset = slvcfg_sw_reset;
assign mcfg0_tx_enable = slvcfg_tx_enable;
assign mcfg0_tx_mmu_mode = slvcfg_tx_mmu_mode;
assign mcfg0_tx_gpio_mode = slvcfg_tx_gpio_mode;
assign mcfg0_tx_ctrl_mode = slvcfg_tx_ctrl_mode;
assign mcfg0_tx_clkdiv = slvcfg_tx_clkdiv;
assign mcfg0_rx_enable = slvcfg_rx_enable;
assign mcfg0_rx_mmu_mode = slvcfg_rx_mmu_mode;
assign mcfg0_rx_gpio_mode = slvcfg_rx_gpio_mode;
assign mcfg0_rx_loopback_mode = slvcfg_rx_loopback_mode;
assign mcfg0_coreid = slvcfg_coreid;
assign mcfg1_sw_reset = slvcfg_sw_reset;
assign mcfg1_tx_enable = slvcfg_tx_enable;
assign mcfg1_tx_mmu_mode = slvcfg_tx_mmu_mode;
assign mcfg1_tx_gpio_mode = slvcfg_tx_gpio_mode;
assign mcfg1_tx_ctrl_mode = slvcfg_tx_ctrl_mode;
assign mcfg1_tx_clkdiv = slvcfg_tx_clkdiv;
assign mcfg1_rx_enable = slvcfg_rx_enable;
assign mcfg1_rx_mmu_mode = slvcfg_rx_mmu_mode;
assign mcfg1_rx_gpio_mode = slvcfg_rx_gpio_mode;
assign mcfg1_rx_loopback_mode = slvcfg_rx_loopback_mode;
assign mcfg1_coreid = slvcfg_coreid;
assign mcfg2_sw_reset = slvcfg_sw_reset;
assign mcfg2_tx_enable = slvcfg_tx_enable;
assign mcfg2_tx_mmu_mode = slvcfg_tx_mmu_mode;
assign mcfg2_tx_gpio_mode = slvcfg_tx_gpio_mode;
assign mcfg2_tx_ctrl_mode = slvcfg_tx_ctrl_mode;
assign mcfg2_tx_clkdiv = slvcfg_tx_clkdiv;
assign mcfg2_rx_enable = slvcfg_rx_enable;
assign mcfg2_rx_mmu_mode = slvcfg_rx_mmu_mode;
assign mcfg2_rx_gpio_mode = slvcfg_rx_gpio_mode;
assign mcfg2_rx_loopback_mode = slvcfg_rx_loopback_mode;
assign mcfg2_coreid = slvcfg_coreid;
assign mcfg3_sw_reset = slvcfg_sw_reset;
assign mcfg3_tx_enable = slvcfg_tx_enable;
assign mcfg3_tx_mmu_mode = slvcfg_tx_mmu_mode;
assign mcfg3_tx_gpio_mode = slvcfg_tx_gpio_mode;
assign mcfg3_tx_ctrl_mode = slvcfg_tx_ctrl_mode;
assign mcfg3_tx_clkdiv = slvcfg_tx_clkdiv;
assign mcfg3_rx_enable = slvcfg_rx_enable;
assign mcfg3_rx_mmu_mode = slvcfg_rx_mmu_mode;
assign mcfg3_rx_gpio_mode = slvcfg_rx_gpio_mode;
assign mcfg3_rx_loopback_mode = slvcfg_rx_loopback_mode;
assign mcfg3_coreid = slvcfg_coreid;
assign mcfg4_sw_reset = slvcfg_sw_reset;
assign mcfg4_tx_enable = slvcfg_tx_enable;
assign mcfg4_tx_mmu_mode = slvcfg_tx_mmu_mode;
assign mcfg4_tx_gpio_mode = slvcfg_tx_gpio_mode;
assign mcfg4_tx_ctrl_mode = slvcfg_tx_ctrl_mode;
assign mcfg4_tx_clkdiv = slvcfg_tx_clkdiv;
assign mcfg4_rx_enable = slvcfg_rx_enable;
assign mcfg4_rx_mmu_mode = slvcfg_rx_mmu_mode;
assign mcfg4_rx_gpio_mode = slvcfg_rx_gpio_mode;
assign mcfg4_rx_loopback_mode = slvcfg_rx_loopback_mode;
assign mcfg4_coreid = slvcfg_coreid;
endmodule // ecfg_split

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ecfg_split/ip_prj/ip_prj.xpr Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2014.3 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="2" Path="/mnt/windowsC/Adapteva/Parallella/parallella-hwelink/fpga/src/ecfg_split/ip_prj/ip_prj.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="994f2548f8544114a47a5480543ae8d2"/>
<Option Name="Part" Val="xc7z020clg400-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="BoardPart" Val=""/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="IPRepoPath" Val="$PPRDIR/../../../src"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../hdl/ecfg_split.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../component.xml">
<FileInfo SFType="IPXACT"/>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="ecfg_split"/>
<Option Name="TopRTLFile" Val="$PPRDIR/../hdl/ecfg_split.v"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="ecfg_split"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="QuestaSim/ModelSim Simulator"/>
</Simulator>
<Simulator Name="IES">
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
</Simulator>
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="9">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2014">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" State="current" SynthRun="synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014">
<Desc>Vivado Implementation Defaults</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
</Run>
</Runs>
</Project>

12
ecfg_split/xgui/ecfg_split_v1_0.tcl Normal file
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# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
set Component_Name [ ipgui::add_param $IPINST -name "Component_Name" -display_name {Component Name}]
set_property tooltip {Component Name} ${Component_Name}
#Adding Page
set Page_0 [ ipgui::add_page $IPINST -name "Page 0" -display_name {Page 0}]
set_property tooltip {Page 0} ${Page_0}
}

394
eclock/component.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>adapteva.com</spirit:vendor>
<spirit:library>Adapteva</spirit:library>
<spirit:name>eclock</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>signal_reset</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>reset</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>POLARITY</spirit:name>
<spirit:value spirit:format="string" spirit:resolve="immediate" spirit:id="BUSIFPARAM_VALUE.SIGNAL_RESET.POLARITY" spirit:choiceRef="choices_0">ACTIVE_HIGH</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>ecfg_cclk</spirit:name>
<spirit:busType spirit:vendor="adapteva.com" spirit:library="Adapteva" spirit:name="eClockCfg" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="adapteva.com" spirit:library="Adapteva" spirit:name="eClockCfg_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>div</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ecfg_cclk_div</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>pllcfg</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ecfg_cclk_pllcfg</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>en</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ecfg_cclk_en</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>xilinx_verilogsynthesis</spirit:name>
<spirit:displayName>Verilog Synthesis</spirit:displayName>
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
<spirit:language>verilog</spirit:language>
<spirit:modelName>eclock</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_verilogsynthesis_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>4c07ce39</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_verilogbehavioralsimulation</spirit:name>
<spirit:displayName>Verilog Simulation</spirit:displayName>
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
<spirit:language>verilog</spirit:language>
<spirit:modelName>eclock</spirit:modelName>
<spirit:fileSetRef>
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</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_xpgui</spirit:name>
<spirit:displayName>UI Layout</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
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</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>CCLK_P</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:port>
<spirit:name>CCLK_N</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
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<spirit:port>
<spirit:name>lclk_s</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
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<spirit:port>
<spirit:name>lclk_out</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
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<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>lclk_p</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>clkin</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>reset</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>ecfg_cclk_en</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>ecfg_cclk_div</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="immediate">3</spirit:left>
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>ecfg_cclk_pllcfg</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="immediate">3</spirit:left>
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
</spirit:ports>
<spirit:modelParameters>
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
<spirit:name>CLKIN_PERIOD</spirit:name>
<spirit:displayName>Clkin Period</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CLKIN_PERIOD">10</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>CLKIN_DIVIDE</spirit:name>
<spirit:displayName>Clkin Divide</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CLKIN_DIVIDE">1</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>VCO_MULT</spirit:name>
<spirit:displayName>Vco Mult</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VCO_MULT">12</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>CCLK_DIVIDE</spirit:name>
<spirit:displayName>Cclk Divide</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CCLK_DIVIDE">2</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>LCLK_DIVIDE</spirit:name>
<spirit:displayName>Lclk Divide</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.LCLK_DIVIDE">4</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>FEATURE_CCLK_DIV</spirit:name>
<spirit:displayName>Feature Cclk Div</spirit:displayName>
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.FEATURE_CCLK_DIV" spirit:bitStringLength="1">&quot;1&quot;</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="string">
<spirit:name>IOSTD_ELINK</spirit:name>
<spirit:displayName>Iostd Elink</spirit:displayName>
<spirit:value spirit:format="string" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IOSTD_ELINK">LVDS_25</spirit:value>
</spirit:modelParameter>
</spirit:modelParameters>
</spirit:model>
<spirit:choices>
<spirit:choice>
<spirit:name>choices_0</spirit:name>
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
</spirit:choice>
</spirit:choices>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>xilinx_verilogsynthesis_view_fileset</spirit:name>
<spirit:file>
<spirit:name>hdl/eclock.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_4c07ce39</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_verilogbehavioralsimulation_view_fileset</spirit:name>
<spirit:file>
<spirit:name>hdl/eclock.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
<spirit:file>
<spirit:name>xgui/eclock_v1_0.tcl</spirit:name>
<spirit:fileType>tclSource</spirit:fileType>
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
<spirit:userFileType>CHECKSUM_f5b360c1</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>eClock Clock Generation Module</spirit:description>
<spirit:parameters>
<spirit:parameter>
<spirit:name>IOSTD_ELINK</spirit:name>
<spirit:displayName>Iostd Elink</spirit:displayName>
<spirit:value spirit:format="string" spirit:resolve="user" spirit:id="PARAM_VALUE.IOSTD_ELINK" spirit:order="1100">LVDS_25</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>FEATURE_CCLK_DIV</spirit:name>
<spirit:displayName>Feature Cclk Div</spirit:displayName>
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.FEATURE_CCLK_DIV" spirit:order="1200" spirit:bitStringLength="1">&quot;1&quot;</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>LCLK_DIVIDE</spirit:name>
<spirit:displayName>Lclk Divide</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.LCLK_DIVIDE" spirit:order="1300">4</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>CCLK_DIVIDE</spirit:name>
<spirit:displayName>Cclk Divide</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CCLK_DIVIDE" spirit:order="1400">2</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>VCO_MULT</spirit:name>
<spirit:displayName>Vco Mult</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.VCO_MULT" spirit:order="1500">12</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLKIN_DIVIDE</spirit:name>
<spirit:displayName>Clkin Divide</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKIN_DIVIDE" spirit:order="1600">1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLKIN_PERIOD</spirit:name>
<spirit:displayName>Clkin Period</spirit:displayName>
<spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKIN_PERIOD" spirit:order="1700" spirit:configGroups="0 UnGrouped textEdit">10</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>Component_Name</spirit:name>
<spirit:displayName>Component Name</spirit:displayName>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">eclock_v1_0</spirit:value>
</spirit:parameter>
</spirit:parameters>
<spirit:vendorExtensions>
<xilinx:coreExtensions>
<xilinx:supportedFamilies>
<xilinx:family xilinx:lifeCycle="Pre-Production">zynq</xilinx:family>
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<xilinx:taxonomies>
<xilinx:taxonomy>/BaseIP</xilinx:taxonomy>
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<xilinx:displayName>eclock_v1_0</xilinx:displayName>
<xilinx:vendorDisplayName>Adapteva</xilinx:vendorDisplayName>
<xilinx:vendorURL>http://www.adapteva.com</xilinx:vendorURL>
<xilinx:coreRevision>4</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2014-11-09T21:07:57Z</xilinx:coreCreationDateTime>
<xilinx:tags>
<xilinx:tag xilinx:name="user.org:user:eclock:1.0_ARCHIVE_LOCATION">/mnt/windowsC/Adapteva/Parallella/parallella-hwelink/fpga/hdl/eclock/ip</xilinx:tag>
<xilinx:tag xilinx:name="adapteva.com:user:eclock:1.0_ARCHIVE_LOCATION">/mnt/windowsC/Adapteva/Parallella/parallella-hwelink/fpga/hdl/eclock/ip</xilinx:tag>
<xilinx:tag xilinx:name="adapteva.com:Adapteva:eclock:1.0_ARCHIVE_LOCATION">/mnt/windowsC/Adapteva/Parallella/parallella-hwelink/fpga/hdl/eclock/ip</xilinx:tag>
</xilinx:tags>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2014.3</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="e77f0e30"/>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="d6cf9a4d"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="abdeedc3"/>
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="b5e7f9c5"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="265acca5"/>
</xilinx:packagingInfo>
</spirit:vendorExtensions>
</spirit:component>

247
eclock/hdl/eclock.v Normal file
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@ -0,0 +1,247 @@
/*
Copyright (C) 2014 Adapteva, Inc.
Contributed by Fred Huettig <fred@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
/*###########################################################################
# Function: Generates clocks for eLink module:
# CCLK_N/P - Epiphany Core Clock, Differential, must be connected
# directly to IO pins.
#
# lclk_p - Parallel data clock, at bit rate / 8
#
# lclk_s - Serial DDR data clock, at bit rate / 2
#
# lclk_out - DDR "Clock" clock, to generate LCLK output
# At bit rate / 2, 90deg shifted from lclk_s
#
# Inputs:
# ecfg_cclk_en - Enable the CCLK output
# ecfg_cclk_div - CCLK divider
# ecfg_cclk_pllcfg - PLL configuration (not implemented)
#
# Notes: Uses Xilinx macros throughout
#
############################################################################
*/
`timescale 1ns/1ps
module eclock (/*AUTOARG*/
// Outputs
CCLK_P, CCLK_N, lclk_s, lclk_out, lclk_p,
// Inputs
clkin, reset, ecfg_cclk_en, ecfg_cclk_div, ecfg_cclk_pllcfg
);
// Parameters must be set as follows:
// PFD input frequency = 1/CLKIN1_PERIOD / DIVCLK_DIVIDE (10-450MHz)
// VCO frequency = PFD input frequency * CLKFBOUT_MULT (800-1600MHz)
// Output frequency = VCO frequency / CLKOUTn_DIVIDE
parameter CLKIN_PERIOD = 10.000; // ns -> 100MHz
parameter CLKIN_DIVIDE = 1;
parameter VCO_MULT = 12; // VCO = 1200MHz
parameter CCLK_DIVIDE = 2; // CCLK = 600MHz (at /1 setting)
parameter LCLK_DIVIDE = 4; // LCLK = 300MHz (600MB/s eLink, 75MW/s parallel)
parameter FEATURE_CCLK_DIV = 1'b1;
parameter IOSTD_ELINK = "LVDS_25";
// input clock & reset
input clkin;
input reset;
// From configuration register
input ecfg_cclk_en; //cclk enable
input [3:0] ecfg_cclk_div; //cclk divider setting
input [3:0] ecfg_cclk_pllcfg; //pll configuration TODO: ??
output CCLK_P, CCLK_N;
output lclk_s;
output lclk_out;
output lclk_p;
// Wires
wire cclk_src;
wire cclk_base;
wire cclk_p;
wire cclk;
wire lclk_s_src;
wire lclk_out_src;
wire lclk_p_src;
wire clkfb;
// PLL Primitive
PLLE2_BASE
#(
.BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW
.CLKFBOUT_MULT(VCO_MULT), // Multiply value for all CLKOUT, (2-64)
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB, (-360.000-360.000).
.CLKIN1_PERIOD(CLKIN_PERIOD),// Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
// CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
.CLKOUT0_DIVIDE(CCLK_DIVIDE),
.CLKOUT1_DIVIDE(LCLK_DIVIDE),
.CLKOUT2_DIVIDE(LCLK_DIVIDE),
.CLKOUT3_DIVIDE(LCLK_DIVIDE * 4),
.CLKOUT4_DIVIDE(CCLK_DIVIDE * 4),
.CLKOUT5_DIVIDE(128),
// CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999).
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT5_DUTY_CYCLE(0.5),
// CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
.CLKOUT0_PHASE(0.0),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_PHASE(90.0),
.CLKOUT3_PHASE(0.0),
.CLKOUT4_PHASE(0.0),
.CLKOUT5_PHASE(0.0),
.DIVCLK_DIVIDE(CLKIN_DIVIDE),// Master division value, (1-56)
.REF_JITTER1(0.01), // Reference input jitter in UI, (0.000-0.999).
.STARTUP_WAIT("FALSE") // Delay DONE until PLL Locks, ("TRUE"/"FALSE")
) eclk_pll
(
// Clock Outputs: 1-bit (each) output: User configurable clock outputs
.CLKOUT0(cclk_src), // 1-bit output: CLKOUT0
.CLKOUT1(lclk_s_src), // 1-bit output: CLKOUT1
.CLKOUT2(lclk_out_src), // 1-bit output: CLKOUT2
.CLKOUT3(lclk_p_src), // 1-bit output: CLKOUT3
.CLKOUT4(cclk_p), // 1-bit output: CLKOUT4
.CLKOUT5(), // 1-bit output: CLKOUT5
// Feedback Clocks: 1-bit (each) output: Clock feedback ports
.CLKFBOUT(clkfb), // 1-bit output: Feedback clock
.LOCKED(), // 1-bit output: LOCK
.CLKIN1(clkin), // 1-bit input: Input clock
// Control Ports: 1-bit (each) inpu: PLL control ports
.PWRDWN(1'b0), // 1-bit input: Power-down
.RST(1'b0), // 1-bit input: Reset
// Feedback Clocks: 1-bit (each) input: Clock feedback ports
.CLKFBIN(clkfb) // 1-bit input: Feedback clock
);
// Output buffering
BUFG cclk_buf
(.O (cclk_base),
.I (cclk_src));
BUFG lclk_s_buf
(.O (lclk_s),
.I (lclk_s_src));
BUFG lclk_out_buf
(.O (lclk_out),
.I (lclk_out_src));
BUFG lclk_p_buf
(.O (lclk_p),
.I (lclk_p_src));
generate
if( FEATURE_CCLK_DIV ) begin : gen_cclk_div
// Create adjustable (but fast) CCLK
wire rxi_cclk_out;
reg [8:1] cclk_pattern;
reg [3:0] clk_div_sync;
reg enb_sync;
always @ (posedge cclk_p) begin // Might need x-clock TIG here
clk_div_sync <= ecfg_cclk_div;
enb_sync <= ecfg_cclk_en;
if(enb_sync)
case(clk_div_sync)
4'h0: cclk_pattern <= 8'd0; // Clock OFF
4'h7: cclk_pattern <= 8'b10101010; // Divide by 1
4'h6: cclk_pattern <= 8'b11001100; // Divide by 2
4'h5: cclk_pattern <= 8'b11110000; // Divide by 4
default: cclk_pattern <= {8{~cclk_pattern[1]}}; // /8
endcase
else
cclk_pattern <= 8'b00000000;
end // always @ (posedge lclk_p)
OSERDESE2
#(
.DATA_RATE_OQ("DDR"), // DDR, SDR
.DATA_RATE_TQ("SDR"), // DDR, BUF, SDR
.DATA_WIDTH(8), // Parallel data width (2-8,10,14)
.INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)
.INIT_TQ(1'b0), // Initial value of TQ output (1'b0,1'b1)
.SERDES_MODE("MASTER"), // MASTER, SLAVE
.SRVAL_OQ(1'b0), // OQ output value when SR is used (1'b0,1'b1)
.SRVAL_TQ(1'b0), // TQ output value when SR is used (1'b0,1'b1)
.TBYTE_CTL("FALSE"), // Enable tristate byte operation (FALSE, TRUE)
.TBYTE_SRC("FALSE"), // Tristate byte source (FALSE, TRUE)
.TRISTATE_WIDTH(1) // 3-state converter width (1,4)
) OSERDESE2_inst
(
.OFB(), // 1-bit output: Feedback path for data
.OQ(cclk), // 1-bit output: Data path output
.SHIFTOUT1(), // SHIFTOUTn: 1-bit (each): Data output expansion
.SHIFTOUT2(),
.TBYTEOUT(), // 1-bit output: Byte group tristate
.TFB(), // 1-bit output: 3-state control
.TQ(), // 1-bit output: 3-state control
.CLK(cclk_base), // 1-bit input: High speed clock
.CLKDIV(cclk_p), // 1-bit input: Divided clock
.D1(cclk_pattern[1]), // D1 - D8: Parallel data inputs (1-bit each)
.D2(cclk_pattern[2]),
.D3(cclk_pattern[3]),
.D4(cclk_pattern[4]),
.D5(cclk_pattern[5]),
.D6(cclk_pattern[6]),
.D7(cclk_pattern[7]),
.D8(cclk_pattern[8]),
.OCE(1'b1), // 1-bit input: Output data clock enable
.RST(reset), // 1-bit input: Reset
.SHIFTIN1(1'b0), // SHIFTINn: Data input expansion (1-bit each)
.SHIFTIN2(1'b0),
.T1(1'b0), // T1 - T4: Parallel 3-state inputs
.T2(1'b0),
.T3(1'b0),
.T4(1'b0),
.TBYTEIN(1'b0), // 1-bit input: Byte group tristate
.TCE(1'b0) // 1-bit input: 3-state clock enable
);
end else begin : gen_fixed_cclk // Non-dividable CCLK
reg enb_sync;
always @ (posedge cclk_p)
enb_sync <= ecfg_cclk_en;
// The following does not result in timing failures,
// but doesn't seem glitch-safe
assign cclk = cclk_base & enb_sync;
end
endgenerate
// xilinx OBUFDS instantiation
//
OBUFDS
#(.IOSTANDARD (IOSTD_ELINK))
obufds_cclk_inst
(.O (CCLK_P),
.OB (CCLK_N),
.I (cclk));
endmodule // eclock

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eclock/ip_prj/ip_prj.xpr Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2014.3 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="2" Path="/mnt/windowsC/Adapteva/Parallella/parallella-hwelink/fpga/src/eclock/ip_prj/ip_prj.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="90800911d7ba45b3b0da36946a992eac"/>
<Option Name="Part" Val="xc7z020clg400-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="BoardPart" Val=""/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="IPRepoPath" Val="$PPRDIR/../../../src"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../hdl/eclock.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../component.xml">
<FileInfo SFType="IPXACT"/>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="eclock"/>
<Option Name="TopRTLFile" Val="$PPRDIR/../hdl/eclock.v"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Filter Type="Srcs"/>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="eclock"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="QuestaSim/ModelSim Simulator"/>
</Simulator>
<Simulator Name="IES">
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
</Simulator>
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="9">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2014"/>
<Step Id="synth_design"/>
</Strategy>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" State="current" SynthRun="synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
</Run>
</Runs>
</Project>

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eclock/xgui/eclock_v1_0.tcl Normal file
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# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
set Component_Name [ ipgui::add_param $IPINST -name "Component_Name" -display_name {Component Name}]
set_property tooltip {Component Name} ${Component_Name}
#Adding Page
set Page_0 [ ipgui::add_page $IPINST -name "Page 0" -display_name {Page 0}]
set_property tooltip {Page 0} ${Page_0}
set IOSTD_ELINK [ ipgui::add_param $IPINST -name "IOSTD_ELINK" -parent ${Page_0} -display_name {Iostd Elink}]
set_property tooltip {Iostd Elink} ${IOSTD_ELINK}
set FEATURE_CCLK_DIV [ ipgui::add_param $IPINST -name "FEATURE_CCLK_DIV" -parent ${Page_0} -display_name {Feature Cclk Div}]
set_property tooltip {Feature Cclk Div} ${FEATURE_CCLK_DIV}
set LCLK_DIVIDE [ ipgui::add_param $IPINST -name "LCLK_DIVIDE" -parent ${Page_0} -display_name {Lclk Divide}]
set_property tooltip {Lclk Divide} ${LCLK_DIVIDE}
set CCLK_DIVIDE [ ipgui::add_param $IPINST -name "CCLK_DIVIDE" -parent ${Page_0} -display_name {Cclk Divide}]
set_property tooltip {Cclk Divide} ${CCLK_DIVIDE}
set VCO_MULT [ ipgui::add_param $IPINST -name "VCO_MULT" -parent ${Page_0} -display_name {Vco Mult}]
set_property tooltip {Vco Mult} ${VCO_MULT}
set CLKIN_DIVIDE [ ipgui::add_param $IPINST -name "CLKIN_DIVIDE" -parent ${Page_0} -display_name {Clkin Divide}]
set_property tooltip {Clkin Divide} ${CLKIN_DIVIDE}
set CLKIN_PERIOD [ ipgui::add_param $IPINST -name "CLKIN_PERIOD" -parent ${Page_0} -display_name {Clkin Period}]
set_property tooltip {Clkin Period} ${CLKIN_PERIOD}
}
proc update_PARAM_VALUE.IOSTD_ELINK { PARAM_VALUE.IOSTD_ELINK } {
# Procedure called to update IOSTD_ELINK when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.IOSTD_ELINK { PARAM_VALUE.IOSTD_ELINK } {
# Procedure called to validate IOSTD_ELINK
return true
}
proc update_PARAM_VALUE.FEATURE_CCLK_DIV { PARAM_VALUE.FEATURE_CCLK_DIV } {
# Procedure called to update FEATURE_CCLK_DIV when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.FEATURE_CCLK_DIV { PARAM_VALUE.FEATURE_CCLK_DIV } {
# Procedure called to validate FEATURE_CCLK_DIV
return true
}
proc update_PARAM_VALUE.LCLK_DIVIDE { PARAM_VALUE.LCLK_DIVIDE } {
# Procedure called to update LCLK_DIVIDE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.LCLK_DIVIDE { PARAM_VALUE.LCLK_DIVIDE } {
# Procedure called to validate LCLK_DIVIDE
return true
}
proc update_PARAM_VALUE.CCLK_DIVIDE { PARAM_VALUE.CCLK_DIVIDE } {
# Procedure called to update CCLK_DIVIDE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.CCLK_DIVIDE { PARAM_VALUE.CCLK_DIVIDE } {
# Procedure called to validate CCLK_DIVIDE
return true
}
proc update_PARAM_VALUE.VCO_MULT { PARAM_VALUE.VCO_MULT } {
# Procedure called to update VCO_MULT when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.VCO_MULT { PARAM_VALUE.VCO_MULT } {
# Procedure called to validate VCO_MULT
return true
}
proc update_PARAM_VALUE.CLKIN_DIVIDE { PARAM_VALUE.CLKIN_DIVIDE } {
# Procedure called to update CLKIN_DIVIDE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.CLKIN_DIVIDE { PARAM_VALUE.CLKIN_DIVIDE } {
# Procedure called to validate CLKIN_DIVIDE
return true
}
proc update_PARAM_VALUE.CLKIN_PERIOD { PARAM_VALUE.CLKIN_PERIOD } {
# Procedure called to update CLKIN_PERIOD when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.CLKIN_PERIOD { PARAM_VALUE.CLKIN_PERIOD } {
# Procedure called to validate CLKIN_PERIOD
return true
}
proc update_MODELPARAM_VALUE.CLKIN_PERIOD { MODELPARAM_VALUE.CLKIN_PERIOD PARAM_VALUE.CLKIN_PERIOD } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.CLKIN_PERIOD}] ${MODELPARAM_VALUE.CLKIN_PERIOD}
}
proc update_MODELPARAM_VALUE.CLKIN_DIVIDE { MODELPARAM_VALUE.CLKIN_DIVIDE PARAM_VALUE.CLKIN_DIVIDE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.CLKIN_DIVIDE}] ${MODELPARAM_VALUE.CLKIN_DIVIDE}
}
proc update_MODELPARAM_VALUE.VCO_MULT { MODELPARAM_VALUE.VCO_MULT PARAM_VALUE.VCO_MULT } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.VCO_MULT}] ${MODELPARAM_VALUE.VCO_MULT}
}
proc update_MODELPARAM_VALUE.CCLK_DIVIDE { MODELPARAM_VALUE.CCLK_DIVIDE PARAM_VALUE.CCLK_DIVIDE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.CCLK_DIVIDE}] ${MODELPARAM_VALUE.CCLK_DIVIDE}
}
proc update_MODELPARAM_VALUE.LCLK_DIVIDE { MODELPARAM_VALUE.LCLK_DIVIDE PARAM_VALUE.LCLK_DIVIDE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.LCLK_DIVIDE}] ${MODELPARAM_VALUE.LCLK_DIVIDE}
}
proc update_MODELPARAM_VALUE.FEATURE_CCLK_DIV { MODELPARAM_VALUE.FEATURE_CCLK_DIV PARAM_VALUE.FEATURE_CCLK_DIV } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.FEATURE_CCLK_DIV}] ${MODELPARAM_VALUE.FEATURE_CCLK_DIV}
}
proc update_MODELPARAM_VALUE.IOSTD_ELINK { MODELPARAM_VALUE.IOSTD_ELINK PARAM_VALUE.IOSTD_ELINK } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.IOSTD_ELINK}] ${MODELPARAM_VALUE.IOSTD_ELINK}
}

886
edistrib/component.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>adapteva.com</spirit:vendor>
<spirit:library>Adapteva</spirit:library>
<spirit:name>edistrib</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>ecfg</spirit:name>
<spirit:busType spirit:vendor="adapteva.com" spirit:library="Adapteva" spirit:name="eConfig" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="adapteva.com" spirit:library="Adapteva" spirit:name="eConfig_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>rx_enable</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ecfg_rx_enable</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>rx_mmu_mode</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ecfg_rx_mmu_mode</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>ems_dir</spirit:name>
<spirit:busType spirit:vendor="adapteva.com" spirit:library="Adapteva" spirit:name="eMesh" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="adapteva.com" spirit:library="Adapteva" spirit:name="eMesh_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>access</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ems_dir_access</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>write</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ems_dir_write</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>datamode</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ems_dir_datamode</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ctrlmode</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ems_dir_ctrlmode</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>dstaddr</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ems_dir_dstaddr</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>srcaddr</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ems_dir_srcaddr</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ems_dir_data</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>wr_wait</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ems_dir_wr_wait</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>rd_wait</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ems_dir_rd_wait</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>ems_mmu</spirit:name>
<spirit:busType spirit:vendor="adapteva.com" spirit:library="Adapteva" spirit:name="eMesh" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="adapteva.com" spirit:library="Adapteva" spirit:name="eMesh_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>access</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ems_mmu_access</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>write</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ems_mmu_write</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>datamode</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ems_mmu_datamode</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ctrlmode</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ems_mmu_ctrlmode</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>dstaddr</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ems_mmu_dstaddr</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>srcaddr</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ems_mmu_srcaddr</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ems_mmu_data</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
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<spirit:name>emrq</spirit:name>
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<spirit:parameter>
<spirit:name>C_READ_TAG_ADDR</spirit:name>
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edistrib/hdl/edistrib.v Normal file
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/*
File: edistrib.v
This file is part of the Parallella Project.
Copyright (C) 2014 Adapteva, Inc.
Contributed by Fred Huettig <fred@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
/*
########################################################################
EPIPHANY eMesh Filter / Distributor
########################################################################
This block takes one eMesh input, selected from two available
(MMU or direct), and distributes the transactions based on type
(write, read request, read response).
*/
module edistrib (/*AUTOARG*/
// Outputs
ems_dir_rd_wait, ems_dir_wr_wait, emwr_wr_data, emwr_wr_en,
emrq_wr_data, emrq_wr_en, emrr_wr_data, emrr_wr_en,
// Inputs
rxlclk, ems_dir_access, ems_dir_write, ems_dir_datamode,
ems_dir_ctrlmode, ems_dir_dstaddr, ems_dir_srcaddr, ems_dir_data,
ems_mmu_access, ems_mmu_write, ems_mmu_datamode, ems_mmu_ctrlmode,
ems_mmu_dstaddr, ems_mmu_srcaddr, ems_mmu_data, emwr_full,
emwr_prog_full, emrq_full, emrq_prog_full, emrr_full,
emrr_prog_full, ecfg_rx_enable, ecfg_rx_mmu_mode
);
parameter [11:0] C_READ_TAG_ADDR = 12'h810;
// RX clock
input rxlclk;
// Direct slave port (with wait signals)
input ems_dir_access;
input ems_dir_write;
input [1:0] ems_dir_datamode;
input [3:0] ems_dir_ctrlmode;
input [31:0] ems_dir_dstaddr;
input [31:0] ems_dir_srcaddr;
input [31:0] ems_dir_data;
output ems_dir_rd_wait;
output ems_dir_wr_wait;
// MMU slave port (no wait signals)
input ems_mmu_access;
input ems_mmu_write;
input [1:0] ems_mmu_datamode;
input [3:0] ems_mmu_ctrlmode;
input [31:0] ems_mmu_dstaddr;
input [31:0] ems_mmu_srcaddr;
input [31:0] ems_mmu_data;
// Master FIFO port, writes
output [102:0] emwr_wr_data;
output emwr_wr_en;
input emwr_full; // full flags for error checking
input emwr_prog_full;
// Master FIFO port, read requests
output [102:0] emrq_wr_data;
output emrq_wr_en;
input emrq_full;
input emrq_prog_full;
// Master FIFO port, read responses
output [102:0] emrr_wr_data;
output emrr_wr_en;
input emrr_full;
input emrr_prog_full;
// Control bits inputs
input ecfg_rx_enable;
input ecfg_rx_mmu_mode;
//############
//# Distribute based on type & read-response tag
//############
reg [1:0] rxmmu_sync;
wire rxmmu = rxmmu_sync[0];
reg in_write;
reg [1:0] in_datamode;
reg [3:0] in_ctrlmode;
reg [31:0] in_dstaddr;
reg [31:0] in_srcaddr;
reg [31:0] in_data;
reg emwr_wr_en;
reg emrq_wr_en;
reg emrr_wr_en;
wire [102:0] fifo_din;
wire [102:0] emwr_wr_data;
wire [102:0] emrq_wr_data;
wire [102:0] emrr_wr_data;
always @ (posedge rxlclk) begin
rxmmu_sync <= {ecfg_rx_mmu_mode, rxmmu_sync[1]};
if(rxmmu) begin
in_write <= ems_mmu_write;
in_datamode <= ems_mmu_datamode;
in_ctrlmode <= ems_mmu_ctrlmode;
in_dstaddr <= ems_mmu_dstaddr;
in_srcaddr <= ems_mmu_srcaddr;
in_data <= ems_mmu_data;
if(ems_mmu_access) begin
emrq_wr_en <= ~ems_mmu_write;
emrr_wr_en <= ems_mmu_write & (ems_mmu_dstaddr[31:20] == C_READ_TAG_ADDR);
emwr_wr_en <= ems_mmu_write & (ems_mmu_dstaddr[31:20] != C_READ_TAG_ADDR);
end else begin
emrq_wr_en <= 1'b0;
emrr_wr_en <= 1'b0;
emwr_wr_en <= 1'b0;
end
end else begin
in_write <= ems_dir_write;
in_datamode <= ems_dir_datamode;
in_ctrlmode <= ems_dir_ctrlmode;
in_dstaddr <= ems_dir_dstaddr;
in_srcaddr <= ems_dir_srcaddr;
in_data <= ems_dir_data;
if(ems_dir_access) begin
emrq_wr_en <= ~ems_dir_write;
emrr_wr_en <= ems_dir_write & (ems_dir_dstaddr[31:20] == C_READ_TAG_ADDR);
emwr_wr_en <= ems_dir_write & (ems_dir_dstaddr[31:20] != C_READ_TAG_ADDR);
end else begin
emrq_wr_en <= 1'b0;
emrr_wr_en <= 1'b0;
emwr_wr_en <= 1'b0;
end
end // else: !if(rxmmu)
end // always @ (posedge rxlclk)
// Data is the same for all.
assign fifo_din =
{in_write,
in_datamode,
in_ctrlmode,
in_dstaddr,
in_srcaddr,
in_data};
assign emwr_wr_data = fifo_din;
assign emrq_wr_data = fifo_din;
assign emrr_wr_data = fifo_din;
//#############################
//# Wait signal passthroughs
//#############################
assign ems_dir_rd_wait = emrq_prog_full;
assign ems_dir_wr_wait = emwr_prog_full | emrr_prog_full;
endmodule // edistrib

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edistrib/ip_prj/ip_prj.xpr Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2014.3 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="2" Path="/mnt/windowsC/Adapteva/Parallella/parallella-hwelink/fpga/src/edistrib/ip_prj/ip_prj.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="ecd00d5f19034e309d97ddb757c25c63"/>
<Option Name="Part" Val="xc7z020clg400-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="BoardPart" Val=""/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="IPRepoPath" Val="$PPRDIR/../../../src"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../hdl/edistrib.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../component.xml">
<FileInfo SFType="IPXACT"/>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="edistrib"/>
<Option Name="TopRTLFile" Val="$PPRDIR/../hdl/edistrib.v"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Filter Type="Srcs"/>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="edistrib"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="QuestaSim/ModelSim Simulator"/>
</Simulator>
<Simulator Name="IES">
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
</Simulator>
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="9">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2014"/>
<Step Id="synth_design"/>
</Strategy>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" State="current" SynthRun="synth_1">
<Strategy Version="1" Minor="2">
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<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
</Run>
</Runs>
</Project>

28
edistrib/xgui/edistrib_v1_0.tcl Normal file
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# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
set Component_Name [ ipgui::add_param $IPINST -name "Component_Name" -display_name {Component Name}]
set_property tooltip {Component Name} ${Component_Name}
#Adding Page
set Page_0 [ ipgui::add_page $IPINST -name "Page 0" -display_name {Page 0}]
set_property tooltip {Page 0} ${Page_0}
set C_READ_TAG_ADDR [ ipgui::add_param $IPINST -name "C_READ_TAG_ADDR" -parent ${Page_0} -display_name {C_READ_TAG_ADDR}]
set_property tooltip {C_READ_TAG_ADDR} ${C_READ_TAG_ADDR}
}
proc update_PARAM_VALUE.C_READ_TAG_ADDR { PARAM_VALUE.C_READ_TAG_ADDR } {
# Procedure called to update C_READ_TAG_ADDR when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_READ_TAG_ADDR { PARAM_VALUE.C_READ_TAG_ADDR } {
# Procedure called to validate C_READ_TAG_ADDR
return true
}
proc update_MODELPARAM_VALUE.C_READ_TAG_ADDR { MODELPARAM_VALUE.C_READ_TAG_ADDR PARAM_VALUE.C_READ_TAG_ADDR } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_READ_TAG_ADDR}] ${MODELPARAM_VALUE.C_READ_TAG_ADDR}
}

706
eio_rx/component.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
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<spirit:vendor>adapteva.com</spirit:vendor>
<spirit:library>Adapteva</spirit:library>
<spirit:name>eio_rx</spirit:name>
<spirit:version>1.0</spirit:version>
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<spirit:busInterface>
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<spirit:name>RST</spirit:name>
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<spirit:physicalPort>
<spirit:name>reset</spirit:name>
</spirit:physicalPort>
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<spirit:parameters>
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<spirit:name>POLARITY</spirit:name>
<spirit:value spirit:format="string" spirit:resolve="immediate" spirit:id="BUSIFPARAM_VALUE.SIGNAL_RESET.POLARITY" spirit:choiceRef="choices_0">ACTIVE_HIGH</spirit:value>
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<spirit:name>RX</spirit:name>
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<spirit:name>data_n</spirit:name>
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<spirit:name>RX_DATA_N</spirit:name>
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<spirit:name>frame_p</spirit:name>
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<spirit:name>RX_FRAME_P</spirit:name>
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<spirit:name>frame_n</spirit:name>
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<spirit:name>RX_FRAME_N</spirit:name>
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</spirit:portMap>
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<spirit:logicalPort>
<spirit:name>lclk_p</spirit:name>
</spirit:logicalPort>
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<spirit:name>RX_LCLK_P</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
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<spirit:logicalPort>
<spirit:name>lclk_n</spirit:name>
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<spirit:name>RX_LCLK_N</spirit:name>
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365
eio_rx/hdl/eio_rx.v Normal file
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@ -0,0 +1,365 @@
/*
File: eio_rx.v
This file is part of the Parallella Project .
Copyright (C) 2014 Adapteva, Inc.
Contributed by Fred Huettig <fred@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module eio_rx (/*AUTOARG*/
// Outputs
RX_WR_WAIT_P, RX_WR_WAIT_N, RX_RD_WAIT_P, RX_RD_WAIT_N, rxlclk_p,
rxframe_p, rxdata_p, ecfg_datain,
// Inputs
RX_LCLK_P, RX_LCLK_N, reset, ioreset, RX_FRAME_P, RX_FRAME_N,
RX_DATA_P, RX_DATA_N, rx_wr_wait, rx_rd_wait, ecfg_rx_enable,
ecfg_rx_gpio_mode, ecfg_rx_loopback_mode, ecfg_dataout, tx_wr_wait,
tx_rd_wait, txlclk_p, loopback_data, loopback_frame
);
parameter IOSTD_ELINK = "LVDS_25";
//###########
//# eLink pins
//###########
input RX_LCLK_P, RX_LCLK_N; // Differential clock from IOB
input reset;
input ioreset;
input RX_FRAME_P, RX_FRAME_N; // Inputs from eLink
input [7:0] RX_DATA_P, RX_DATA_N;
output RX_WR_WAIT_P, RX_WR_WAIT_N;
output RX_RD_WAIT_P, RX_RD_WAIT_N;
//#############
//# Fabric interface, 1/8 bit rate of eLink
//#############
output rxlclk_p; // Parallel clock output
output [7:0] rxframe_p;
output [63:0] rxdata_p;
input rx_wr_wait;
input rx_rd_wait;
//#############
//# Configuration bits
//#############
input ecfg_rx_enable; //enable signal for rx
input ecfg_rx_gpio_mode; //forces rx wait pins to constants
input ecfg_rx_loopback_mode; //loops back tx to rx receiver (after serdes)
input [10:0] ecfg_dataout; // rd_wait, wr_wait for GPIO mode
output [10:0] ecfg_datain;
input tx_wr_wait, tx_rd_wait; // copies of wait signals for GPIO mode
// Data & frame from TX module for loopback
input txlclk_p; // TODO: Need to mux this in during loopback!
input [63:0] loopback_data;
input [7:0] loopback_frame;
//############
//# REGS
//############
reg [63:0] rxdata_p; // output registers
reg [7:0] rxframe_p;
//############
//# WIRES
//############
wire [7:0] rx_data; // High-speed serial data
wire rx_frame; // serial frame
wire serdes_reset;
//################################
//# Input Buffers Instantiation
//################################
IBUFDS
#(.DIFF_TERM ("TRUE"), // Differential termination
.IOSTANDARD (IOSTD_ELINK))
ibufds_rxdata[0:7]
(.I (RX_DATA_P),
.IB (RX_DATA_N),
.O (rx_data));
IBUFDS
#(.DIFF_TERM ("TRUE"), // Differential termination
.IOSTANDARD (IOSTD_ELINK))
ibufds_rxframe
(.I (RX_FRAME_P),
.IB (RX_FRAME_N),
.O (rx_frame));
//#####################
//# Clock Buffers
//#####################
wire rx_lclk; // Single-ended clock
wire rx_lclk_s; // Serial clock after BUFIO
IBUFGDS
#(.DIFF_TERM ("TRUE"), // Differential termination
.IOSTANDARD (IOSTD_ELINK))
ibufds_rxlclk
(.I (RX_LCLK_P),
.IB (RX_LCLK_N),
.O (rx_lclk));
BUFIO bufio_rxlclk
(.I (rx_lclk),
.O (rx_lclk_s));
// BUFR generates the slow clock
BUFR
#(.SIM_DEVICE("7SERIES"),
.BUFR_DIVIDE("4"))
clkout_bufr
(.O (rxlclk_p),
.CE(1'b1),
.CLR(1'b0),
.I (rx_lclk));
//#############################
//# Deserializer instantiations
//#############################
wire [63:0] rxdata_des;
wire [7:0] rxframe_des;
wire rx_lclk_sn = ~rx_lclk_s;
genvar i;
generate for(i=0; i<8; i=i+1)
begin : gen_serdes
ISERDESE2
#(
.DATA_RATE("DDR"), // DDR, SDR
.DATA_WIDTH(8), // Parallel data width (2-8,10,14)
.DYN_CLKDIV_INV_EN("FALSE"), // Enable DYNCLKDIVINVSEL inversion (FALSE, TRUE)
.DYN_CLK_INV_EN("FALSE"), // Enable DYNCLKINVSEL inversion (FALSE, TRUE)
// INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1)
.INIT_Q1(1'b0),
.INIT_Q2(1'b0),
.INIT_Q3(1'b0),
.INIT_Q4(1'b0),
.INTERFACE_TYPE("NETWORKING"),
// MEMORY, MEMORY_DDR3, MEMORY_QDR, NETWORKING, OVERSAMPLE
.IOBDELAY("NONE"), // NONE, BOTH, IBUF, IFD
.NUM_CE(2), // Number of clock enables (1,2)
.OFB_USED("FALSE"), // Select OFB path (FALSE, TRUE)
.SERDES_MODE("MASTER"), // MASTER, SLAVE
// SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1)
.SRVAL_Q1(1'b0),
.SRVAL_Q2(1'b0),
.SRVAL_Q3(1'b0),
.SRVAL_Q4(1'b0)
)
ISERDESE2_rxdata
(
.O(), // 1-bit output: Combinatorial output
// Q1 - Q8: 1-bit (each) output: Registered data outputs
.Q1(rxdata_des[i]), // Last data in?
.Q2(rxdata_des[i+8]),
.Q3(rxdata_des[i+16]),
.Q4(rxdata_des[i+24]),
.Q5(rxdata_des[i+32]),
.Q6(rxdata_des[i+40]),
.Q7(rxdata_des[i+48]),
.Q8(rxdata_des[i+56]), // First data in?
// SHIFTOUT1, SHIFTOUT2: 1-bit (each) output: Data width expansion output ports
.SHIFTOUT1(),
.SHIFTOUT2(),
.BITSLIP(1'b0), // 1-bit input: The BITSLIP pin performs a Bitslip operation
// synchronous to CLKDIV when asserted (active High). Subsequently, the data
// seen on the Q1 to Q8 output ports will shift, as in a barrel-shifter
// operation, one position every time Bitslip is invoked. DDR operation is
// different from SDR.
// CE1, CE2: 1-bit (each) input: Data register clock enable inputs
.CE1(1'b1),
.CE2(1'b1),
.CLKDIVP(1'b0), // 1-bit input: TBD
// Clocks: 1-bit (each) input: ISERDESE2 clock input ports
.CLK(rx_lclk_s), // 1-bit input: High-speed clock
.CLKB(rx_lclk_sn), // 1-bit input: High-speed secondary clock
.CLKDIV(rxlclk_p), // 1-bit input: Divided clock
.OCLK(1'b0), // 1-bit input: High speed output clock used when INTERFACE_TYPE="MEMORY"
// Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inversion pins to switch clock polarity
.DYNCLKDIVSEL(1'b0), // 1-bit input: Dynamic CLKDIV inversion
.DYNCLKSEL(1'b0), // 1-bit input: Dynamic CLK/CLKB inversion
// Input Data: 1-bit (each) input: ISERDESE2 data input ports
.D(rx_data[i]), // 1-bit input: Data input
.DDLY(1'b0), // 1-bit input: Serial data from IDELAYE2
.OFB(1'b0), // 1-bit input: Data feedback from OSERDESE2
.OCLKB(1'b0), // 1-bit input: High speed negative edge output clock
.RST(serdes_reset), // 1-bit input: Active high asynchronous reset
// SHIFTIN1, SHIFTIN2: 1-bit (each) input: Data width expansion input ports
.SHIFTIN1(1'b0),
.SHIFTIN2(1'b0)
);
end // block: gen_serdes
endgenerate
ISERDESE2
#(
.DATA_RATE("DDR"), // DDR, SDR
.DATA_WIDTH(8), // Parallel data width (2-8,10,14)
.DYN_CLKDIV_INV_EN("FALSE"), // Enable DYNCLKDIVINVSEL inversion (FALSE, TRUE)
.DYN_CLK_INV_EN("FALSE"), // Enable DYNCLKINVSEL inversion (FALSE, TRUE)
// INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1)
.INIT_Q1(1'b0),
.INIT_Q2(1'b0),
.INIT_Q3(1'b0),
.INIT_Q4(1'b0),
.INTERFACE_TYPE("NETWORKING"),
// MEMORY, MEMORY_DDR3, MEMORY_QDR, NETWORKING, OVERSAMPLE
.IOBDELAY("NONE"), // NONE, BOTH, IBUF, IFD
.NUM_CE(2), // Number of clock enables (1,2)
.OFB_USED("FALSE"), // Select OFB path (FALSE, TRUE)
.SERDES_MODE("MASTER"), // MASTER, SLAVE
// SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1)
.SRVAL_Q1(1'b0),
.SRVAL_Q2(1'b0),
.SRVAL_Q3(1'b0),
.SRVAL_Q4(1'b0)
)
ISERDESE2_rxframe
(
.O(), // 1-bit output: Combinatorial output
// Q1 - Q8: 1-bit (each) output: Registered data outputs
.Q1(rxframe_des[0]),
.Q2(rxframe_des[1]),
.Q3(rxframe_des[2]),
.Q4(rxframe_des[3]),
.Q5(rxframe_des[4]),
.Q6(rxframe_des[5]),
.Q7(rxframe_des[6]),
.Q8(rxframe_des[7]),
// SHIFTOUT1, SHIFTOUT2: 1-bit (each) output: Data width expansion output ports
.SHIFTOUT1(),
.SHIFTOUT2(),
.BITSLIP(1'b0), // 1-bit input: The BITSLIP pin performs a Bitslip operation
// synchronous to CLKDIV when asserted (active High). Subsequently, the data
// seen on the Q1 to Q8 output ports will shift, as in a barrel-shifter
// operation, one position every time Bitslip is invoked. DDR operation is
// different from SDR.
// CE1, CE2: 1-bit (each) input: Data register clock enable inputs
.CE1(1'b1),
.CE2(1'b1),
.CLKDIVP(1'b0), // 1-bit input: TBD
// Clocks: 1-bit (each) input: ISERDESE2 clock input ports
.CLK(rx_lclk_s), // 1-bit input: High-speed clock
.CLKB(rx_lclk_sn), // 1-bit input: High-speed secondary clock
.CLKDIV(rxlclk_p), // 1-bit input: Divided clock
.OCLK(1'b0), // 1-bit input: High speed output clock used when INTERFACE_TYPE="MEMORY"
// Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inversion pins to switch clock polarity
.DYNCLKDIVSEL(1'b0), // 1-bit input: Dynamic CLKDIV inversion
.DYNCLKSEL(1'b0), // 1-bit input: Dynamic CLK/CLKB inversion
// Input Data: 1-bit (each) input: ISERDESE2 data input ports
.D(rx_frame), // 1-bit input: Data input
.DDLY(1'b0), // 1-bit input: Serial data from IDELAYE2
.OFB(1'b0), // 1-bit input: Data feedback from OSERDESE2
.OCLKB(1'b0), // 1-bit input: High speed negative edge output clock
.RST(serdes_reset), // 1-bit input: Active high asynchronous reset
// SHIFTIN1, SHIFTIN2: 1-bit (each) input: Data width expansion input ports
.SHIFTIN1(1'b0),
.SHIFTIN2(1'b0)
);
// Sync control signals into our RX clock domain
reg [1:0] rxenb_sync;
wire rxenb = rxenb_sync[0];
assign serdes_reset = ~rxenb;
reg [1:0] rxloopback_sync;
wire rxloopback = rxloopback_sync[0];
reg [1:0] rxgpio_sync;
wire rxgpio = rxgpio_sync[0];
// Register outputs once for good measure, then mux in loopback data if enabled
reg [63:0] rxdata_reg;
reg [7:0] rxframe_reg;
wire rxreset = reset | ~ecfg_rx_enable;
always @ (posedge rxlclk_p or posedge rxreset) begin
if(rxreset)
rxenb_sync <= 'd0;
else
rxenb_sync <= {1'b1, rxenb_sync[1]};
end
always @ (posedge rxlclk_p) begin
rxloopback_sync <= {ecfg_rx_loopback_mode, rxloopback_sync[1]};
rxgpio_sync <= {ecfg_rx_gpio_mode, rxgpio_sync[1]};
rxdata_reg <= rxdata_des;
rxframe_reg <= rxframe_des & {8{rxenb}} & {8{~rxgpio}};
if(rxloopback) begin
rxdata_p <= loopback_data;
rxframe_p <= loopback_frame;
end else begin
rxdata_p <= rxdata_reg;
rxframe_p <= rxframe_reg;
end
end // always @ (posedge rxlclk_p)
//#############
//# GPIO mode inputs
//#############
reg [10:0] datain_reg;
reg [10:0] ecfg_datain;
always @ (posedge rxlclk_p) begin
datain_reg[10] <= tx_wr_wait;
datain_reg[9] <= tx_rd_wait;
datain_reg[8] <= rxframe_p[0];
datain_reg[7:0] <= rxdata_p[7:0];
ecfg_datain <= datain_reg;
end
//#############
//# Wait signals (asynchronous)
//#############
wire wr_wait = rxgpio ? ecfg_dataout[9] : rx_wr_wait;
wire rd_wait = rxgpio ? ecfg_dataout[10] : rx_rd_wait;
OBUFDS
#(
.IOSTANDARD(IOSTD_ELINK),
.SLEW("SLOW")
) OBUFDS_RXWRWAIT
(
.O(RX_WR_WAIT_P),
.OB(RX_WR_WAIT_N),
.I(wr_wait)
);
OBUFDS
#(
.IOSTANDARD(IOSTD_ELINK),
.SLEW("SLOW")
) OBUFDS_RXRDWAIT
(
.O(RX_RD_WAIT_P),
.OB(RX_RD_WAIT_N),
.I(rd_wait)
);
endmodule // eio_rx

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eio_rx/ip_prj/ip_prj.xpr Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2014.3 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="2" Path="/mnt/windowsC/Adapteva/Parallella/parallella-hwelink/fpga/src/eio_rx/ip_prj/ip_prj.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="2e28e1d9b6074e99bdf35d1229335da5"/>
<Option Name="Part" Val="xc7z020clg400-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="BoardPart" Val=""/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="IPRepoPath" Val="$PPRDIR/../../../src"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../hdl/eio_rx.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../component.xml">
<FileInfo SFType="IPXACT"/>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="eio_rx"/>
<Option Name="TopRTLFile" Val="$PPRDIR/../hdl/eio_rx.v"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="eio_rx"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="QuestaSim/ModelSim Simulator"/>
</Simulator>
<Simulator Name="IES">
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
</Simulator>
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="9">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2014">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" State="current" SynthRun="synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014">
<Desc>Vivado Implementation Defaults</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
</Run>
</Runs>
</Project>

28
eio_rx/xgui/eio_rx_v1_0.tcl Normal file
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# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
set Component_Name [ ipgui::add_param $IPINST -name "Component_Name" -display_name {Component Name}]
set_property tooltip {Component Name} ${Component_Name}
#Adding Page
set Page_0 [ ipgui::add_page $IPINST -name "Page 0" -display_name {Page 0}]
set_property tooltip {Page 0} ${Page_0}
set IOSTD_ELINK [ ipgui::add_param $IPINST -name "IOSTD_ELINK" -parent ${Page_0} -display_name {Iostd Elink}]
set_property tooltip {Iostd Elink} ${IOSTD_ELINK}
}
proc update_PARAM_VALUE.IOSTD_ELINK { PARAM_VALUE.IOSTD_ELINK } {
# Procedure called to update IOSTD_ELINK when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.IOSTD_ELINK { PARAM_VALUE.IOSTD_ELINK } {
# Procedure called to validate IOSTD_ELINK
return true
}
proc update_MODELPARAM_VALUE.IOSTD_ELINK { MODELPARAM_VALUE.IOSTD_ELINK PARAM_VALUE.IOSTD_ELINK } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.IOSTD_ELINK}] ${MODELPARAM_VALUE.IOSTD_ELINK}
}

632
eio_tx/component.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>adapteva.com</spirit:vendor>
<spirit:library>Adapteva</spirit:library>
<spirit:name>eio_tx</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>signal_reset</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>reset</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>POLARITY</spirit:name>
<spirit:value spirit:format="string" spirit:resolve="immediate" spirit:id="BUSIFPARAM_VALUE.SIGNAL_RESET.POLARITY" spirit:choiceRef="choices_0">ACTIVE_HIGH</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>TX</spirit:name>
<spirit:busType spirit:vendor="adapteva.com" spirit:library="interface" spirit:name="eLink" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="adapteva.com" spirit:library="interface" spirit:name="eLink_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>data_p</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>TX_DATA_P</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>data_n</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>TX_DATA_N</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>frame_p</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>TX_FRAME_P</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>frame_n</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>TX_FRAME_N</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>lclk_p</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>TX_LCLK_P</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>lclk_n</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>TX_LCLK_N</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>wr_wait_p</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>TX_WR_WAIT_P</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>wr_wait_n</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>TX_WR_WAIT_N</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>rd_wait_p</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>TX_RD_WAIT_P</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>rd_wait_n</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>TX_RD_WAIT_N</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>ecfg</spirit:name>
<spirit:busType spirit:vendor="adapteva.com" spirit:library="Adapteva" spirit:name="eConfig" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="adapteva.com" spirit:library="Adapteva" spirit:name="eConfig_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>tx_enable</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ecfg_tx_enable</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>tx_gpio_mode</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ecfg_tx_gpio_mode</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>tx_clkdiv</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ecfg_tx_clkdiv</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>dataout</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ecfg_dataout</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>xilinx_verilogsynthesis</spirit:name>
<spirit:displayName>Verilog Synthesis</spirit:displayName>
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
<spirit:language>verilog</spirit:language>
<spirit:modelName>eio_tx</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_verilogsynthesis_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>a723fa92</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_verilogbehavioralsimulation</spirit:name>
<spirit:displayName>Verilog Simulation</spirit:displayName>
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
<spirit:language>verilog</spirit:language>
<spirit:modelName>eio_tx</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_verilogbehavioralsimulation_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>a723fa92</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_xpgui</spirit:name>
<spirit:displayName>UI Layout</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>54415c9d</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>TX_LCLK_P</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>TX_LCLK_N</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>reset</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>ioreset</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>TX_FRAME_P</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>TX_FRAME_N</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>TX_DATA_P</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="immediate">7</spirit:left>
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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290
eio_tx/hdl/eio_tx.v Normal file
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@ -0,0 +1,290 @@
/*
File: eio_tx.v
This file is part of the Parallella Project .
Copyright (C) 2014 Adapteva, Inc.
Contributed by Fred Huettig <fred@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module eio_tx (/*AUTOARG*/
// Outputs
TX_LCLK_P, TX_LCLK_N, TX_FRAME_P, TX_FRAME_N, TX_DATA_P, TX_DATA_N,
tx_wr_wait, tx_rd_wait,
// Inputs
reset, ioreset, TX_WR_WAIT_P, TX_WR_WAIT_N, TX_RD_WAIT_P,
TX_RD_WAIT_N, txlclk_p, txlclk_s, txlclk_out, txframe_p, txdata_p,
ecfg_tx_enable, ecfg_tx_gpio_mode, ecfg_tx_clkdiv, ecfg_dataout
);
parameter IOSTD_ELINK = "LVDS_25";
//###########
//# eLink pins
//###########
output TX_LCLK_P, TX_LCLK_N; // Differential clock from PLL to eLink
input reset;
input ioreset;
output TX_FRAME_P, TX_FRAME_N; // Outputs to eLink
output [7:0] TX_DATA_P, TX_DATA_N;
input TX_WR_WAIT_P, TX_WR_WAIT_N;
input TX_RD_WAIT_P, TX_RD_WAIT_N;
//#############
//# Fabric interface, 1/8 bit rate of eLink
//#############
input txlclk_p; // Parallel clock in (bit rate / 8)
input txlclk_s; // Serial clock in (bit rate / 2)
input txlclk_out; // "LCLK" source in, 90deg from lclk_s
input [7:0] txframe_p;
input [63:0] txdata_p;
output tx_wr_wait;
output tx_rd_wait;
//#############
//# Configuration bits
//#############
input ecfg_tx_enable; //enable signal for rx
input ecfg_tx_gpio_mode; //forces rx wait pins to constants
input [3:0] ecfg_tx_clkdiv; // TODO: Implement this
input [10:0] ecfg_dataout; // frame & data for GPIO mode
//############
//# REGS
//############
//############
//# WIRES
//############
wire [7:0] tx_data; // High-speed serial data outputs
wire tx_frame; // serial frame signal
wire tx_lclk;
//#############################
//# Serializer instantiations
//#############################
reg [63:0] pdata;
reg [7:0] pframe;
reg [1:0] txenb_sync;
wire txenb = txenb_sync[0];
reg [1:0] txgpio_sync;
wire txgpio = txgpio_sync[0];
integer n;
// Sync these control bits into our domain
always @ (posedge txlclk_p) begin
txenb_sync <= {ecfg_tx_enable, txenb_sync[1]};
txgpio_sync <= {ecfg_tx_gpio_mode, txgpio_sync[1]};
if(txgpio) begin
pframe <= {8{ecfg_dataout[8]}};
for(n=0; n<8; n=n+1)
pdata[n*8+7 -: 8] <= ecfg_dataout[7:0];
end else if(txenb) begin
pframe <= txframe_p;
pdata <= txdata_p;
end else begin
pframe <= 8'd0;
pdata <= 64'd0;
end // else: !if(txgpio)
end // always @ (posedge txlclk_p)
genvar i;
generate for(i=0; i<8; i=i+1)
begin : gen_serdes
OSERDESE2
#(
.DATA_RATE_OQ("DDR"), // DDR, SDR
.DATA_RATE_TQ("DDR"), // DDR, BUF, SDR
.DATA_WIDTH(8), // Parallel data width (2-8,10,14)
.INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)
.INIT_TQ(1'b0), // Initial value of TQ output (1'b0,1'b1)
.SERDES_MODE("MASTER"), // MASTER, SLAVE
.SRVAL_OQ(1'b0), // OQ output value when SR is used (1'b0,1'b1)
.SRVAL_TQ(1'b0), // TQ output value when SR is used (1'b0,1'b1)
.TBYTE_CTL("FALSE"), // Enable tristate byte operation (FALSE, TRUE)
.TBYTE_SRC("FALSE"), // Tristate byte source (FALSE, TRUE)
.TRISTATE_WIDTH(4) // 3-state converter width (1,4)
) OSERDESE2_txdata
(
.OFB(), // 1-bit output: Feedback path for data
.OQ(tx_data[i]), // 1-bit output: Data path output
// SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
.SHIFTOUT1(),
.SHIFTOUT2(),
.TBYTEOUT(), // 1-bit output: Byte group tristate
.TFB(), // 1-bit output: 3-state control
.TQ(), // 1-bit output: 3-state control
.CLK(txlclk_s), // 1-bit input: High speed clock
.CLKDIV(txlclk_p), // 1-bit input: Divided clock
// D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
.D1(pdata[i+56]), // First data out
.D2(pdata[i+48]),
.D3(pdata[i+40]),
.D4(pdata[i+32]),
.D5(pdata[i+24]),
.D6(pdata[i+16]),
.D7(pdata[i+8]),
.D8(pdata[i]), // Last data out
.OCE(1'b1), // 1-bit input: Output data clock enable
.RST(ioreset), // 1-bit input: Reset
// SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
.SHIFTIN1(1'b0),
.SHIFTIN2(1'b0),
// T1 - T4: 1-bit (each) input: Parallel 3-state inputs
.T1(1'b0),
.T2(1'b0),
.T3(1'b0),
.T4(1'b0),
.TBYTEIN(1'b0), // 1-bit input: Byte group tristate
.TCE(1'b0) // 1-bit input: 3-state clock enable
);
end // block: gen_serdes
endgenerate
OSERDESE2
#(
.DATA_RATE_OQ("DDR"), // DDR, SDR
.DATA_RATE_TQ("DDR"), // DDR, BUF, SDR
.DATA_WIDTH(8), // Parallel data width (2-8,10,14)
.INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)
.INIT_TQ(1'b0), // Initial value of TQ output (1'b0,1'b1)
.SERDES_MODE("MASTER"), // MASTER, SLAVE
.SRVAL_OQ(1'b0), // OQ output value when SR is used (1'b0,1'b1)
.SRVAL_TQ(1'b0), // TQ output value when SR is used (1'b0,1'b1)
.TBYTE_CTL("FALSE"), // Enable tristate byte operation (FALSE, TRUE)
.TBYTE_SRC("FALSE"), // Tristate byte source (FALSE, TRUE)
.TRISTATE_WIDTH(4) // 3-state converter width (1,4)
) OSERDESE2_tframe
(
.OFB(), // 1-bit output: Feedback path for data
.OQ(tx_frame), // 1-bit output: Data path output
// SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
.SHIFTOUT1(),
.SHIFTOUT2(),
.TBYTEOUT(), // 1-bit output: Byte group tristate
.TFB(), // 1-bit output: 3-state control
.TQ(), // 1-bit output: 3-state control
.CLK(txlclk_s), // 1-bit input: High speed clock
.CLKDIV(txlclk_p), // 1-bit input: Divided clock
// D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
.D1(pframe[7]), // first data out
.D2(pframe[6]),
.D3(pframe[5]),
.D4(pframe[4]),
.D5(pframe[3]),
.D6(pframe[2]),
.D7(pframe[1]),
.D8(pframe[0]), // last data out
.OCE(1'b1), // 1-bit input: Output data clock enable
.RST(ioreset), // 1-bit input: Reset
// SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
.SHIFTIN1(1'b0),
.SHIFTIN2(1'b0),
// T1 - T4: 1-bit (each) input: Parallel 3-state inputs
.T1(1'b0),
.T2(1'b0),
.T3(1'b0),
.T4(1'b0),
.TBYTEIN(1'b0), // 1-bit input: Byte group tristate
.TCE(1'b0) // 1-bit input: 3-state clock enable
);
//################################
//# LClock Creation
//################################
ODDR
#(
.DDR_CLK_EDGE ("SAME_EDGE"),
.INIT (1'b0),
.SRTYPE ("ASYNC"))
oddr_lclk_inst
(
.Q (tx_lclk),
.C (txlclk_out),
.CE (1'b1),
.D1 (txenb),
.D2 (1'b0),
.R (1'b0),
.S (1'b0));
//################################
//# Output Buffers
//################################
OBUFTDS
#(
.IOSTANDARD(IOSTD_ELINK),
.SLEW("FAST")
) OBUFTDS_txdata [7:0]
(
.O (TX_DATA_P),
.OB (TX_DATA_N),
.I (tx_data),
.T (~ecfg_tx_enable)
);
OBUFDS
#(
.IOSTANDARD(IOSTD_ELINK),
.SLEW("FAST")
) OBUFDS_txframe
(
.O (TX_FRAME_P),
.OB (TX_FRAME_N),
.I (tx_frame)
);
OBUFDS
#(
.IOSTANDARD(IOSTD_ELINK),
.SLEW("FAST")
) OBUFDS_lclk
(
.O (TX_LCLK_P),
.OB (TX_LCLK_N),
.I (tx_lclk)
);
//################################
//# Wait Input Buffers
//################################
IBUFDS
#(.DIFF_TERM ("TRUE"), // Differential termination
.IOSTANDARD (IOSTD_ELINK))
ibufds_txwrwait
(.I (TX_WR_WAIT_P),
.IB (TX_WR_WAIT_N),
.O (tx_wr_wait));
// On Parallella this signal comes in single-ended
assign tx_rd_wait = TX_RD_WAIT_P;
endmodule // eio_rx

88
eio_tx/ip_prj/ip_prj.xpr Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2014.3 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="2" Path="/mnt/windowsC/Adapteva/Parallella/parallella-hwelink/fpga/src/eio_tx/ip_prj/ip_prj.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="261b285b2a9c45f2a7d6f9c30d7e39d7"/>
<Option Name="Part" Val="xc7z020clg400-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="BoardPart" Val=""/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="IPRepoPath" Val="$PPRDIR/../../../src"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../hdl/eio_tx.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../component.xml">
<FileInfo SFType="IPXACT"/>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="eio_tx"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Filter Type="Srcs"/>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="eio_tx"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="QuestaSim/ModelSim Simulator"/>
</Simulator>
<Simulator Name="IES">
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
</Simulator>
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="9">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2014"/>
<Step Id="synth_design"/>
</Strategy>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" State="current" SynthRun="synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
</Run>
</Runs>
</Project>

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eio_tx/xgui/eio_tx_v1_0.tcl Normal file
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# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
set Component_Name [ ipgui::add_param $IPINST -name "Component_Name" -display_name {Component Name}]
set_property tooltip {Component Name} ${Component_Name}
#Adding Page
set Page_0 [ ipgui::add_page $IPINST -name "Page 0" -display_name {Page 0}]
set_property tooltip {Page 0} ${Page_0}
set IOSTD_ELINK [ ipgui::add_param $IPINST -name "IOSTD_ELINK" -parent ${Page_0} -display_name {Iostd Elink}]
set_property tooltip {Iostd Elink} ${IOSTD_ELINK}
}
proc update_PARAM_VALUE.IOSTD_ELINK { PARAM_VALUE.IOSTD_ELINK } {
# Procedure called to update IOSTD_ELINK when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.IOSTD_ELINK { PARAM_VALUE.IOSTD_ELINK } {
# Procedure called to validate IOSTD_ELINK
return true
}
proc update_MODELPARAM_VALUE.IOSTD_ELINK { MODELPARAM_VALUE.IOSTD_ELINK PARAM_VALUE.IOSTD_ELINK } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.IOSTD_ELINK}] ${MODELPARAM_VALUE.IOSTD_ELINK}
}

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proc init { cellpath otherInfo } {
set cell_handle [get_bd_cells $cellpath]
set all_busif [get_bd_intf_pins $cellpath/*]
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
set full_sbusif_list [list ]
foreach busif $all_busif {
if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } {
set busif_param_list [list]
set busif_name [get_property NAME $busif]
if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } {
continue
}
foreach tparam $axi_standard_param_list {
lappend busif_param_list "C_${busif_name}_${tparam}"
}
bd::mark_propagate_only $cell_handle $busif_param_list
}
}
}
proc pre_propagate {cellpath otherInfo } {
set cell_handle [get_bd_cells $cellpath]
set all_busif [get_bd_intf_pins $cellpath/*]
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
foreach busif $all_busif {
if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
continue
}
if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } {
continue
}
set busif_name [get_property NAME $busif]
foreach tparam $axi_standard_param_list {
set busif_param_name "C_${busif_name}_${tparam}"
set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
if { $val_on_cell != "" } {
set_property CONFIG.${tparam} $val_on_cell $busif
}
}
}
}
}
proc propagate {cellpath otherInfo } {
set cell_handle [get_bd_cells $cellpath]
set all_busif [get_bd_intf_pins $cellpath/*]
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
foreach busif $all_busif {
if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
continue
}
if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } {
continue
}
set busif_name [get_property NAME $busif]
foreach tparam $axi_standard_param_list {
set busif_param_name "C_${busif_name}_${tparam}"
set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
#override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values..
if { $val_on_cell_intf_pin != "" } {
set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle
}
}
}
}
}

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emaxi/example_designs/bfm_design/design.tcl Normal file
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proc create_ipi_design { offsetfile design_name } {
create_bd_design $design_name
open_bd_design $design_name
# Create Clock and Reset Ports
set ACLK [ create_bd_port -dir I -type clk ACLK ]
set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.PHASE {0.000} CONFIG.CLK_DOMAIN "${design_name}_ACLK" ] $ACLK
set ARESETN [ create_bd_port -dir I -type rst ARESETN ]
set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW} ] $ARESETN
set_property CONFIG.ASSOCIATED_RESET ARESETN $ACLK
# Create instance: emaxi_0, and set properties
set emaxi_0 [ create_bd_cell -type ip -vlnv adapteva.com:Adapteva:emaxi:1.0 emaxi_0]
# Create External ports
set M00_AXI_INIT_AXI_TXN [ create_bd_port -dir I M00_AXI_INIT_AXI_TXN ]
set M00_AXI_ERROR [ create_bd_port -dir O M00_AXI_ERROR ]
set M00_AXI_TXN_DONE [ create_bd_port -dir O M00_AXI_TXN_DONE ]
# Create instance: slave_0, and set properties
set slave_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:cdn_axi_bfm slave_0]
set_property -dict [ list CONFIG.C_PROTOCOL_SELECTION {1} CONFIG.C_MODE_SELECT {1} CONFIG.C_S_AXI4_HIGHADDR {0x4000FFFF} CONFIG.C_S_AXI4_BASEADDR {0x40000000} CONFIG.C_S_AXI4_MEMORY_MODEL_MODE {1} ] $slave_0
connect_bd_intf_net [get_bd_intf_pins slave_0/S_AXI] [get_bd_intf_pins emaxi_0/M00_AXI]
# Create port connections
connect_bd_net -net aclk_net [get_bd_ports ACLK] [get_bd_pins slave_0/S_AXI_ACLK] [get_bd_pins emaxi_0/M00_AXI_ACLK]
connect_bd_net -net aresetn_net [get_bd_ports ARESETN] [get_bd_pins slave_0/S_AXI_ARESETN] [get_bd_pins emaxi_0/M00_AXI_ARESETN]
connect_bd_net -net init_axi_txn_00 [get_bd_ports M00_AXI_INIT_AXI_TXN] [get_bd_pins emaxi_0/M00_AXI_INIT_AXI_TXN]
connect_bd_net -net error_00 [get_bd_ports M00_AXI_ERROR] [get_bd_pins emaxi_0/M00_AXI_ERROR]
connect_bd_net -net txn_done_00 [get_bd_ports M00_AXI_TXN_DONE] [get_bd_pins emaxi_0/M00_AXI_TXN_DONE]
# Auto assign address
assign_bd_address
# Copy all address to interface_address.vh file
set bd_path [file dirname [get_property NAME [get_files ${design_name}.bd]]]
upvar 1 $offsetfile offset_file
set offset_file "${bd_path}/emaxi_v1_0_tb_include.vh"
set fp [open $offset_file "w"]
puts $fp "`ifndef emaxi_v1_0_tb_include_vh_"
puts $fp "`define emaxi_v1_0_tb_include_vh_\n"
puts $fp "//Configuration current bd names"
puts $fp "`define BD_INST_NAME ${design_name}_i"
puts $fp "`define BD_WRAPPER ${design_name}_wrapper\n"
puts $fp "//Configuration address parameters"
puts $fp "`endif"
close $fp
}
set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores adapteva.com:Adapteva:emaxi:1.0]]]]
set test_bench_file ${ip_path}/example_designs/bfm_design/emaxi_v1_0_tb.v
set interface_address_vh_file ""
# Set IP Repository and Update IP Catalogue
set repo_paths [get_property ip_repo_paths [current_fileset]]
if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } {
set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset]
update_ip_catalog
}
set design_name ""
set all_bd {}
set all_bd_files [get_files *.bd -quiet]
foreach file $all_bd_files {
set file_name [string range $file [expr {[string last "/" $file] + 1}] end]
set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]]
lappend all_bd $bd_name
}
for { set i 1 } { 1 } { incr i } {
set design_name "emaxi_v1_0_bfm_${i}"
if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } {
break
}
}
create_ipi_design interface_address_vh_file ${design_name}
validate_bd_design
set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force]
import_files -force -norecurse $wrapper_file
set_property SOURCE_SET sources_1 [get_filesets sim_1]
import_files -fileset sim_1 -norecurse -force $test_bench_file
remove_files -quiet -fileset sim_1 emaxi_v1_0_tb_include.vh
import_files -fileset sim_1 -norecurse -force $interface_address_vh_file
set_property top emaxi_v1_0_tb [get_filesets sim_1]
set_property top_lib {} [get_filesets sim_1]
set_property top_file {} [get_filesets sim_1]
launch_xsim -simset sim_1 -mode behavioral
restart
run 1000 us

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`timescale 1 ns / 1 ps
`include "emaxi_v1_0_tb_include.vh"
module emaxi_v1_0_tb;
reg tb_ACLK;
reg tb_ARESETn;
reg M00_AXI_INIT_AXI_TXN;
wire M00_AXI_TXN_DONE;
wire M00_AXI_ERROR;
// Create an instance of the example tb
`BD_WRAPPER dut (.ACLK(tb_ACLK),
.ARESETN(tb_ARESETn),
.M00_AXI_TXN_DONE(M00_AXI_TXN_DONE),
.M00_AXI_ERROR(M00_AXI_ERROR),
.M00_AXI_INIT_AXI_TXN(M00_AXI_INIT_AXI_TXN));
// Simple Reset Generator and test
initial begin
tb_ARESETn = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge tb_ACLK);
tb_ARESETn = 1'b1;
@(posedge tb_ACLK);
end
// Simple Clock Generator
initial tb_ACLK = 1'b0;
always #10 tb_ACLK = !tb_ACLK;
// Drive the BFM
initial begin
// Wait for end of reset
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
M00_AXI_INIT_AXI_TXN = 1'b0;
#500 M00_AXI_INIT_AXI_TXN = 1'b1;
$display("EXAMPLE TEST M00_AXI:");
wait( M00_AXI_TXN_DONE == 1'b1);
$display("M00_AXI: PTGEN_TEST_FINISHED!");
if ( M00_AXI_ERROR ) begin
$display("PTGEN_TEST: FAILED!");
end else begin
$display("PTGEN_TEST: PASSED!");
end
end
endmodule

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proc create_ipi_design { offsetfile design_name } {
create_bd_design $design_name
open_bd_design $design_name
# Create and configure Clock/Reset
create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz sys_clk_0
create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset sys_reset_0
#check if current_board is set, if true - figure out required clocks.
set is_board_clock_found 0
set is_board_reset_found 0
set external_reset_port ""
set external_clock_port ""
if { [current_board_part -quiet] != "" } {
#check if any reset interface exists in board.
set board_reset [lindex [get_board_part_interfaces -filter { BUSDEF_NAME == reset_rtl && MODE == slave }] 0 ]
if { $board_reset ne "" } {
set is_board_reset_found 1
apply_board_connection -board_interface $board_reset -ip_intf sys_clk_0/reset -diagram [current_bd_design]
apply_board_connection -board_interface $board_reset -ip_intf sys_reset_0/ext_reset -diagram [current_bd_design]
set external_rst [get_bd_ports -quiet -of_objects [get_bd_nets -quiet -of_objects [get_bd_pins -quiet sys_clk_0/reset]]]
if { $external_rst ne "" } {
set external_reset_port [get_property NAME $external_rst]
}
} else {
send_msg "ptgen 51-200" WARNING "No reset interface found in current_board, Users may need to specify the location constraints manually."
}
# check for differential clock, exclude any special clocks which has TYPE property.
set board_clock_busifs ""
foreach busif [get_board_part_interfaces -filter "BUSDEF_NAME == diff_clock_rtl"] {
set type [get_property PARAM.TYPE $busif]
if { $type == "" } {
set board_clock_busifs $busif
break
}
}
if { $board_clock_busifs ne "" } {
apply_board_connection -board_interface $board_clock_busifs -ip_intf sys_clk_0/CLK_IN1_D -diagram [current_bd_design]
set is_board_clock_found 1
} else {
# check for single ended clock
set board_sclock_busifs [lindex [get_board_part_interfaces -filter "BUSDEF_NAME == clock_rtl"] 0 ]
if { $board_sclock_busifs ne "" } {
apply_board_connection -board_interface $board_sclock_busifs -ip_intf sys_clk_0/clock_CLK_IN1 -diagram [current_bd_design]
set external_clk [get_bd_ports -quiet -of_objects [get_bd_nets -quiet -of_objects [get_bd_pins -quiet sys_clk_0/clk_in1]]]
if { $external_clk ne "" } {
set external_clock_port [get_property NAME $external_clk]
}
set is_board_clock_found 1
} else {
send_msg "ptgen 51-200" WARNING "No clock interface found in current_board, Users may need to specify the location constraints manually."
}
}
} else {
send_msg "ptgen 51-201" WARNING "No board selected in current_project. Users may need to specify the location constraints manually."
}
#if there is no corresponding board interface found, assume constraints will be provided manually while pin planning.
if { $is_board_reset_found == 0 } {
create_bd_port -dir I -type rst reset_rtl
set_property CONFIG.POLARITY [get_property CONFIG.POLARITY [get_bd_pins sys_clk_0/reset]] [get_bd_ports reset_rtl]
connect_bd_net [get_bd_pins sys_reset_0/ext_reset_in] [get_bd_ports reset_rtl]
connect_bd_net [get_bd_ports reset_rtl] [get_bd_pins sys_clk_0/reset]
set external_reset_port reset_rtl
}
if { $is_board_clock_found == 0 } {
create_bd_port -dir I -type clk clock_rtl
connect_bd_net [get_bd_pins sys_clk_0/clk_in1] [get_bd_ports clock_rtl]
set external_clock_port clock_rtl
}
#Avoid IPI DRC, make clock port synchronous to reset
if { $external_clock_port ne "" && $external_reset_port ne "" } {
set_property CONFIG.ASSOCIATED_RESET $external_reset_port [get_bd_ports $external_clock_port]
}
# Connect other sys_reset pins
connect_bd_net [get_bd_pins sys_reset_0/slowest_sync_clk] [get_bd_pins sys_clk_0/clk_out1]
connect_bd_net [get_bd_pins sys_clk_0/locked] [get_bd_pins sys_reset_0/dcm_locked]
# Create instance: emaxi_0, and set properties
set emaxi_0 [ create_bd_cell -type ip -vlnv adapteva.com:Adapteva:emaxi:1.0 emaxi_0 ]
# Create instance: jtag_axi_0, and set properties
set jtag_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi jtag_axi_0 ]
set_property -dict [list CONFIG.PROTOCOL {0}] [get_bd_cells jtag_axi_0]
connect_bd_net [get_bd_pins jtag_axi_0/aclk] [get_bd_pins sys_clk_0/clk_out1]
connect_bd_net [get_bd_pins jtag_axi_0/aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
# Create instance: axi_peri_interconnect, and set properties
set axi_peri_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_peri_interconnect ]
connect_bd_net [get_bd_pins axi_peri_interconnect/ACLK] [get_bd_pins sys_clk_0/clk_out1]
connect_bd_net [get_bd_pins axi_peri_interconnect/ARESETN] [get_bd_pins sys_reset_0/interconnect_aresetn]
set_property -dict [ list CONFIG.NUM_SI {1} ] $axi_peri_interconnect
connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
connect_bd_intf_net [get_bd_intf_pins jtag_axi_0/M_AXI] [get_bd_intf_pins axi_peri_interconnect/S00_AXI]
set_property -dict [ list CONFIG.NUM_MI {3} ] $axi_peri_interconnect
connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
connect_bd_net [get_bd_pins axi_peri_interconnect/M01_ACLK] [get_bd_pins sys_clk_0/clk_out1]
connect_bd_net [get_bd_pins axi_peri_interconnect/M01_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
connect_bd_net [get_bd_pins axi_peri_interconnect/M02_ACLK] [get_bd_pins sys_clk_0/clk_out1]
connect_bd_net [get_bd_pins axi_peri_interconnect/M02_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
# Create instance: axi_mem_interconnect, and set properties
set axi_mem_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_mem_interconnect ]
connect_bd_net [get_bd_pins axi_mem_interconnect/ACLK] [get_bd_pins sys_clk_0/clk_out1]
connect_bd_net [get_bd_pins axi_mem_interconnect/ARESETN] [get_bd_pins sys_reset_0/interconnect_aresetn]
set_property -dict [ list CONFIG.NUM_MI {1} ] $axi_mem_interconnect
connect_bd_net [get_bd_pins axi_mem_interconnect/M00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
connect_bd_net [get_bd_pins axi_mem_interconnect/M00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
set_property -dict [ list CONFIG.NUM_SI {2} ] $axi_mem_interconnect
connect_bd_net [get_bd_pins axi_mem_interconnect/S00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
connect_bd_net [get_bd_pins axi_mem_interconnect/S00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
connect_bd_net [get_bd_pins axi_mem_interconnect/S01_ACLK] [get_bd_pins sys_clk_0/clk_out1]
connect_bd_net [get_bd_pins axi_mem_interconnect/S01_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
connect_bd_intf_net [get_bd_intf_pins axi_mem_interconnect/S01_AXI] [get_bd_intf_pins axi_peri_interconnect/M00_AXI]
# Create instance: axi_bram_ctrl_0, and set properties
set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl axi_bram_ctrl_0 ]
connect_bd_intf_net [get_bd_intf_pins axi_mem_interconnect/M00_AXI] [get_bd_intf_pins axi_bram_ctrl_0/S_AXI]
connect_bd_net [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins sys_clk_0/clk_out1]
connect_bd_net [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
# Create instance: axi_bram_0, and set properties
set axi_bram_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen axi_bram_0 ]
set_property -dict [ list CONFIG.Memory_Type {True_Dual_Port_RAM} ] $axi_bram_0
connect_bd_intf_net [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA] [get_bd_intf_pins axi_bram_0/BRAM_PORTA]
connect_bd_intf_net [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTB] [get_bd_intf_pins axi_bram_0/BRAM_PORTB]
# Create instance: axi_gpio_out, and set properties
set axi_gpio_out [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio axi_gpio_out ]
set_property -dict [ list CONFIG.C_ALL_OUTPUTS {1} CONFIG.C_GPIO_WIDTH {1} ] $axi_gpio_out
connect_bd_net [get_bd_pins axi_gpio_out/s_axi_aclk] [get_bd_pins sys_clk_0/clk_out1]
connect_bd_net [get_bd_pins axi_gpio_out/s_axi_aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
connect_bd_intf_net [get_bd_intf_pins axi_gpio_out/S_AXI] [get_bd_intf_pins axi_peri_interconnect/M01_AXI]
# Create instance: axi_gpio_in, and set properties
set axi_gpio_in [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio axi_gpio_in ]
set_property -dict [ list CONFIG.C_ALL_INPUTS {1} CONFIG.C_GPIO_WIDTH {2} ] $axi_gpio_in
connect_bd_net [get_bd_pins axi_gpio_in/s_axi_aclk] [get_bd_pins sys_clk_0/clk_out1]
connect_bd_net [get_bd_pins axi_gpio_in/s_axi_aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
connect_bd_intf_net [get_bd_intf_pins axi_gpio_in/S_AXI] [get_bd_intf_pins axi_peri_interconnect/M02_AXI]
# Create instance: xlconcat_0, and set properties
set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat xlconcat_0 ]
set_property -dict [ list CONFIG.NUM_PORTS {2} ] $xlconcat_0
connect_bd_net [get_bd_pins xlconcat_0/dout] [get_bd_pins axi_gpio_in/gpio_io_i]
# Connect all clock, reset & status pins of emaxi_0 master interfaces..
connect_bd_intf_net [get_bd_intf_pins axi_mem_interconnect/S00_AXI] [get_bd_intf_pins emaxi_0/M00_AXI]
connect_bd_net [get_bd_pins emaxi_0/m00_axi_aclk] [get_bd_pins sys_clk_0/clk_out1]
connect_bd_net [get_bd_pins emaxi_0/m00_axi_aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
connect_bd_net [get_bd_pins emaxi_0/m00_axi_txn_done] [get_bd_pins xlconcat_0/In0]
connect_bd_net [get_bd_pins emaxi_0/m00_axi_error] [get_bd_pins xlconcat_0/In1]
connect_bd_net [get_bd_pins emaxi_0/m00_axi_init_axi_txn] [ get_bd_pins axi_gpio_out/gpio_io_o ]
# Auto assign address
assign_bd_address
# Configure address param & range of emaxi_0 master interfaces..
set_property range 16K [get_bd_addr_segs {jtag_axi_0/Data/SEG_axi_bram_ctrl_0_Mem0}]
set_property range 16K [get_bd_addr_segs {emaxi_0/M00_AXI/SEG_axi_bram_ctrl_0_Mem0}]
set_property -dict [list CONFIG.C_M00_AXI_TARGET_SLAVE_BASE_ADDR {0xC0000000} ] [get_bd_cells emaxi_0]
# Copy all address to emaxi_v1_0_include.tcl file
set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd
upvar 1 $offsetfile offset_file
set offset_file "${bd_path}/emaxi_v1_0_include.tcl"
set fp [open $offset_file "w"]
puts $fp "# Configuration address parameters"
set offset [get_property OFFSET [get_bd_addr_segs /jtag_axi_0/Data/SEG_axi_gpio_in_Reg ]]
puts $fp "set axi_gpio_in_addr ${offset}"
set offset [get_property OFFSET [get_bd_addr_segs /jtag_axi_0/Data/SEG_axi_gpio_out_Reg ]]
puts $fp "set axi_gpio_out_addr ${offset}"
close $fp
}
# Set IP Repository and Update IP Catalogue
set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores adapteva.com:Adapteva:emaxi:1.0]]]]
set hw_test_file ${ip_path}/example_designs/debug_hw_design/emaxi_v1_0_hw_test.tcl
set repo_paths [get_property ip_repo_paths [current_fileset]]
if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } {
set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset]
update_ip_catalog
}
set design_name ""
set all_bd {}
set all_bd_files [get_files *.bd -quiet]
foreach file $all_bd_files {
set file_name [string range $file [expr {[string last "/" $file] + 1}] end]
set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]]
lappend all_bd $bd_name
}
for { set i 1 } { 1 } { incr i } {
set design_name "emaxi_v1_0_hw_${i}"
if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } {
break
}
}
set intf_address_include_file ""
create_ipi_design intf_address_include_file ${design_name}
save_bd_design
validate_bd_design
set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force]
import_files -force -norecurse $wrapper_file
puts "-------------------------------------------------------------------------------------------------"
puts "INFO NEXT STEPS : Until this stage, debug hardware design has been created, "
puts " please perform following steps to test design in targeted board."
puts "1. Generate bitstream"
puts "2. Setup your targeted board, open hardware manager and open new(or existing) hardware target"
puts "3. Download generated bitstream"
puts "4. Run generated hardware test using below command, this invokes basic read/write operation"
puts " to every interface present in the peripheral : xilinx.com:user:myip:1.0"
puts " : source -notrace ${hw_test_file}"
puts "-------------------------------------------------------------------------------------------------"

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# Runtime Tcl commands to interact with - emaxi_v1_0
# Sourcing design address info tcl
set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd
source ${bd_path}/emaxi_v1_0_include.tcl
# jtag axi master interface hardware name, change as per your design.
set jtag_axi_master hw_axi_1
set ec 0
# hw test script
# Delete all previous axis transactions
if { [llength [get_hw_axi_txns -quiet]] } {
delete_hw_axi_txn [get_hw_axi_txns -quiet]
}
# Master Tests..
# CIP Master performs write and read transaction followed by data comparison.
# To initiate the master "init_axi_txn" port needs to be asserted high. The same assertion is done by axi_gpio_out driven by jtag_axi_lite master.
# Writing 32'b1 to axi_gpio_out reg will initiate the first master. Subsequent masters will take following gpio bits.
# Master 0 init_axi_txn is controlled by bit_0 of axi_gpio_out while bit_1 initiates Master 1.
# To monitor the result of the data comparison by Master 0, error and done flags are being monitored by axi_gpio_in.
# Reading bit 0 of gpio_1_reg gives the done status of the master transaction while bit 1 gives the error
# status of the transaction initiated by the master. bit_0 being '1' means the transaction is complete
# while bit_1 being 1 means the transaction is completed with error. The status of subsequent masters
# will take up higher order bits in the same order. Master 1 has bit_2 as done bit, bit_3 as error bit.
# Utility procs
proc get_done_and_error_bit { rdata totmaster position } {
# position can be 0 1 2 3 ...
# Always Done is at sequence of bit 0 & error is at bit 1 position.
set hexdata [string range $rdata 0 7 ]
# In case of 64 bit data width
#set hexdata [string range $rdata 8 15 ]
binary scan [binary format H* $hexdata] B* bindata
set bindata [string range $bindata [expr 32 - $totmaster * 2] 31 ]
set DE [string range $bindata [ expr ($totmaster - ($position + 1) ) * 2 ] [expr ($totmaster - ($position + 1) ) * 2 + 1] ]
return $DE
}
proc bin2hex {bin} {
set result ""
set prepend [string repeat 0 [expr (4-[string length $bin]%4)%4]]
foreach g [regexp -all -inline {[01]{4}} $prepend$bin] {
foreach {b3 b2 b1 b0} [split $g ""] {
append result [format %X [expr {$b3*8+$b2*4+$b1*2+$b0}]]
}
}
return $result
}
proc get_init_data { position } {
# position can be 0, 1, 2, 3, 4...15
set initbit 00000000000000000000000000000000
set position [ expr 31 - $position ]
set newinitbit [string replace $initbit $position $position 1]
set hexdata [bin2hex $newinitbit]
return $hexdata
}
# Test: M00_AXI
set wdata_m00_axi [get_init_data 0]
create_hw_axi_txn w_m00_axi_addr [get_hw_axis $jtag_axi_master] -type write -address $axi_gpio_out_addr -data ${wdata_m00_axi}
create_hw_axi_txn r_m00_axi_addr [get_hw_axis $jtag_axi_master] -type read -address $axi_gpio_in_addr
# Initiate transactions
run_hw_axi r_m00_axi_addr
run_hw_axi w_m00_axi_addr
run_hw_axi r_m00_axi_addr
set rdata_tmp [get_property DATA [get_hw_axi_txn r_m00_axi_addr]]
set DE [ get_done_and_error_bit $rdata_tmp 1 0 ]
# Compare read data
if { $DE == 01 } {
puts "Data comparison test pass for - M00_AXI"
} else {
puts "Data comparison test fail for - M00_AXI, rdata-$rdata_tmp expected-01 actual-$DE"
inc ec
}
# Check error flag
if { $ec == 0 } {
puts "PTGEN_TEST: PASSED!"
} else {
puts "PTGEN_TEST: FAILED!"
}

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`timescale 1 ns / 1 ps
module emaxi_v1_0 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Master Bus Interface M00_AXI
parameter C_M00_AXI_TARGET_SLAVE_BASE_ADDR = 32'h40000000,
parameter integer C_M00_AXI_BURST_LEN = 16,
parameter integer C_M00_AXI_ID_WIDTH = 1,
parameter integer C_M00_AXI_ADDR_WIDTH = 32,
parameter integer C_M00_AXI_DATA_WIDTH = 32,
parameter integer C_M00_AXI_AWUSER_WIDTH = 0,
parameter integer C_M00_AXI_ARUSER_WIDTH = 0,
parameter integer C_M00_AXI_WUSER_WIDTH = 0,
parameter integer C_M00_AXI_RUSER_WIDTH = 0,
parameter integer C_M00_AXI_BUSER_WIDTH = 0
)
(
// Users to add ports here
// FIFO read-master port, writes from RX channel
input wire [102:0] emwr_rd_data,
output wire emwr_rd_en,
input wire emwr_empty,
// FIFO read-master port, read requests from RX channel
input wire [102:0] emrq_rd_data,
output wire emrq_rd_en,
input wire emrq_empty,
// FIFO write-master port, read responses to TX channel
output wire [102:0] emrr_wr_data,
output wire emrr_wr_en,
input wire emrr_full,
input wire emrr_prog_full,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Master Bus Interface M00_AXI
input wire m00_axi_aclk,
input wire m00_axi_aresetn,
output wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_awid,
output wire [C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_awaddr,
output wire [7 : 0] m00_axi_awlen,
output wire [2 : 0] m00_axi_awsize,
output wire [1 : 0] m00_axi_awburst,
output wire m00_axi_awlock,
output wire [3 : 0] m00_axi_awcache,
output wire [2 : 0] m00_axi_awprot,
output wire [3 : 0] m00_axi_awqos,
output wire [C_M00_AXI_AWUSER_WIDTH-1 : 0] m00_axi_awuser,
output wire m00_axi_awvalid,
input wire m00_axi_awready,
output wire [C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_wdata,
output wire [C_M00_AXI_DATA_WIDTH/8-1 : 0] m00_axi_wstrb,
output wire m00_axi_wlast,
output wire [C_M00_AXI_WUSER_WIDTH-1 : 0] m00_axi_wuser,
output wire m00_axi_wvalid,
input wire m00_axi_wready,
input wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_bid,
input wire [1 : 0] m00_axi_bresp,
input wire [C_M00_AXI_BUSER_WIDTH-1 : 0] m00_axi_buser,
input wire m00_axi_bvalid,
output wire m00_axi_bready,
output wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_arid,
output wire [C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_araddr,
output wire [7 : 0] m00_axi_arlen,
output wire [2 : 0] m00_axi_arsize,
output wire [1 : 0] m00_axi_arburst,
output wire m00_axi_arlock,
output wire [3 : 0] m00_axi_arcache,
output wire [2 : 0] m00_axi_arprot,
output wire [3 : 0] m00_axi_arqos,
output wire [C_M00_AXI_ARUSER_WIDTH-1 : 0] m00_axi_aruser,
output wire m00_axi_arvalid,
input wire m00_axi_arready,
input wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_rid,
input wire [C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_rdata,
input wire [1 : 0] m00_axi_rresp,
input wire m00_axi_rlast,
input wire [C_M00_AXI_RUSER_WIDTH-1 : 0] m00_axi_ruser,
input wire m00_axi_rvalid,
output wire m00_axi_rready
);
// Instantiation of Axi Bus Interface M00_AXI
emaxi_v1_0_M00_AXI # (
.C_M_TARGET_SLAVE_BASE_ADDR(C_M00_AXI_TARGET_SLAVE_BASE_ADDR),
.C_M_AXI_BURST_LEN(C_M00_AXI_BURST_LEN),
.C_M_AXI_ID_WIDTH(C_M00_AXI_ID_WIDTH),
.C_M_AXI_ADDR_WIDTH(C_M00_AXI_ADDR_WIDTH),
.C_M_AXI_DATA_WIDTH(C_M00_AXI_DATA_WIDTH),
.C_M_AXI_AWUSER_WIDTH(C_M00_AXI_AWUSER_WIDTH),
.C_M_AXI_ARUSER_WIDTH(C_M00_AXI_ARUSER_WIDTH),
.C_M_AXI_WUSER_WIDTH(C_M00_AXI_WUSER_WIDTH),
.C_M_AXI_RUSER_WIDTH(C_M00_AXI_RUSER_WIDTH),
.C_M_AXI_BUSER_WIDTH(C_M00_AXI_BUSER_WIDTH)
) emaxi_v1_0_M00_AXI_inst (
.emwr_rd_data(emwr_rd_data),
.emwr_rd_en(emwr_rd_en),
.emwr_empty(emwr_empty),
.emrq_rd_data(emrq_rd_data),
.emrq_rd_en(emrq_rd_en),
.emrq_empty(emrq_empty),
.emrr_wr_data(emrr_wr_data),
.emrr_wr_en(emrr_wr_en),
.emrr_full(emrr_full),
.emrr_prog_full(emrr_prog_full),
.M_AXI_ACLK(m00_axi_aclk),
.M_AXI_ARESETN(m00_axi_aresetn),
.M_AXI_AWID(m00_axi_awid),
.M_AXI_AWADDR(m00_axi_awaddr),
.M_AXI_AWLEN(m00_axi_awlen),
.M_AXI_AWSIZE(m00_axi_awsize),
.M_AXI_AWBURST(m00_axi_awburst),
.M_AXI_AWLOCK(m00_axi_awlock),
.M_AXI_AWCACHE(m00_axi_awcache),
.M_AXI_AWPROT(m00_axi_awprot),
.M_AXI_AWQOS(m00_axi_awqos),
.M_AXI_AWUSER(m00_axi_awuser),
.M_AXI_AWVALID(m00_axi_awvalid),
.M_AXI_AWREADY(m00_axi_awready),
.M_AXI_WDATA(m00_axi_wdata),
.M_AXI_WSTRB(m00_axi_wstrb),
.M_AXI_WLAST(m00_axi_wlast),
.M_AXI_WUSER(m00_axi_wuser),
.M_AXI_WVALID(m00_axi_wvalid),
.M_AXI_WREADY(m00_axi_wready),
.M_AXI_BID(m00_axi_bid),
.M_AXI_BRESP(m00_axi_bresp),
.M_AXI_BUSER(m00_axi_buser),
.M_AXI_BVALID(m00_axi_bvalid),
.M_AXI_BREADY(m00_axi_bready),
.M_AXI_ARID(m00_axi_arid),
.M_AXI_ARADDR(m00_axi_araddr),
.M_AXI_ARLEN(m00_axi_arlen),
.M_AXI_ARSIZE(m00_axi_arsize),
.M_AXI_ARBURST(m00_axi_arburst),
.M_AXI_ARLOCK(m00_axi_arlock),
.M_AXI_ARCACHE(m00_axi_arcache),
.M_AXI_ARPROT(m00_axi_arprot),
.M_AXI_ARQOS(m00_axi_arqos),
.M_AXI_ARUSER(m00_axi_aruser),
.M_AXI_ARVALID(m00_axi_arvalid),
.M_AXI_ARREADY(m00_axi_arready),
.M_AXI_RID(m00_axi_rid),
.M_AXI_RDATA(m00_axi_rdata),
.M_AXI_RRESP(m00_axi_rresp),
.M_AXI_RLAST(m00_axi_rlast),
.M_AXI_RUSER(m00_axi_ruser),
.M_AXI_RVALID(m00_axi_rvalid),
.M_AXI_RREADY(m00_axi_rready)
);
// Add user logic here
// User logic ends
endmodule

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/*
Copyright (C) 2014 Adapteva, Inc.
Contributed by Fred Huettig <fred@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
/*
########################################################################
Epiphany eLink AXI Master Module
########################################################################
*/
`define WRITE_BIT 102
`define DATAMODE_RANGE 101:100
`define CTRLMODE_RANGE 99:96
`define DSTADDR_RANGE 95:64
`define DSTADDR_LSB 64
`define SRCADDR_RANGE 63:32
`define SRCADDR_LSB 32
`define DATA_RANGE 31:0
`define DATA_LSB 0
`timescale 1 ns / 1 ps
module emaxi_v1_0_M00_AXI #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Base address of targeted slave
parameter C_M_TARGET_SLAVE_BASE_ADDR = 32'h40000000,
// Burst Length. Supports 1, 2, 4, 8, 16, 32, 64, 128, 256 burst lengths
parameter integer C_M_AXI_BURST_LEN = 16,
// Thread ID Width
parameter integer C_M_AXI_ID_WIDTH = 1,
// Width of Address Bus
parameter integer C_M_AXI_ADDR_WIDTH = 32,
// Width of Data Bus
parameter integer C_M_AXI_DATA_WIDTH = 64,
// Width of User Write Address Bus
parameter integer C_M_AXI_AWUSER_WIDTH = 0,
// Width of User Read Address Bus
parameter integer C_M_AXI_ARUSER_WIDTH = 0,
// Width of User Write Data Bus
parameter integer C_M_AXI_WUSER_WIDTH = 0,
// Width of User Read Data Bus
parameter integer C_M_AXI_RUSER_WIDTH = 0,
// Width of User Response Bus
parameter integer C_M_AXI_BUSER_WIDTH = 0
)
(
// Users to add ports here
// FIFO read-master port, writes from RX channel
input wire [102:0] emwr_rd_data,
output wire emwr_rd_en,
input wire emwr_empty,
// FIFO read-master port, read requests from RX channel
input wire [102:0] emrq_rd_data,
output wire emrq_rd_en,
input wire emrq_empty,
// FIFO write-master port, read responses to TX channel
output reg [102:0] emrr_wr_data,
output reg emrr_wr_en,
input wire emrr_full,
input wire emrr_prog_full,
// User ports ends
// Do not modify the ports beyond this line
// Global Clock Signal.
input wire M_AXI_ACLK,
// Global Reset Singal. This Signal is Active Low
input wire M_AXI_ARESETN,
// Master Interface Write Address ID
output wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_AWID,
// Master Interface Write Address
output wire [C_M_AXI_ADDR_WIDTH-1 : 0] M_AXI_AWADDR,
// Burst length. The burst length gives the exact number of transfers in a burst
output wire [7 : 0] M_AXI_AWLEN,
// Burst size. This signal indicates the size of each transfer in the burst
output wire [2 : 0] M_AXI_AWSIZE,
// Burst type. The burst type and the size information,
// determine how the address for each transfer within the burst is calculated.
output wire [1 : 0] M_AXI_AWBURST,
// Lock type. Provides additional information about the
// atomic characteristics of the transfer.
output wire M_AXI_AWLOCK,
// Memory type. This signal indicates how transactions
// are required to progress through a system.
output wire [3 : 0] M_AXI_AWCACHE,
// Protection type. This signal indicates the privilege
// and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
output wire [2 : 0] M_AXI_AWPROT,
// Quality of Service, QoS identifier sent for each write transaction.
output wire [3 : 0] M_AXI_AWQOS,
// Optional User-defined signal in the write address channel.
output wire [C_M_AXI_AWUSER_WIDTH-1 : 0] M_AXI_AWUSER,
// Write address valid. This signal indicates that
// the channel is signaling valid write address and control information.
output wire M_AXI_AWVALID,
// Write address ready. This signal indicates that
// the slave is ready to accept an address and associated control signals
input wire M_AXI_AWREADY,
// Master Interface Write Data.
output wire [C_M_AXI_DATA_WIDTH-1 : 0] M_AXI_WDATA,
// Write strobes. This signal indicates which byte
// lanes hold valid data. There is one write strobe
// bit for each eight bits of the write data bus.
output wire [C_M_AXI_DATA_WIDTH/8-1 : 0] M_AXI_WSTRB,
// Write last. This signal indicates the last transfer in a write burst.
output wire M_AXI_WLAST,
// Optional User-defined signal in the write data channel.
output wire [C_M_AXI_WUSER_WIDTH-1 : 0] M_AXI_WUSER,
// Write valid. This signal indicates that valid write
// data and strobes are available
output wire M_AXI_WVALID,
// Write ready. This signal indicates that the slave
// can accept the write data.
input wire M_AXI_WREADY,
// Master Interface Write Response.
input wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_BID,
// Write response. This signal indicates the status of the write transaction.
input wire [1 : 0] M_AXI_BRESP,
// Optional User-defined signal in the write response channel
input wire [C_M_AXI_BUSER_WIDTH-1 : 0] M_AXI_BUSER,
// Write response valid. This signal indicates that the
// channel is signaling a valid write response.
input wire M_AXI_BVALID,
// Response ready. This signal indicates that the master
// can accept a write response.
output wire M_AXI_BREADY,
// Master Interface Read Address.
output wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_ARID,
// Read address. This signal indicates the initial
// address of a read burst transaction.
output wire [C_M_AXI_ADDR_WIDTH-1 : 0] M_AXI_ARADDR,
// Burst length. The burst length gives the exact number of transfers in a burst
output wire [7 : 0] M_AXI_ARLEN,
// Burst size. This signal indicates the size of each transfer in the burst
output wire [2 : 0] M_AXI_ARSIZE,
// Burst type. The burst type and the size information,
// determine how the address for each transfer within the burst is calculated.
output wire [1 : 0] M_AXI_ARBURST,
// Lock type. Provides additional information about the
// atomic characteristics of the transfer.
output wire M_AXI_ARLOCK,
// Memory type. This signal indicates how transactions
// are required to progress through a system.
output wire [3 : 0] M_AXI_ARCACHE,
// Protection type. This signal indicates the privilege
// and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
output wire [2 : 0] M_AXI_ARPROT,
// Quality of Service, QoS identifier sent for each read transaction
output wire [3 : 0] M_AXI_ARQOS,
// Optional User-defined signal in the read address channel.
output wire [C_M_AXI_ARUSER_WIDTH-1 : 0] M_AXI_ARUSER,
// Write address valid. This signal indicates that
// the channel is signaling valid read address and control information
output wire M_AXI_ARVALID,
// Read address ready. This signal indicates that
// the slave is ready to accept an address and associated control signals
input wire M_AXI_ARREADY,
// Read ID tag. This signal is the identification tag
// for the read data group of signals generated by the slave.
input wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_RID,
// Master Read Data
input wire [C_M_AXI_DATA_WIDTH-1 : 0] M_AXI_RDATA,
// Read response. This signal indicates the status of the read transfer
input wire [1 : 0] M_AXI_RRESP,
// Read last. This signal indicates the last transfer in a read burst
input wire M_AXI_RLAST,
// Optional User-defined signal in the read address channel.
input wire [C_M_AXI_RUSER_WIDTH-1 : 0] M_AXI_RUSER,
// Read valid. This signal indicates that the channel
// is signaling the required read data.
input wire M_AXI_RVALID,
// Read ready. This signal indicates that the master can
// accept the read data and response information.
output wire M_AXI_RREADY
);
// function called clogb2 that returns an integer which has the
//value of the ceiling of the log base 2
// function called clogb2 that returns an integer which has the
// value of the ceiling of the log base 2.
function integer clogb2 (input integer bit_depth);
begin
for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
bit_depth = bit_depth >> 1;
end
endfunction // clogb2
// AXI4LITE signals
//AXI4 internal temp signals
reg [C_M_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
reg [7:0] axi_awlen;
reg [2:0] axi_awsize;
reg axi_awvalid;
reg [C_M_AXI_DATA_WIDTH-1 : 0] axi_wdata;
reg [C_M_AXI_DATA_WIDTH/8-1 : 0] axi_wstrb;
reg axi_wlast;
reg axi_wvalid;
//reg axi_bready;
reg [C_M_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
reg [7:0] axi_arlen;
reg [2:0] axi_arsize;
reg axi_arvalid;
wire axi_rready;
// I/O Connections assignments
//I/O Connections. Write Address (AW)
assign M_AXI_AWID = 'b0;
//The AXI address is a concatenation of the target base address + active offset range
assign M_AXI_AWADDR = axi_awaddr;
//Burst LENgth is number of transaction beats, minus 1
assign M_AXI_AWLEN = axi_awlen;
//Size should be C_M_AXI_DATA_WIDTH, in 2^SIZE bytes, otherwise narrow bursts are used
assign M_AXI_AWSIZE = axi_awsize;
//INCR burst type is usually used, except for keyhole bursts
assign M_AXI_AWBURST = 2'b01;
assign M_AXI_AWLOCK = 1'b0;
//Update value to 4'b0011 if coherent accesses to be used via the Zynq ACP port. Not Allocated, Modifiable, not Bufferable. Not Bufferable since this example is meant to test memory, not intermediate cache.
assign M_AXI_AWCACHE = 4'b0010;
assign M_AXI_AWPROT = 3'h0;
assign M_AXI_AWQOS = 4'h0;
assign M_AXI_AWUSER = 'b1;
assign M_AXI_AWVALID = axi_awvalid;
//Write Data(W)
assign M_AXI_WDATA = axi_wdata;
//All bursts are complete and aligned in this example
assign M_AXI_WSTRB = axi_wstrb;
assign M_AXI_WLAST = axi_wlast;
assign M_AXI_WUSER = 'b0;
assign M_AXI_WVALID = axi_wvalid;
//Write Response (B)
assign M_AXI_BREADY = 1'b1; // axi_bready;
//Read Address (AR)
assign M_AXI_ARID = 'b0;
assign M_AXI_ARADDR = axi_araddr;
//Burst LENgth is number of transaction beats, minus 1
assign M_AXI_ARLEN = axi_arlen;
//Size should be C_M_AXI_DATA_WIDTH, in 2^n bytes, otherwise narrow bursts are used
assign M_AXI_ARSIZE = axi_arsize;
//INCR burst type is usually used, except for keyhole bursts
assign M_AXI_ARBURST = 2'b01;
assign M_AXI_ARLOCK = 1'b0;
//Update value to 4'b0011 if coherent accesses to be used via the Zynq ACP port. Not Allocated, Modifiable, not Bufferable. Not Bufferable since this example is meant to test memory, not intermediate cache.
assign M_AXI_ARCACHE = 4'b0010;
assign M_AXI_ARPROT = 3'h0;
assign M_AXI_ARQOS = 4'h0;
assign M_AXI_ARUSER = 'b1;
assign M_AXI_ARVALID = axi_arvalid;
//Read and Read Response (R)
assign M_AXI_RREADY = axi_rready;
//--------------------
//Write Address Channel
//--------------------
reg aw_wait;
reg w_wait;
assign emwr_rd_en = ( ~emwr_empty & ~axi_awvalid & ~axi_wvalid )
| ( ~emwr_empty & axi_awvalid & M_AXI_AWREADY & axi_wvalid & M_AXI_WREADY)
| ( ~emwr_empty & axi_awvalid & M_AXI_AWREADY & w_wait )
| ( ~emwr_empty & axi_wvalid & M_AXI_WREADY & aw_wait );
// Generate valid signals, internal waits
always @( posedge M_AXI_ACLK ) begin
if( M_AXI_ARESETN == 1'b0 ) begin
axi_awvalid <= 1'b0;
axi_wvalid <= 1'b0;
aw_wait <= 1'b0;
w_wait <= 1'b0;
end else begin
if( ~axi_awvalid & emwr_rd_en )
axi_awvalid <= 1'b1;
else if( axi_awvalid & M_AXI_AWREADY & ( emwr_empty | aw_wait ))
axi_awvalid <= 1'b0;
if( ~emwr_empty & axi_awvalid & M_AXI_AWREADY & ~M_AXI_WREADY )
aw_wait <= 1'b1;
else if( emwr_rd_en )
aw_wait <= 1'b0;
if( ~axi_wvalid & emwr_rd_en )
axi_wvalid <= 1'b1;
else if( axi_wvalid & M_AXI_WREADY & ( emwr_empty | w_wait ))
axi_wvalid <= 1'b0;
if( ~emwr_empty & axi_wvalid & M_AXI_WREADY & ~M_AXI_AWREADY )
w_wait <= 1'b1;
else if( emwr_rd_en )
w_wait <= 1'b0;
end // else: !if( M_AXI_ARESETN == 1'b0 )
end // always @ ( posedge M_AXI_ACLK )
// Put the address, info, & data on the AXI signals
always @( posedge M_AXI_ACLK ) begin
if( M_AXI_ARESETN == 1'b0 ) begin
axi_awaddr <= 'd0;
axi_awlen <= 'd0;
axi_awsize <= 'd0;
axi_wdata <= 'd0;
axi_wstrb <= 'd0;
axi_wlast <= 1'b1; // TODO: no bursts for now
end else begin
if( ~axi_awvalid | M_AXI_AWREADY ) begin
axi_awaddr <= emwr_rd_data[`DSTADDR_RANGE];
axi_awlen <= 'd0;
axi_awsize <= {1'b0, emwr_rd_data[`DATAMODE_RANGE]};
end
if( ~axi_wvalid | M_AXI_WREADY ) begin
// Place data of stated size in all legal positions
case( emwr_rd_data[`DATAMODE_RANGE] )
2'd0: axi_wdata <= { 8{emwr_rd_data[`DATA_LSB+7 -: 8]}};
2'd1: axi_wdata <= { 4{emwr_rd_data[`DATA_LSB+15 -: 16]}};
2'd2: axi_wdata <= { 2{emwr_rd_data[`DATA_LSB+31 -: 32]}};
default: axi_wdata <= { emwr_rd_data[`SRCADDR_RANGE],
emwr_rd_data[`DATA_RANGE]};
endcase // case ( emwr_rd_data[`DATAMODE_RANGE] )
// Create write strobes
case( emwr_rd_data[`DATAMODE_RANGE] )
2'd0: // BYTE
case( emwr_rd_data[`DSTADDR_LSB+2 -: 3] )
3'd0: axi_wstrb <= 8'h01;
3'd1: axi_wstrb <= 8'h02;
3'd2: axi_wstrb <= 8'h04;
3'd3: axi_wstrb <= 8'h08;
3'd4: axi_wstrb <= 8'h10;
3'd5: axi_wstrb <= 8'h20;
3'd6: axi_wstrb <= 8'h40;
default: axi_wstrb <= 8'h80;
endcase
2'd1: // 16b HWORD
case( emwr_rd_data[`DSTADDR_LSB+2 -: 2] )
2'd0: axi_wstrb <= 8'h03;
2'd1: axi_wstrb <= 8'h0C;
2'd2: axi_wstrb <= 8'h30;
default: axi_wstrb <= 8'hC0;
endcase
2'd2: // 32b WORD
if( emwr_rd_data[`DSTADDR_LSB+2] )
axi_wstrb <= 8'hF0;
else
axi_wstrb <= 8'h0F;
default: // 64b DWORD
axi_wstrb <= 8'hFF;
endcase // case ( emwr_rd_data[`DATAMODE_RANGE] )
end // if ( ~axi_wvalid | M_AXI_WREADY )
end // else: !if( M_AXI_ARESETN == 1'b0 )
end // always @ ( posedge M_AXI_ACLK )
//----------------------------
// Read Address Channel
//----------------------------
reg read_waiting;
assign emrq_rd_en = axi_rready & M_AXI_RVALID;
always @( posedge M_AXI_ACLK ) begin
if ( ~M_AXI_ARESETN ) begin
axi_araddr <= 'd0;
axi_arlen <= 'd0;
axi_arsize <= 'd0;
axi_arvalid <= 1'b0;
read_waiting <= 1'b0;
end else begin
if( ~emrq_empty & ~read_waiting ) begin
axi_arvalid <= 1'b1;
axi_arsize <= {1'b0, emrq_rd_data[`DATAMODE_RANGE]};
axi_araddr <= emrq_rd_data[`DSTADDR_RANGE];
end else if( M_AXI_ARREADY ) begin
axi_arvalid <= 1'b0;
end
if( ~emrq_empty & ~read_waiting )
read_waiting <= 1'b1;
else if( axi_rready & M_AXI_RVALID )
read_waiting <= 1'b0;
end
end // always @ ( posedge M_AXI_ACLK )
//--------------------------------
// Read Data (and Response) Channel
//--------------------------------
assign axi_rready = ~emrr_full;
always @( posedge M_AXI_ACLK ) begin
if( ~M_AXI_ARESETN ) begin
emrr_wr_data <= 'd0;
emrr_wr_en <= 1'b0;
end else begin
emrr_wr_en <= axi_rready & M_AXI_RVALID;
emrr_wr_data[`WRITE_BIT] <= 1'b1;
emrr_wr_data[`DATAMODE_RANGE] <= emrq_rd_data[`DATAMODE_RANGE];
emrr_wr_data[`CTRLMODE_RANGE] <= emrq_rd_data[`CTRLMODE_RANGE]; // TODO: This or cfg value?
emrr_wr_data[`DSTADDR_RANGE] <= emrq_rd_data[`SRCADDR_RANGE];
emrr_wr_data[`SRCADDR_RANGE] <= M_AXI_RDATA[63:32]; // only used for 64b reads
emrr_wr_data[`DATA_RANGE] <= M_AXI_RDATA[31:0];
// Steer read data according to size & host address lsbs
case( emrq_rd_data[`DATAMODE_RANGE] )
2'd0: // BYTE read
case( emrq_rd_data[`DSTADDR_LSB+2 -: 3] )
3'd0: emrr_wr_data[`DATA_LSB+7 -: 8] <= M_AXI_RDATA[7:0];
3'd1: emrr_wr_data[`DATA_LSB+7 -: 8] <= M_AXI_RDATA[15:8];
3'd2: emrr_wr_data[`DATA_LSB+7 -: 8] <= M_AXI_RDATA[23:16];
3'd3: emrr_wr_data[`DATA_LSB+7 -: 8] <= M_AXI_RDATA[31:24];
3'd4: emrr_wr_data[`DATA_LSB+7 -: 8] <= M_AXI_RDATA[39:32];
3'd5: emrr_wr_data[`DATA_LSB+7 -: 8] <= M_AXI_RDATA[47:40];
3'd6: emrr_wr_data[`DATA_LSB+7 -: 8] <= M_AXI_RDATA[55:48];
default: emrr_wr_data[`DATA_LSB+7 -: 8] <= M_AXI_RDATA[63:56];
endcase // case ( emrq_rd_data[`DSTADDR_LSB+2 -: 3] )
2'd1: // 16b HWORD
case( emrq_rd_data[`DSTADDR_LSB+2 -: 2] )
2'd0: emrr_wr_data[`DATA_LSB+15 -: 16] <= M_AXI_RDATA[15:0];
2'd1: emrr_wr_data[`DATA_LSB+15 -: 16] <= M_AXI_RDATA[31:16];
2'd2: emrr_wr_data[`DATA_LSB+15 -: 16] <= M_AXI_RDATA[47:32];
default: emrr_wr_data[`DATA_LSB+15 -: 16] <= M_AXI_RDATA[63:48];
endcase // case ( emrq_rd_data[`DSTADDR_LSB+2 -: 2] )
2'd2: // 32b WORD
if( emrq_rd_data[`DSTADDR_LSB+2] )
emrr_wr_data[`DATA_RANGE] <= M_AXI_RDATA[63:32];
// 32b w/0 offset handled by default
// 64b word already defined by defaults above
endcase
end // else: !if( ~M_AXI_ARESETN )
end // always @ ( posedge M_AXI_ACLK )
endmodule

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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2014.3 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="2" Path="/mnt/windowsC/Adapteva/Parallella/parallella-hwelink/fpga/src/emaxi/ip_prj/ip_prj.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="bde46b17430e4506bc3de032c2ced18b"/>
<Option Name="Part" Val="xc7z020clg400-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="BoardPart" Val=""/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="IPRepoPath" Val="$PPRDIR/../../../src"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../hdl/emaxi_v1_0_M00_AXI.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../hdl/emaxi_v1_0.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../component.xml">
<FileInfo SFType="IPXACT"/>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="emaxi_v1_0"/>
<Option Name="TopRTLFile" Val="$PPRDIR/../hdl/emaxi_v1_0.v"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Filter Type="Srcs"/>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="emaxi_v1_0"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="QuestaSim/ModelSim Simulator"/>
</Simulator>
<Simulator Name="IES">
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
</Simulator>
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="9">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2014"/>
<Step Id="synth_design"/>
</Strategy>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" State="current" SynthRun="synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
</Run>
</Runs>
</Project>

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# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
set Component_Name [ ipgui::add_param $IPINST -name "Component_Name" -display_name {Component Name}]
set_property tooltip {Component Name} ${Component_Name}
#Adding Page
set Page_0 [ ipgui::add_page $IPINST -name "Page 0" -display_name {Page 0}]
set_property tooltip {Page 0} ${Page_0}
set C_M00_AXI_TARGET_SLAVE_BASE_ADDR [ ipgui::add_param $IPINST -name "C_M00_AXI_TARGET_SLAVE_BASE_ADDR" -parent ${Page_0} -display_name {C M00 AXI TARGET SLAVE BASE ADDR}]
set_property tooltip {Base address of targeted slave} ${C_M00_AXI_TARGET_SLAVE_BASE_ADDR}
set C_M00_AXI_BURST_LEN [ ipgui::add_param $IPINST -name "C_M00_AXI_BURST_LEN" -parent ${Page_0} -display_name {C M00 AXI BURST LEN} -widget comboBox]
set_property tooltip {Burst Length. Supports 1, 2, 4, 8, 16, 32, 64, 128, 256 burst lengths} ${C_M00_AXI_BURST_LEN}
set C_M00_AXI_ID_WIDTH [ ipgui::add_param $IPINST -name "C_M00_AXI_ID_WIDTH" -parent ${Page_0} -display_name {C M00 AXI ID WIDTH}]
set_property tooltip {Thread ID Width} ${C_M00_AXI_ID_WIDTH}
set C_M00_AXI_ADDR_WIDTH [ ipgui::add_param $IPINST -name "C_M00_AXI_ADDR_WIDTH" -parent ${Page_0} -display_name {C M00 AXI ADDR WIDTH}]
set_property tooltip {Width of Address Bus} ${C_M00_AXI_ADDR_WIDTH}
set C_M00_AXI_DATA_WIDTH [ ipgui::add_param $IPINST -name "C_M00_AXI_DATA_WIDTH" -parent ${Page_0} -display_name {C M00 AXI DATA WIDTH}]
set_property tooltip {Width of Data Bus} ${C_M00_AXI_DATA_WIDTH}
set C_M00_AXI_AWUSER_WIDTH [ ipgui::add_param $IPINST -name "C_M00_AXI_AWUSER_WIDTH" -parent ${Page_0} -display_name {C M00 AXI AWUSER WIDTH}]
set_property tooltip {Width of User Write Address Bus} ${C_M00_AXI_AWUSER_WIDTH}
set C_M00_AXI_ARUSER_WIDTH [ ipgui::add_param $IPINST -name "C_M00_AXI_ARUSER_WIDTH" -parent ${Page_0} -display_name {C M00 AXI ARUSER WIDTH}]
set_property tooltip {Width of User Read Address Bus} ${C_M00_AXI_ARUSER_WIDTH}
set C_M00_AXI_WUSER_WIDTH [ ipgui::add_param $IPINST -name "C_M00_AXI_WUSER_WIDTH" -parent ${Page_0} -display_name {C M00 AXI WUSER WIDTH}]
set_property tooltip {Width of User Write Data Bus} ${C_M00_AXI_WUSER_WIDTH}
set C_M00_AXI_RUSER_WIDTH [ ipgui::add_param $IPINST -name "C_M00_AXI_RUSER_WIDTH" -parent ${Page_0} -display_name {C M00 AXI RUSER WIDTH}]
set_property tooltip {Width of User Read Data Bus} ${C_M00_AXI_RUSER_WIDTH}
set C_M00_AXI_BUSER_WIDTH [ ipgui::add_param $IPINST -name "C_M00_AXI_BUSER_WIDTH" -parent ${Page_0} -display_name {C M00 AXI BUSER WIDTH}]
set_property tooltip {Width of User Response Bus} ${C_M00_AXI_BUSER_WIDTH}
}
proc update_PARAM_VALUE.C_M00_AXI_TARGET_SLAVE_BASE_ADDR { PARAM_VALUE.C_M00_AXI_TARGET_SLAVE_BASE_ADDR } {
# Procedure called to update C_M00_AXI_TARGET_SLAVE_BASE_ADDR when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_M00_AXI_TARGET_SLAVE_BASE_ADDR { PARAM_VALUE.C_M00_AXI_TARGET_SLAVE_BASE_ADDR } {
# Procedure called to validate C_M00_AXI_TARGET_SLAVE_BASE_ADDR
return true
}
proc update_PARAM_VALUE.C_M00_AXI_BURST_LEN { PARAM_VALUE.C_M00_AXI_BURST_LEN } {
# Procedure called to update C_M00_AXI_BURST_LEN when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_M00_AXI_BURST_LEN { PARAM_VALUE.C_M00_AXI_BURST_LEN } {
# Procedure called to validate C_M00_AXI_BURST_LEN
return true
}
proc update_PARAM_VALUE.C_M00_AXI_ID_WIDTH { PARAM_VALUE.C_M00_AXI_ID_WIDTH } {
# Procedure called to update C_M00_AXI_ID_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_M00_AXI_ID_WIDTH { PARAM_VALUE.C_M00_AXI_ID_WIDTH } {
# Procedure called to validate C_M00_AXI_ID_WIDTH
return true
}
proc update_PARAM_VALUE.C_M00_AXI_ADDR_WIDTH { PARAM_VALUE.C_M00_AXI_ADDR_WIDTH } {
# Procedure called to update C_M00_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_M00_AXI_ADDR_WIDTH { PARAM_VALUE.C_M00_AXI_ADDR_WIDTH } {
# Procedure called to validate C_M00_AXI_ADDR_WIDTH
return true
}
proc update_PARAM_VALUE.C_M00_AXI_DATA_WIDTH { PARAM_VALUE.C_M00_AXI_DATA_WIDTH } {
# Procedure called to update C_M00_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_M00_AXI_DATA_WIDTH { PARAM_VALUE.C_M00_AXI_DATA_WIDTH } {
# Procedure called to validate C_M00_AXI_DATA_WIDTH
return true
}
proc update_PARAM_VALUE.C_M00_AXI_AWUSER_WIDTH { PARAM_VALUE.C_M00_AXI_AWUSER_WIDTH } {
# Procedure called to update C_M00_AXI_AWUSER_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_M00_AXI_AWUSER_WIDTH { PARAM_VALUE.C_M00_AXI_AWUSER_WIDTH } {
# Procedure called to validate C_M00_AXI_AWUSER_WIDTH
return true
}
proc update_PARAM_VALUE.C_M00_AXI_ARUSER_WIDTH { PARAM_VALUE.C_M00_AXI_ARUSER_WIDTH } {
# Procedure called to update C_M00_AXI_ARUSER_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_M00_AXI_ARUSER_WIDTH { PARAM_VALUE.C_M00_AXI_ARUSER_WIDTH } {
# Procedure called to validate C_M00_AXI_ARUSER_WIDTH
return true
}
proc update_PARAM_VALUE.C_M00_AXI_WUSER_WIDTH { PARAM_VALUE.C_M00_AXI_WUSER_WIDTH } {
# Procedure called to update C_M00_AXI_WUSER_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_M00_AXI_WUSER_WIDTH { PARAM_VALUE.C_M00_AXI_WUSER_WIDTH } {
# Procedure called to validate C_M00_AXI_WUSER_WIDTH
return true
}
proc update_PARAM_VALUE.C_M00_AXI_RUSER_WIDTH { PARAM_VALUE.C_M00_AXI_RUSER_WIDTH } {
# Procedure called to update C_M00_AXI_RUSER_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_M00_AXI_RUSER_WIDTH { PARAM_VALUE.C_M00_AXI_RUSER_WIDTH } {
# Procedure called to validate C_M00_AXI_RUSER_WIDTH
return true
}
proc update_PARAM_VALUE.C_M00_AXI_BUSER_WIDTH { PARAM_VALUE.C_M00_AXI_BUSER_WIDTH } {
# Procedure called to update C_M00_AXI_BUSER_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_M00_AXI_BUSER_WIDTH { PARAM_VALUE.C_M00_AXI_BUSER_WIDTH } {
# Procedure called to validate C_M00_AXI_BUSER_WIDTH
return true
}
proc update_MODELPARAM_VALUE.C_M00_AXI_TARGET_SLAVE_BASE_ADDR { MODELPARAM_VALUE.C_M00_AXI_TARGET_SLAVE_BASE_ADDR PARAM_VALUE.C_M00_AXI_TARGET_SLAVE_BASE_ADDR } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_TARGET_SLAVE_BASE_ADDR}] ${MODELPARAM_VALUE.C_M00_AXI_TARGET_SLAVE_BASE_ADDR}
}
proc update_MODELPARAM_VALUE.C_M00_AXI_BURST_LEN { MODELPARAM_VALUE.C_M00_AXI_BURST_LEN PARAM_VALUE.C_M00_AXI_BURST_LEN } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_BURST_LEN}] ${MODELPARAM_VALUE.C_M00_AXI_BURST_LEN}
}
proc update_MODELPARAM_VALUE.C_M00_AXI_ID_WIDTH { MODELPARAM_VALUE.C_M00_AXI_ID_WIDTH PARAM_VALUE.C_M00_AXI_ID_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_ID_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXI_ID_WIDTH}
}
proc update_MODELPARAM_VALUE.C_M00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_M00_AXI_ADDR_WIDTH PARAM_VALUE.C_M00_AXI_ADDR_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXI_ADDR_WIDTH}
}
proc update_MODELPARAM_VALUE.C_M00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_M00_AXI_DATA_WIDTH PARAM_VALUE.C_M00_AXI_DATA_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXI_DATA_WIDTH}
}
proc update_MODELPARAM_VALUE.C_M00_AXI_AWUSER_WIDTH { MODELPARAM_VALUE.C_M00_AXI_AWUSER_WIDTH PARAM_VALUE.C_M00_AXI_AWUSER_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_AWUSER_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXI_AWUSER_WIDTH}
}
proc update_MODELPARAM_VALUE.C_M00_AXI_ARUSER_WIDTH { MODELPARAM_VALUE.C_M00_AXI_ARUSER_WIDTH PARAM_VALUE.C_M00_AXI_ARUSER_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_ARUSER_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXI_ARUSER_WIDTH}
}
proc update_MODELPARAM_VALUE.C_M00_AXI_WUSER_WIDTH { MODELPARAM_VALUE.C_M00_AXI_WUSER_WIDTH PARAM_VALUE.C_M00_AXI_WUSER_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_WUSER_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXI_WUSER_WIDTH}
}
proc update_MODELPARAM_VALUE.C_M00_AXI_RUSER_WIDTH { MODELPARAM_VALUE.C_M00_AXI_RUSER_WIDTH PARAM_VALUE.C_M00_AXI_RUSER_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_RUSER_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXI_RUSER_WIDTH}
}
proc update_MODELPARAM_VALUE.C_M00_AXI_BUSER_WIDTH { MODELPARAM_VALUE.C_M00_AXI_BUSER_WIDTH PARAM_VALUE.C_M00_AXI_BUSER_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_BUSER_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXI_BUSER_WIDTH}
}

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emesh_split/component.xml Normal file
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@ -0,0 +1,786 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>adapteva.com</spirit:vendor>
<spirit:library>Adapteva</spirit:library>
<spirit:name>emesh_split</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>emm0</spirit:name>
<spirit:busType spirit:vendor="adapteva.com" spirit:library="Adapteva" spirit:name="eMesh" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="adapteva.com" spirit:library="Adapteva" spirit:name="eMesh_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>access</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>emm0_access</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>write</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>emm0_write</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>datamode</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>emm0_datamode</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ctrlmode</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>emm0_ctrlmode</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>dstaddr</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>emm0_dstaddr</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>srcaddr</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>emm0_srcaddr</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>emm0_data</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>wr_wait</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>emm0_wr_wait</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>rd_wait</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>emm0_rd_wait</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>emm1</spirit:name>
<spirit:busType spirit:vendor="adapteva.com" spirit:library="Adapteva" spirit:name="eMesh" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="adapteva.com" spirit:library="Adapteva" spirit:name="eMesh_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>access</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>emm1_access</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>write</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>emm1_write</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>datamode</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>emm1_datamode</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ctrlmode</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>emm1_ctrlmode</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>dstaddr</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>emm1_dstaddr</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>srcaddr</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>emm1_srcaddr</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>emm1_data</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>ems</spirit:name>
<spirit:busType spirit:vendor="adapteva.com" spirit:library="Adapteva" spirit:name="eMesh" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="adapteva.com" spirit:library="Adapteva" spirit:name="eMesh_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>access</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ems_access</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>write</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ems_write</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>datamode</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ems_datamode</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ctrlmode</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ems_ctrlmode</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>dstaddr</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ems_dstaddr</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>srcaddr</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ems_srcaddr</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ems_data</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>wr_wait</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ems_wr_wait</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>rd_wait</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ems_rd_wait</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>xilinx_verilogsynthesis</spirit:name>
<spirit:displayName>Verilog Synthesis</spirit:displayName>
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
<spirit:language>verilog</spirit:language>
<spirit:modelName>emesh_split</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_verilogsynthesis_view_fileset</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_verilogbehavioralsimulation</spirit:name>
<spirit:displayName>Verilog Simulation</spirit:displayName>
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
<spirit:language>verilog</spirit:language>
<spirit:modelName>emesh_split</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_verilogbehavioralsimulation_view_fileset</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_xpgui</spirit:name>
<spirit:displayName>UI Layout</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>ems_rd_wait</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long" spirit:resolve="immediate">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>ems_wr_wait</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long" spirit:resolve="immediate">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>emm0_access</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long" spirit:resolve="immediate">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>emm0_write</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long" spirit:resolve="immediate">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>emm0_datamode</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="immediate">1</spirit:left>
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long" spirit:resolve="immediate">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>emm0_ctrlmode</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="immediate">3</spirit:left>
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long" spirit:resolve="dependent" spirit:dependency="ems_ctrlmode">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>emm0_dstaddr</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="immediate">31</spirit:left>
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long" spirit:resolve="dependent" spirit:dependency="ems_dstaddr">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>emm0_srcaddr</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="immediate">31</spirit:left>
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long" spirit:resolve="dependent" spirit:dependency="ems_srcaddr">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>emm0_data</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="immediate">31</spirit:left>
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long" spirit:resolve="dependent" spirit:dependency="ems_data">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>emm1_access</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long" spirit:resolve="dependent" spirit:dependency="ems_access">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>emm1_write</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long" spirit:resolve="dependent" spirit:dependency="ems_write">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>emm1_datamode</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="immediate">1</spirit:left>
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long" spirit:resolve="dependent" spirit:dependency="ems_datamode">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>emm1_ctrlmode</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="immediate">3</spirit:left>
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long" spirit:resolve="dependent" spirit:dependency="ems_ctrlmode">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>emm1_dstaddr</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="immediate">31</spirit:left>
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long" spirit:resolve="dependent" spirit:dependency="ems_dstaddr">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>emm1_srcaddr</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="immediate">31</spirit:left>
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long" spirit:resolve="dependent" spirit:dependency="ems_srcaddr">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>emm1_data</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="immediate">31</spirit:left>
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long" spirit:resolve="dependent" spirit:dependency="ems_data">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>ems_access</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>ems_write</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>ems_datamode</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="immediate">1</spirit:left>
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>ems_ctrlmode</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="immediate">3</spirit:left>
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>ems_dstaddr</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="immediate">31</spirit:left>
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>ems_srcaddr</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="immediate">31</spirit:left>
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>ems_data</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="immediate">31</spirit:left>
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>emm0_rd_wait</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>emm0_wr_wait</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
</spirit:ports>
</spirit:model>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>xilinx_verilogsynthesis_view_fileset</spirit:name>
<spirit:file>
<spirit:name>hdl/emesh_split.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
<spirit:userFileType>CHECKSUM_3e1c3b31</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_verilogbehavioralsimulation_view_fileset</spirit:name>
<spirit:file>
<spirit:name>hdl/emesh_split.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
<spirit:file>
<spirit:name>xgui/emesh_split_v1_0.tcl</spirit:name>
<spirit:fileType>tclSource</spirit:fileType>
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
<spirit:userFileType>CHECKSUM_b3eea7a6</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>eMesh 1:2 Splitter</spirit:description>
<spirit:parameters>
<spirit:parameter>
<spirit:name>Component_Name</spirit:name>
<spirit:displayName>Component Name</spirit:displayName>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">emesh_split_v1_0</spirit:value>
</spirit:parameter>
</spirit:parameters>
<spirit:vendorExtensions>
<xilinx:coreExtensions>
<xilinx:supportedFamilies>
<xilinx:family xilinx:lifeCycle="Pre-Production">zynq</xilinx:family>
</xilinx:supportedFamilies>
<xilinx:taxonomies>
<xilinx:taxonomy>/BaseIP</xilinx:taxonomy>
</xilinx:taxonomies>
<xilinx:displayName>emesh_split_v1_0</xilinx:displayName>
<xilinx:vendorDisplayName>Adapteva, Inc.</xilinx:vendorDisplayName>
<xilinx:vendorURL>http://www.adapteva.com</xilinx:vendorURL>
<xilinx:coreRevision>2</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2014-11-15T08:04:21Z</xilinx:coreCreationDateTime>
<xilinx:tags>
<xilinx:tag xilinx:name="user.org:user:emesh_split:1.0_ARCHIVE_LOCATION">/mnt/windowsC/Adapteva/Parallella/parallella-hwelink/fpga/src/emesh_split/ip</xilinx:tag>
<xilinx:tag xilinx:name="adapteva.com:user:emesh_split:1.0_ARCHIVE_LOCATION">/mnt/windowsC/Adapteva/Parallella/parallella-hwelink/fpga/src/emesh_split/ip</xilinx:tag>
<xilinx:tag xilinx:name="adapteva.com:Adapteva:emesh_split:1.0_ARCHIVE_LOCATION">/mnt/windowsC/Adapteva/Parallella/parallella-hwelink/fpga/src/emesh_split/ip</xilinx:tag>
</xilinx:tags>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2014.3</xilinx:xilinxVersion>
</xilinx:packagingInfo>
</spirit:vendorExtensions>
</spirit:component>

107
emesh_split/hdl/emesh_split.v Normal file
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/*
File: emesh_split.v
This file is part of the Parallella Project.
Copyright (C) 2014 Adapteva, Inc.
Contributed by Fred Huettig <fred@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
/*
########################################################################
EPIPHANY eMesh Splitter
########################################################################
This block takes one eMesh input (104-bit transactions) and
copies it to two outputs. The wait signals are taken only from the
first slave port.
This block will hopefully be removed once I figure out how to get
Vivado to allow multiple slaves on one interface!
*/
module emesh_split (/*AUTOARG*/
// Outputs
ems_rd_wait, ems_wr_wait, emm0_access, emm0_write, emm0_datamode,
emm0_ctrlmode, emm0_dstaddr, emm0_srcaddr, emm0_data, emm1_access,
emm1_write, emm1_datamode, emm1_ctrlmode, emm1_dstaddr,
emm1_srcaddr, emm1_data,
// Inputs
ems_access, ems_write, ems_datamode, ems_ctrlmode, ems_dstaddr,
ems_srcaddr, ems_data, emm0_rd_wait, emm0_wr_wait
);
// Slave port
input ems_access;
input ems_write;
input [1:0] ems_datamode;
input [3:0] ems_ctrlmode;
input [31:0] ems_dstaddr;
input [31:0] ems_srcaddr;
input [31:0] ems_data;
output ems_rd_wait;
output ems_wr_wait;
// Master port #0 (with wait inputs)
output emm0_access;
output emm0_write;
output [1:0] emm0_datamode;
output [3:0] emm0_ctrlmode;
output [31:0] emm0_dstaddr;
output [31:0] emm0_srcaddr;
output [31:0] emm0_data;
input emm0_rd_wait;
input emm0_wr_wait;
// Master port #1 (NO wait inputs)
output emm1_access;
output emm1_write;
output [1:0] emm1_datamode;
output [3:0] emm1_ctrlmode;
output [31:0] emm1_dstaddr;
output [31:0] emm1_srcaddr;
output [31:0] emm1_data;
//############
//# Duplicate all slave->master signals
//############
wire emm0_access = ems_access;
wire emm0_write = ems_write;
wire [1:0] emm0_datamode = ems_datamode;
wire [3:0] emm0_ctrlmode = ems_ctrlmode;
wire [31:0] emm0_dstaddr = ems_dstaddr;
wire [31:0] emm0_srcaddr = ems_srcaddr;
wire [31:0] emm0_data = ems_data;
// Master port #1 (NO wait inputs)
wire emm1_access = ems_access;
wire emm1_write = ems_write;
wire [1:0] emm1_datamode = ems_datamode;
wire [3:0] emm1_ctrlmode = ems_ctrlmode;
wire [31:0] emm1_dstaddr = ems_dstaddr;
wire [31:0] emm1_srcaddr = ems_srcaddr;
wire [31:0] emm1_data = ems_data;
//#############################
//# Wait signal passthroughs, port 0 only
//#############################
wire ems_rd_wait = emm0_rd_wait;
wire ems_wr_wait = emm0_wr_wait;
endmodule // emesh_split

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emesh_split/ip_prj/ip_prj.xpr Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2014.3 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="2" Path="/mnt/windowsC/Adapteva/Parallella/parallella-hwelink/fpga/src/emesh_split/ip_prj/ip_prj.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="5ff4b58eb3be4f0ba0953326bd65a629"/>
<Option Name="Part" Val="xc7z020clg400-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="BoardPart" Val=""/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="IPRepoPath" Val="$PPRDIR/../../../src"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../hdl/emesh_split.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../component.xml">
<FileInfo SFType="IPXACT"/>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="emesh_split"/>
<Option Name="TopRTLFile" Val="$PPRDIR/../hdl/emesh_split.v"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Filter Type="Srcs"/>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="emesh_split"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="QuestaSim/ModelSim Simulator"/>
</Simulator>
<Simulator Name="IES">
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
</Simulator>
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="9">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2014"/>
<Step Id="synth_design"/>
</Strategy>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" State="current" SynthRun="synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
</Run>
</Runs>
</Project>

6
emesh_split/xgui/emesh_split_v1_0.tcl Normal file
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# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
}

467
eproto_rx/component.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>adapteva.com</spirit:vendor>
<spirit:library>Adapteva</spirit:library>
<spirit:name>eproto_rx</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>signal_reset</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>reset</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>POLARITY</spirit:name>
<spirit:value spirit:format="string" spirit:resolve="immediate" spirit:id="BUSIFPARAM_VALUE.SIGNAL_RESET.POLARITY" spirit:choiceRef="choices_0">ACTIVE_HIGH</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>emrx</spirit:name>
<spirit:displayName>emrx</spirit:displayName>
<spirit:description>eMesh RX</spirit:description>
<spirit:busType spirit:vendor="adapteva.com" spirit:library="Adapteva" spirit:name="eMesh" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="adapteva.com" spirit:library="Adapteva" spirit:name="eMesh_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>srcaddr</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>emrx_srcaddr</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>access</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>emrx_access</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>datamode</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>emrx_datamode</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>emrx_data</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>wr_wait</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>emrx_wr_wait</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ctrlmode</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>emrx_ctrlmode</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>dstaddr</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>emrx_dstaddr</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>write</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>emrx_write</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>rd_wait</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>emrx_rd_wait</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>xilinx_verilogsynthesis</spirit:name>
<spirit:displayName>Verilog Synthesis</spirit:displayName>
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
<spirit:language>verilog</spirit:language>
<spirit:modelName>eproto_rx</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_verilogsynthesis_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>5ee440b5</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
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359
eproto_rx/hdl/eproto_rx.v Normal file
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@ -0,0 +1,359 @@
/*
File: eproto_rx.v
This file is part of the Parallella Project.
Copyright (C) 2014 Adapteva, Inc.
Contributed by Fred Huettig <fred@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
/*
########################################################################
EPIPHANY eLink RX Protocol block
########################################################################
This block takes the parallel output of the input deserializers, locates
valid frame transitions, and decodes the bytes into standard eMesh
protocol (104-bit transactions).
*/
module eproto_rx (/*AUTOARG*/
// Outputs
rx_rd_wait, rx_wr_wait, emrx_access, emrx_write, emrx_datamode,
emrx_ctrlmode, emrx_dstaddr, emrx_srcaddr, emrx_data,
// Inputs
reset, rxlclk_p, rxframe_p, rxdata_p, emrx_rd_wait, emrx_wr_wait
);
// System reset input
input reset;
// Parallel interface, 8 eLink bytes at a time
input rxlclk_p; // Parallel clock input from IO block
input [7:0] rxframe_p;
input [63:0] rxdata_p;
output rx_rd_wait; // The wait signals are passed through
output rx_wr_wait; // from the emesh interfaces
// Output to MMU / filter
output emrx_access;
output emrx_write;
output [1:0] emrx_datamode;
output [3:0] emrx_ctrlmode;
output [31:0] emrx_dstaddr;
output [31:0] emrx_srcaddr;
output [31:0] emrx_data;
input emrx_rd_wait;
input emrx_wr_wait;
//#############
//# Configuration bits
//#############
//######################
//# Identify FRAME edges
//######################
reg frame_prev;
reg [2:0] rxalign_in;
reg rxactive_in;
reg [63:0] rxdata_in;
reg [2:0] rxalign_0;
reg rxactive_0;
reg [3:0] ctrlmode_0;
reg [31:0] dstaddr_0;
reg [1:0] datamode_0;
reg write_0;
reg access_0;
reg [31:16] data_0;
reg [2:0] rxalign_1;
reg rxactive_1;
reg [3:0] ctrlmode_1;
reg [31:0] dstaddr_1;
reg [1:0] datamode_1;
reg write_1;
reg access_1;
reg [31:0] data_1;
reg [31:0] srcaddr_1;
reg rxactive_2;
reg [3:0] ctrlmode_2;
reg [31:0] dstaddr_2;
reg [1:0] datamode_2;
reg write_2;
reg access_2;
reg [31:0] data_2;
reg [31:0] srcaddr_2;
// Here we handle any alignment of the frame within an 8-cycle group,
// though in theory frames should only start on rising edges??
always @( posedge rxlclk_p ) begin
frame_prev <= rxframe_p[0] ; // Capture last bit for next group
rxdata_in <= rxdata_p;
if( ~frame_prev & rxframe_p[7] ) begin // All 8 bytes are a new frame
rxalign_in <= 3'd7;
rxactive_in <= 1'b1;
end else if( ~rxframe_p[7] & rxframe_p[6] ) begin
rxalign_in <= 3'd6;
rxactive_in <= 1'b1;
end else if( ~rxframe_p[6] & rxframe_p[5] ) begin
rxalign_in <= 3'd5;
rxactive_in <= 1'b1;
end else if( ~rxframe_p[5] & rxframe_p[4] ) begin
rxalign_in <= 3'd4;
rxactive_in <= 1'b1;
end else if( ~rxframe_p[4] & rxframe_p[3] ) begin
rxalign_in <= 3'd3;
rxactive_in <= 1'b1;
end else if( ~rxframe_p[3] & rxframe_p[2] ) begin
rxalign_in <= 3'd2;
rxactive_in <= 1'b1;
end else if( ~rxframe_p[2] & rxframe_p[1] ) begin
rxalign_in <= 3'd1;
rxactive_in <= 1'b1;
end else if( ~rxframe_p[1] & rxframe_p[0] ) begin
rxalign_in <= 3'd0;
rxactive_in <= 1'b1;
end else begin
rxalign_in <= 3'd0; // No edge
rxactive_in <= 3'd0;
end
end // always @ ( posedge rxlclk_p )
// 1st cycle
always @( posedge rxlclk_p ) begin
rxactive_0 <= rxactive_in;
rxalign_0 <= rxalign_in;
case(rxalign_in)
3'd7: begin
ctrlmode_0 <= rxdata_in[55:52];
dstaddr_0[31:0] <= rxdata_in[51:20];
datamode_0 <= rxdata_in[19:18];
write_0 <= rxdata_in[17];
access_0 <= rxdata_in[16];
data_0[31:16] <= rxdata_in[15:0];
end
3'd6: begin
ctrlmode_0 <= rxdata_in[47:44];
dstaddr_0[31:0] <= rxdata_in[43:12];
datamode_0 <= rxdata_in[11:10];
write_0 <= rxdata_in[9];
access_0 <= rxdata_in[8];
data_0[31:24] <= rxdata_in[7:0];
end
3'd5: begin
ctrlmode_0 <= rxdata_in[39:36];
dstaddr_0[31:0] <= rxdata_in[35:4];
datamode_0 <= rxdata_in[3:2];
write_0 <= rxdata_in[1];
access_0 <= rxdata_in[0];
end
3'd4: begin
ctrlmode_0 <= rxdata_in[31:28];
dstaddr_0[31:4] <= rxdata_in[27:0];
end
3'd3: begin
ctrlmode_0 <= rxdata_in[23:20];
dstaddr_0[31:12] <= rxdata_in[19:0];
end
3'd2: begin
ctrlmode_0 <= rxdata_in[15:12];
dstaddr_0[31:20] <= rxdata_in[11:0];
end
3'd1: begin
ctrlmode_0 <= rxdata_in[7:4];
dstaddr_0[31:28] <= rxdata_in[3:0];
end
// if align == 0 then only the tran byte is present, ignore
endcase // case (rxalign_in)
end // always @ ( posedge rxlclk_p )
// 2nd cycle
always @( posedge rxlclk_p ) begin
rxactive_1 <= rxactive_0;
rxalign_1 <= rxalign_0;
// default pass-throughs
ctrlmode_1 <= ctrlmode_0;
dstaddr_1 <= dstaddr_0;
datamode_1 <= datamode_0;
write_1 <= write_0;
access_1 <= access_0;
data_1[31:16] <= data_0[31:16];
case(rxalign_0)
3'd7: begin
data_1[15:0] <= rxdata_in[63:48];
srcaddr_1 <= rxdata_in[47:16];
end
3'd6: begin
data_1[23:0] <= rxdata_in[63:40];
srcaddr_1 <= rxdata_in[39:8];
end
3'd5: begin
data_1 <= rxdata_in[63:32];
srcaddr_1 <= rxdata_in[31:0];
end
3'd4: begin
dstaddr_1[3:0] <= rxdata_in[63:60];
datamode_1 <= rxdata_in[59:58];
write_1 <= rxdata_in[57];
access_1 <= rxdata_in[56];
data_1 <= rxdata_in[55:24];
srcaddr_1[31:8] <= rxdata_in[23:0];
end
3'd3: begin
dstaddr_1[11:0] <= rxdata_in[63:52];
datamode_1 <= rxdata_in[51:50];
write_1 <= rxdata_in[49];
access_1 <= rxdata_in[48];
data_1 <= rxdata_in[47:16];
srcaddr_1[31:16] <= rxdata_in[15:0];
end
3'd2: begin
dstaddr_1[19:0] <= rxdata_in[63:44];
datamode_1 <= rxdata_in[43:42];
write_1 <= rxdata_in[41];
access_1 <= rxdata_in[40];
data_1 <= rxdata_in[39:8];
srcaddr_1[31:24] <= rxdata_in[7:0];
end
3'd1: begin
dstaddr_1[27:0] <= rxdata_in[63:36];
datamode_1 <= rxdata_in[35:34];
write_1 <= rxdata_in[33];
access_1 <= rxdata_in[32];
data_1 <= rxdata_in[31:0];
end
3'd0: begin
ctrlmode_1 <= rxdata_in[63:60];
dstaddr_1[31:0] <= rxdata_in[59:28];
datamode_1 <= rxdata_in[27:26];
write_1 <= rxdata_in[25];
access_1 <= rxdata_in[24];
data_1[31:8] <= rxdata_in[23:0];
end
endcase
end // always @ ( posedge rxlclk_p )
// 3rd cycle
always @( posedge rxlclk_p ) begin
// default pass-throughs
ctrlmode_2 <= ctrlmode_1;
dstaddr_2 <= dstaddr_1;
datamode_2 <= datamode_1;
write_2 <= write_1;
access_2 <= access_1 & rxactive_1; // avoid random non-frame data
data_2 <= data_1;
srcaddr_2 <= srcaddr_1;
case( rxalign_1 )
// 7-5: Full packet is complete in 2nd cycle
3'd4:
srcaddr_2[7:0] <= rxdata_in[63:56];
3'd3:
srcaddr_2[15:0] <= rxdata_in[63:48];
3'd2:
srcaddr_2[23:0] <= rxdata_in[63:40];
3'd1:
srcaddr_2[31:0] <= rxdata_in[63:32];
3'd0: begin
data_2[7:0] <= rxdata_in[63:56];
srcaddr_2[31:0] <= rxdata_in[55:24];
end
endcase // case ( rxalign_1 )
end // always @ ( posedge rxlclk_p )
/* The spec says reads use the 'data' slot for src address, but apparently
the silicon has not read this spec.
if( write_1 ) begin
srcaddr_2 <= srcaddr_1;
case( rxalign_1 )
// 7-5 Full packet is complete in 2nd cycle
3'd4:
srcaddr_2[7:0] <= rxdata_in[63:56];
3'd3:
srcaddr_2[15:0] <= rxdata_in[63:48];
3'd2:
srcaddr_2[23:0] <= rxdata_in[63:40];
3'd1:
srcaddr_2[31:0] <= rxdata_in[63:32];
3'd0: begin
data_2[7:0] <= rxdata_in[63:56];
srcaddr_2[31:0] <= rxdata_in[55:24];
end
endcase // case ( rxalign_1 )
end else begin // on reads, source addr is in data slot
srcaddr_2 <= data_1;
if( rxalign_1 == )
srcaddr_2[7:0] <= rxdata_in[63:56];
end // else: !if( write_1 )
end // always @ ( posedge rxlclk_p )
*/
// xxx_2 now has one complete transfer
// TODO: Handle burst mode, for now we stop after one xaction
assign emrx_access = access_2;
assign emrx_write = write_2;
assign emrx_datamode = datamode_2;
assign emrx_ctrlmode = ctrlmode_2;
assign emrx_dstaddr = dstaddr_2;
assign emrx_srcaddr = srcaddr_2;
assign emrx_data = data_2;
//################################
//# Wait signal passthrough
//################################
wire rx_rd_wait = emrx_rd_wait;
wire rx_wr_wait = emrx_wr_wait;
endmodule // eproto_rx

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eproto_rx/ip_prj/ip_prj.xpr Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2014.3 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="2" Path="/mnt/windowsC/Adapteva/Parallella/parallella-hwelink/fpga/src/eproto_rx/ip_prj/ip_prj.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="30a0a8e2c2014878b6c623ba59c3c721"/>
<Option Name="Part" Val="xc7z020clg400-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="BoardPart" Val=""/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="IPRepoPath" Val="$PPRDIR/../../../src"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../hdl/eproto_rx.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../component.xml">
<FileInfo SFType="IPXACT"/>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="eproto_rx"/>
<Option Name="TopRTLFile" Val="$PPRDIR/../hdl/eproto_rx.v"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Filter Type="Srcs"/>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="eproto_rx"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="QuestaSim/ModelSim Simulator"/>
</Simulator>
<Simulator Name="IES">
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
</Simulator>
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="9">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2014"/>
<Step Id="synth_design"/>
</Strategy>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" State="current" SynthRun="synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
</Run>
</Runs>
</Project>

12
eproto_rx/xgui/eproto_rx_v1_0.tcl Normal file
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# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
set Component_Name [ ipgui::add_param $IPINST -name "Component_Name" -display_name {Component Name}]
set_property tooltip {Component Name} ${Component_Name}
#Adding Page
set Page_0 [ ipgui::add_page $IPINST -name "Page 0" -display_name {Page 0}]
set_property tooltip {Page 0} ${Page_0}
}

472
eproto_tx/component.xml Normal file
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@ -0,0 +1,472 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>adapteva.com</spirit:vendor>
<spirit:library>Adatpeva</spirit:library>
<spirit:name>eproto_tx</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>signal_reset</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>reset</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>POLARITY</spirit:name>
<spirit:value spirit:format="string" spirit:resolve="immediate" spirit:id="BUSIFPARAM_VALUE.SIGNAL_RESET.POLARITY" spirit:choiceRef="choices_0">ACTIVE_HIGH</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>emtx</spirit:name>
<spirit:busType spirit:vendor="adapteva.com" spirit:library="Adapteva" spirit:name="eMesh" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="adapteva.com" spirit:library="Adapteva" spirit:name="eMesh_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>srcaddr</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>emtx_srcaddr</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>access</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>emtx_access</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>datamode</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>emtx_datamode</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>emtx_data</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>wr_wait</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>emtx_wr_wait</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ctrlmode</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>emtx_ctrlmode</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>dstaddr</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>emtx_dstaddr</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>write</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>emtx_write</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>rd_wait</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>emtx_rd_wait</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:model>
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<spirit:view>
<spirit:name>xilinx_verilogsynthesis</spirit:name>
<spirit:displayName>Verilog Synthesis</spirit:displayName>
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
<spirit:language>verilog</spirit:language>
<spirit:modelName>eproto_tx</spirit:modelName>
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<spirit:name>emtx_access</spirit:name>
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<spirit:left spirit:format="long" spirit:resolve="immediate">31</spirit:left>
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</spirit:port>
<spirit:port>
<spirit:name>emtx_srcaddr</spirit:name>
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<spirit:left spirit:format="long" spirit:resolve="immediate">31</spirit:left>
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
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<spirit:typeName>std_logic</spirit:typeName>
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</spirit:model>
<spirit:choices>
<spirit:choice>
<spirit:name>choices_0</spirit:name>
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
</spirit:choice>
</spirit:choices>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>xilinx_verilogsynthesis_view_fileset</spirit:name>
<spirit:file>
<spirit:name>hdl/eproto_tx.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
<spirit:userFileType>CHECKSUM_df6c71d1</spirit:userFileType>
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<spirit:name>xilinx_verilogbehavioralsimulation_view_fileset</spirit:name>
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<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
<spirit:userFileType>CHECKSUM_e65e5adf</spirit:userFileType>
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</spirit:fileSets>
<spirit:description>eLink TX Protocol Generator</spirit:description>
<spirit:parameters>
<spirit:parameter>
<spirit:name>Component_Name</spirit:name>
<spirit:displayName>Component Name</spirit:displayName>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">eproto_tx_v1_0</spirit:value>
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<xilinx:taxonomy>/BaseIP</xilinx:taxonomy>
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<xilinx:displayName>eproto_tx_v1_0</xilinx:displayName>
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<xilinx:tag xilinx:name="user.org:user:eproto_tx:1.0_ARCHIVE_LOCATION">/mnt/windowsC/Adapteva/Parallella/parallella-hwelink/fpga/src/eproto_tx/ip</xilinx:tag>
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<xilinx:tag xilinx:name="adapteva.com:Adatpeva:eproto_tx:1.0_ARCHIVE_LOCATION">/mnt/windowsC/Adapteva/Parallella/parallella-hwelink/fpga/src/eproto_tx/ip</xilinx:tag>
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<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="b31d678a"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="88ac7c75"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="d0bdb522"/>
</xilinx:packagingInfo>
</spirit:vendorExtensions>
</spirit:component>

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eproto_tx/hdl/eproto_tx.v Normal file
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/*
File: eproto_tx.v
This file is part of the Parallella Project.
Copyright (C) 2014 Adapteva, Inc.
Contributed by Fred Huettig <fred@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
/*
########################################################################
EPIPHANY eLink TX Protocol block
########################################################################
This block takes standard eMesh protocol (104-bit transactions) and
encodes the bytes into 8-byte parallel outputs for the output
serializers.
*/
module eproto_tx (/*AUTOARG*/
// Outputs
emtx_rd_wait, emtx_wr_wait, emtx_ack, txframe_p, txdata_p,
// Inputs
reset, emtx_access, emtx_write, emtx_datamode, emtx_ctrlmode,
emtx_dstaddr, emtx_srcaddr, emtx_data, txlclk_p, tx_rd_wait,
tx_wr_wait
);
// System reset input
input reset;
// Input from TX Arbiter
input emtx_access;
input emtx_write;
input [1:0] emtx_datamode;
input [3:0] emtx_ctrlmode;
input [31:0] emtx_dstaddr;
input [31:0] emtx_srcaddr;
input [31:0] emtx_data;
output emtx_rd_wait;
output emtx_wr_wait;
output emtx_ack;
// Parallel interface, 8 eLink bytes at a time
input txlclk_p; // Parallel-rate clock from eClock block
output [7:0] txframe_p;
output [63:0] txdata_p;
input tx_rd_wait; // The wait signals are passed through
input tx_wr_wait; // to the emesh interfaces
//#############
//# Configuration bits
//#############
//############
//# Local regs & wires
//############
reg emtx_ack; // Acknowledge transaction
reg [7:0] txframe_p;
reg [63:0] txdata_p;
//############
//# Logic
//############
// TODO: Bursts
always @( posedge txlclk_p or reset ) begin
if( reset ) begin
emtx_ack <= 1'b0;
txframe_p <= 'd0;
txdata_p <= 'd0;
end else begin
if( emtx_access & ~emtx_ack ) begin
emtx_ack <= 1'b1;
txframe_p <= 8'h3F;
txdata_p <=
{ 8'd0, // Not used
8'd0,
~emtx_write, 7'd0, // B0- TODO: For bursts, add the inc bit
emtx_ctrlmode, emtx_dstaddr[31:28], // B1
emtx_dstaddr[27:4], // B2, B3, B4
emtx_dstaddr[3:0], emtx_datamode, emtx_write, emtx_access // B5
};
end else if( emtx_ack ) begin // if ( emtx_access & ~emtx_ack )
emtx_ack <= 1'b0;
txframe_p <= 8'hFF;
txdata_p <= { emtx_data, emtx_srcaddr };
end else begin
emtx_ack <= 1'b0;
txframe_p <= 8'h00;
txdata_p <= 64'd0;
end
end // else: !if( reset )
end // always @ ( posedge txlclk_p or reset )
//#############################
//# Wait signals
//#############################
reg rd_wait_sync;
reg wr_wait_sync;
reg emtx_rd_wait;
reg emtx_wr_wait;
always @( posedge txlclk_p ) begin
rd_wait_sync <= tx_rd_wait;
emtx_rd_wait <= rd_wait_sync;
wr_wait_sync <= tx_wr_wait;
emtx_wr_wait <= wr_wait_sync;
end
endmodule // eproto_tx

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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2014.3 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="2" Path="/mnt/windowsC/Adapteva/Parallella/parallella-hwelink/fpga/src/eproto_tx/ip_prj/ip_prj.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="71ee907bb36e4a1b8ddc59a6ec07bfcb"/>
<Option Name="Part" Val="xc7z020clg400-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="BoardPart" Val=""/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="IPRepoPath" Val="$PPRDIR/../../../src"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../hdl/eproto_tx.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../component.xml">
<FileInfo SFType="IPXACT"/>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="eproto_tx"/>
<Option Name="TopRTLFile" Val="$PPRDIR/../hdl/eproto_tx.v"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="eproto_tx"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="QuestaSim/ModelSim Simulator"/>
</Simulator>
<Simulator Name="IES">
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
</Simulator>
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="9">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2014">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" State="current" SynthRun="synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014">
<Desc>Vivado Implementation Defaults</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
</Run>
</Runs>
</Project>

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eproto_tx/xgui/eproto_tx_v1_0.tcl Normal file
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# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
set Component_Name [ ipgui::add_param $IPINST -name "Component_Name" -display_name {Component Name}]
set_property tooltip {Component Name} ${Component_Name}
#Adding Page
set Page_0 [ ipgui::add_page $IPINST -name "Page 0" -display_name {Page 0}]
set_property tooltip {Page 0} ${Page_0}
}

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proc init { cellpath otherInfo } {
set cell_handle [get_bd_cells $cellpath]
set all_busif [get_bd_intf_pins $cellpath/*]
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
set full_sbusif_list [list S00_AXI ]
foreach busif $all_busif {
if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } {
set busif_param_list [list]
set busif_name [get_property NAME $busif]
if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } {
continue
}
foreach tparam $axi_standard_param_list {
lappend busif_param_list "C_${busif_name}_${tparam}"
}
bd::mark_propagate_only $cell_handle $busif_param_list
}
}
}
proc pre_propagate {cellpath otherInfo } {
set cell_handle [get_bd_cells $cellpath]
set all_busif [get_bd_intf_pins $cellpath/*]
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
foreach busif $all_busif {
if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
continue
}
if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } {
continue
}
set busif_name [get_property NAME $busif]
foreach tparam $axi_standard_param_list {
set busif_param_name "C_${busif_name}_${tparam}"
set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
if { $val_on_cell != "" } {
set_property CONFIG.${tparam} $val_on_cell $busif
}
}
}
}
}
proc propagate {cellpath otherInfo } {
set cell_handle [get_bd_cells $cellpath]
set all_busif [get_bd_intf_pins $cellpath/*]
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
foreach busif $all_busif {
if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
continue
}
if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } {
continue
}
set busif_name [get_property NAME $busif]
foreach tparam $axi_standard_param_list {
set busif_param_name "C_${busif_name}_${tparam}"
set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
#override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values..
if { $val_on_cell_intf_pin != "" } {
set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle
}
}
}
}
}

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10
esaxi/drivers/esaxi_v1_0/data/esaxi.mdd Normal file
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OPTION psf_version = 2.1;
BEGIN DRIVER esaxi
OPTION supported_peripherals = (esaxi);
OPTION copyfiles = all;
OPTION VERSION = 1.0;
OPTION NAME = esaxi;
END DRIVER

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esaxi/drivers/esaxi_v1_0/data/esaxi.tcl Normal file
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proc generate {drv_handle} {
xdefine_include_file $drv_handle "xparameters.h" "esaxi" "NUM_INSTANCES" "DEVICE_ID" "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR"
}

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esaxi/drivers/esaxi_v1_0/src/Makefile Normal file
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COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
INCLUDEFILES=*.h
LIBSOURCES=*.c
OUTS = *.o
libs:
echo "Compiling esaxi..."
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
make clean
include:
${CP} $(INCLUDEFILES) $(INCLUDEDIR)
clean:
rm -rf ${OUTS}

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esaxi/drivers/esaxi_v1_0/src/esaxi.c Normal file
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/***************************** Include Files *******************************/
#include "esaxi.h"
/************************** Function Definitions ***************************/

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esaxi/drivers/esaxi_v1_0/src/esaxi.h Normal file
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#ifndef ESAXI_H
#define ESAXI_H
/****************** Include Files ********************/
#include "xil_types.h"
#include "xstatus.h"
/**************************** Type Definitions *****************************/
/**
*
* Write/Read 32 bit value to/from ESAXI user logic memory (BRAM).
*
* @param Address is the memory address of the ESAXI device.
* @param Data is the value written to user logic memory.
*
* @return The data from the user logic memory.
*
* @note
* C-style signature:
* void ESAXI_mWriteMemory(u32 Address, u32 Data)
* u32 ESAXI_mReadMemory(u32 Address)
*
*/
#define ESAXI_mWriteMemory(Address, Data) \
Xil_Out32(Address, (u32)(Data))
#define ESAXI_mReadMemory(Address) \
Xil_In32(Address)
/************************** Function Prototypes ****************************/
/**
*
* Run a self-test on the driver/device. Note this may be a destructive test if
* resets of the device are performed.
*
* If the hardware system is not built correctly, this function may never
* return to the caller.
*
* @param baseaddr_p is the base address of the ESAXIinstance to be worked on.
*
* @return
*
* - XST_SUCCESS if all self-test code passed
* - XST_FAILURE if any self-test code failed
*
* @note Caching must be turned off for this function to work.
* @note Self test may fail if data memory and device are not on the same bus.
*
*/
XStatus ESAXI_Mem_SelfTest(void * baseaddr_p);
#endif // ESAXI_H

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esaxi/drivers/esaxi_v1_0/src/esaxi_selftest.c Normal file
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/***************************** Include Files *******************************/
#include "esaxi.h"
#include "xparameters.h"
#include "stdio.h"
#include "xil_io.h"
/************************** Constant Definitions ***************************/
#define READ_WRITE_MUL_FACTOR 0x10
/************************** Function Definitions ***************************/
/**
*
* Run a self-test on the driver/device. Note this may be a destructive test if
* resets of the device are performed.
*
* If the hardware system is not built correctly, this function may never
* return to the caller.
*
* @param baseaddr_p is the base address of the ESAXIinstance to be worked on.
*
* @return
*
* - XST_SUCCESS if all self-test code passed
* - XST_FAILURE if any self-test code failed
*
* @note Caching must be turned off for this function to work.
* @note Self test may fail if data memory and device are not on the same bus.
*
*/
XStatus ESAXI_Mem_SelfTest(void * baseaddr_p)
{
int Index;
u32 baseaddr;
u32 Mem32Value;
baseaddr = (u32) baseaddr_p;
xil_printf("******************************\n\r");
xil_printf("* User Peripheral Self Test\n\r");
xil_printf("******************************\n\n\r");
/*
* Write data to user logic BRAMs and read back
*/
xil_printf("User logic memory test...\n\r");
xil_printf(" - local memory address is 0x%08x\n\r", baseaddr);
xil_printf(" - write pattern to local BRAM and read back\n\r");
for ( Index = 0; Index < 16; Index++ )
{
ESAXI_mWriteMemory(baseaddr+4*Index, (0xDEADBEEF % Index));
}
for ( Index = 0; Index < 16; Index++ )
{
Mem32Value = ESAXI_mReadMemory(baseaddr+4*Index);
if ( Mem32Value != (0xDEADBEEF % Index) )
{
xil_printf(" - write/read memory failed on address 0x%08x\n\r", baseaddr+4*Index);
return XST_FAILURE;
}
}
xil_printf(" - write/read memory passed\n\n\r");
return XST_SUCCESS;
}

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esaxi/example_designs/bfm_design/design.tcl Normal file
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proc create_ipi_design { offsetfile design_name } {
create_bd_design $design_name
open_bd_design $design_name
# Create Clock and Reset Ports
set ACLK [ create_bd_port -dir I -type clk ACLK ]
set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.PHASE {0.000} CONFIG.CLK_DOMAIN "${design_name}_ACLK" ] $ACLK
set ARESETN [ create_bd_port -dir I -type rst ARESETN ]
set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW} ] $ARESETN
set_property CONFIG.ASSOCIATED_RESET ARESETN $ACLK
# Create instance: esaxi_0, and set properties
set esaxi_0 [ create_bd_cell -type ip -vlnv adapteva.com:Adapteva:esaxi:1.0 esaxi_0]
# Create instance: master_0, and set properties
set master_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:cdn_axi_bfm master_0]
# Create interface connections
connect_bd_intf_net [get_bd_intf_pins master_0/M_AXI] [get_bd_intf_pins esaxi_0/S00_AXI]
# Create port connections
connect_bd_net -net aclk_net [get_bd_ports ACLK] [get_bd_pins master_0/M_AXI_ACLK] [get_bd_pins esaxi_0/S00_AXI_ACLK]
connect_bd_net -net aresetn_net [get_bd_ports ARESETN] [get_bd_pins master_0/M_AXI_ARESETN] [get_bd_pins esaxi_0/S00_AXI_ARESETN]
# Auto assign address
assign_bd_address
# Copy all address to interface_address.vh file
set bd_path [file dirname [get_property NAME [get_files ${design_name}.bd]]]
upvar 1 $offsetfile offset_file
set offset_file "${bd_path}/esaxi_v1_0_tb_include.vh"
set fp [open $offset_file "w"]
puts $fp "`ifndef esaxi_v1_0_tb_include_vh_"
puts $fp "`define esaxi_v1_0_tb_include_vh_\n"
puts $fp "//Configuration current bd names"
puts $fp "`define BD_INST_NAME ${design_name}_i"
puts $fp "`define BD_WRAPPER ${design_name}_wrapper\n"
puts $fp "//Configuration address parameters"
set offset [get_property OFFSET [get_bd_addr_segs -of_objects [get_bd_addr_spaces master_0/Data]]]
set offset_hex [string replace $offset 0 1 "32'h"]
puts $fp "`define S00_AXI_SLAVE_ADDRESS ${offset_hex}"
puts $fp "`endif"
close $fp
}
set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores adapteva.com:Adapteva:esaxi:1.0]]]]
set test_bench_file ${ip_path}/example_designs/bfm_design/esaxi_v1_0_tb.v
set interface_address_vh_file ""
# Set IP Repository and Update IP Catalogue
set repo_paths [get_property ip_repo_paths [current_fileset]]
if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } {
set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset]
update_ip_catalog
}
set design_name ""
set all_bd {}
set all_bd_files [get_files *.bd -quiet]
foreach file $all_bd_files {
set file_name [string range $file [expr {[string last "/" $file] + 1}] end]
set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]]
lappend all_bd $bd_name
}
for { set i 1 } { 1 } { incr i } {
set design_name "esaxi_v1_0_bfm_${i}"
if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } {
break
}
}
create_ipi_design interface_address_vh_file ${design_name}
validate_bd_design
set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force]
import_files -force -norecurse $wrapper_file
set_property SOURCE_SET sources_1 [get_filesets sim_1]
import_files -fileset sim_1 -norecurse -force $test_bench_file
remove_files -quiet -fileset sim_1 esaxi_v1_0_tb_include.vh
import_files -fileset sim_1 -norecurse -force $interface_address_vh_file
set_property top esaxi_v1_0_tb [get_filesets sim_1]
set_property top_lib {} [get_filesets sim_1]
set_property top_file {} [get_filesets sim_1]
launch_xsim -simset sim_1 -mode behavioral
restart
run 1000 us

237
esaxi/example_designs/bfm_design/esaxi_v1_0_tb.v Normal file
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`timescale 1 ns / 1 ps
`include "esaxi_v1_0_tb_include.vh"
// Burst Size Defines
`define BURST_SIZE_4_BYTES 3'b010
// Lock Type Defines
`define LOCK_TYPE_NORMAL 1'b0
// lite_response Type Defines
`define RESPONSE_OKAY 2'b00
`define RESPONSE_EXOKAY 2'b01
`define RESP_BUS_WIDTH 2
`define BURST_TYPE_INCR 2'b01
`define BURST_TYPE_WRAP 2'b10
// AMBA S00_AXI AXI4 Range Constants
`define S00_AXI_MAX_BURST_LENGTH 8'b1111_1111
`define S00_AXI_MAX_DATA_SIZE (`S00_AXI_DATA_BUS_WIDTH*(`S00_AXI_MAX_BURST_LENGTH+1))/8
`define S00_AXI_DATA_BUS_WIDTH 32
`define S00_AXI_ADDRESS_BUS_WIDTH 32
`define S00_AXI_RUSER_BUS_WIDTH 1
`define S00_AXI_WUSER_BUS_WIDTH 1
module esaxi_v1_0_tb;
reg tb_ACLK;
reg tb_ARESETn;
// Create an instance of the example tb
`BD_WRAPPER dut (.ACLK(tb_ACLK),
.ARESETN(tb_ARESETn));
// Local Variables
// AMBA S00_AXI AXI4 Local Reg
reg [(`S00_AXI_DATA_BUS_WIDTH*(`S00_AXI_MAX_BURST_LENGTH+1)/16)-1:0] S00_AXI_rd_data;
reg [(`S00_AXI_DATA_BUS_WIDTH*(`S00_AXI_MAX_BURST_LENGTH+1)/16)-1:0] S00_AXI_test_data [2:0];
reg [(`RESP_BUS_WIDTH*(`S00_AXI_MAX_BURST_LENGTH+1))-1:0] S00_AXI_vresponse;
reg [`S00_AXI_ADDRESS_BUS_WIDTH-1:0] S00_AXI_mtestAddress;
reg [(`S00_AXI_RUSER_BUS_WIDTH*(`S00_AXI_MAX_BURST_LENGTH+1))-1:0] S00_AXI_v_ruser;
reg [(`S00_AXI_WUSER_BUS_WIDTH*(`S00_AXI_MAX_BURST_LENGTH+1))-1:0] S00_AXI_v_wuser;
reg [`RESP_BUS_WIDTH-1:0] S00_AXI_response;
integer S00_AXI_mtestID; // Master side testID
integer S00_AXI_mtestBurstLength;
integer S00_AXI_mtestvector; // Master side testvector
integer S00_AXI_mtestdatasize;
integer S00_AXI_mtestCacheType = 0;
integer S00_AXI_mtestProtectionType = 0;
integer S00_AXI_mtestRegion = 0;
integer S00_AXI_mtestQOS = 0;
integer S00_AXI_mtestAWUSER = 0;
integer S00_AXI_mtestARUSER = 0;
integer S00_AXI_mtestBUSER = 0;
integer result_slave_full;
// Simple Reset Generator and test
initial begin
tb_ARESETn = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge tb_ACLK);
tb_ARESETn = 1'b1;
@(posedge tb_ACLK);
end
// Simple Clock Generator
initial tb_ACLK = 1'b0;
always #10 tb_ACLK = !tb_ACLK;
//------------------------------------------------------------------------
// TEST LEVEL API: CHECK_RESPONSE_OKAY
//------------------------------------------------------------------------
// Description:
// CHECK_RESPONSE_OKAY(lite_response)
// This task checks if the return lite_response is equal to OKAY
//------------------------------------------------------------------------
task automatic CHECK_RESPONSE_OKAY;
input [`RESP_BUS_WIDTH-1:0] response;
begin
if (response !== `RESPONSE_OKAY) begin
$display("TESTBENCH ERROR! lite_response is not OKAY",
"\n expected = 0x%h",`RESPONSE_OKAY,
"\n actual = 0x%h",response);
$stop;
end
end
endtask
//------------------------------------------------------------------------
// TEST LEVEL API: COMPARE_DATA
//------------------------------------------------------------------------
// Description:
// COMPARE_DATA(expected,actual)
// This task checks if the actual data is equal to the expected data.
// X is used as don't care but it is not permitted for the full vector
// to be don't care.
//------------------------------------------------------------------------
task automatic COMPARE_DATA;
input expected;
input actual;
begin
if (expected === 'hx || actual === 'hx) begin
$display("TESTBENCH ERROR! COMPARE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
result_slave_full = 0;
$stop;
end
if (actual != expected) begin
$display("TESTBENCH ERROR! Data expected is not equal to actual.",
"\n expected = 0x%h",expected,
"\n actual = 0x%h",actual);
result_slave_full = 0;
$stop;
end
else
begin
$display("TESTBENCH Passed! Data expected is equal to actual.",
"\n expected = 0x%h",expected,
"\n actual = 0x%h",actual);
end
end
endtask
task automatic S00_AXI_TEST;
begin
//---------------------------------------------------------------------
// EXAMPLE TEST 1:
// Simple sequential write and read burst transfers example
// DESCRIPTION:
// The following master code does a simple write and read burst for
// each burst transfer type.
//---------------------------------------------------------------------
$display("---------------------------------------------------------");
$display("EXAMPLE TEST S00_AXI:");
$display("Simple sequential write and read burst transfers example");
$display("---------------------------------------------------------");
S00_AXI_mtestID = 1;
S00_AXI_mtestvector = 0;
S00_AXI_mtestBurstLength = 15;
S00_AXI_mtestAddress = `S00_AXI_SLAVE_ADDRESS;
S00_AXI_mtestCacheType = 0;
S00_AXI_mtestProtectionType = 0;
S00_AXI_mtestdatasize = `S00_AXI_MAX_DATA_SIZE;
S00_AXI_mtestRegion = 0;
S00_AXI_mtestQOS = 0;
S00_AXI_mtestAWUSER = 0;
S00_AXI_mtestARUSER = 0;
result_slave_full = 1;
dut.`BD_INST_NAME.master_0.cdn_axi4_master_bfm_inst.WRITE_BURST_CONCURRENT(S00_AXI_mtestID,
S00_AXI_mtestAddress,
S00_AXI_mtestBurstLength,
`BURST_SIZE_4_BYTES,
`BURST_TYPE_INCR,
`LOCK_TYPE_NORMAL,
S00_AXI_mtestCacheType,
S00_AXI_mtestProtectionType,
S00_AXI_test_data[S00_AXI_mtestvector],
S00_AXI_mtestdatasize,
S00_AXI_mtestRegion,
S00_AXI_mtestQOS,
S00_AXI_mtestAWUSER,
S00_AXI_v_wuser,
S00_AXI_response,
S00_AXI_mtestBUSER);
$display("EXAMPLE TEST 1 : DATA = 0x%h, response = 0x%h",S00_AXI_test_data[S00_AXI_mtestvector],S00_AXI_response);
CHECK_RESPONSE_OKAY(S00_AXI_response);
S00_AXI_mtestID = S00_AXI_mtestID+1;
dut.`BD_INST_NAME.master_0.cdn_axi4_master_bfm_inst.READ_BURST(S00_AXI_mtestID,
S00_AXI_mtestAddress,
S00_AXI_mtestBurstLength,
`BURST_SIZE_4_BYTES,
`BURST_TYPE_WRAP,
`LOCK_TYPE_NORMAL,
S00_AXI_mtestCacheType,
S00_AXI_mtestProtectionType,
S00_AXI_mtestRegion,
S00_AXI_mtestQOS,
S00_AXI_mtestARUSER,
S00_AXI_rd_data,
S00_AXI_vresponse,
S00_AXI_v_ruser);
$display("EXAMPLE TEST 1 : DATA = 0x%h, vresponse = 0x%h",S00_AXI_rd_data,S00_AXI_vresponse);
CHECK_RESPONSE_OKAY(S00_AXI_vresponse);
// Check that the data received by the master is the same as the test
// vector supplied by the slave.
COMPARE_DATA(S00_AXI_test_data[S00_AXI_mtestvector],S00_AXI_rd_data);
$display("EXAMPLE TEST 1 : Sequential write and read FIXED burst transfers complete from the master side.");
$display("---------------------------------------------------------");
$display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!");
if ( result_slave_full ) begin
$display("PTGEN_TEST: PASSED!");
end else begin
$display("PTGEN_TEST: FAILED!");
end
$display("---------------------------------------------------------");
end
endtask
// Create the test vectors
initial begin
// When performing debug enable all levels of INFO messages.
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
dut.`BD_INST_NAME.master_0.cdn_axi4_master_bfm_inst.set_channel_level_info(1);
// Create test data vectors
S00_AXI_test_data[1] = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;
S00_AXI_test_data[0] = 512'h00abcdef111111112222222233333333444444445555555566666666777777778888888899999999AAAAAAAABBBBBBBBCCCCCCCCDDDDDDDDEEEEEEEEFFFFFFFF;
S00_AXI_test_data[2] = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
S00_AXI_v_ruser = 0;
S00_AXI_v_wuser = 0;
end
// Drive the BFM
initial begin
// Wait for end of reset
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
S00_AXI_TEST();
end
endmodule

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proc create_ipi_design { offsetfile design_name } {
create_bd_design $design_name
open_bd_design $design_name
# Create and configure Clock/Reset
create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz sys_clk_0
create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset sys_reset_0
#check if current_board is set, if true - figure out required clocks.
set is_board_clock_found 0
set is_board_reset_found 0
set external_reset_port ""
set external_clock_port ""
if { [current_board_part -quiet] != "" } {
#check if any reset interface exists in board.
set board_reset [lindex [get_board_part_interfaces -filter { BUSDEF_NAME == reset_rtl && MODE == slave }] 0 ]
if { $board_reset ne "" } {
set is_board_reset_found 1
apply_board_connection -board_interface $board_reset -ip_intf sys_clk_0/reset -diagram [current_bd_design]
apply_board_connection -board_interface $board_reset -ip_intf sys_reset_0/ext_reset -diagram [current_bd_design]
set external_rst [get_bd_ports -quiet -of_objects [get_bd_nets -quiet -of_objects [get_bd_pins -quiet sys_clk_0/reset]]]
if { $external_rst ne "" } {
set external_reset_port [get_property NAME $external_rst]
}
} else {
send_msg "ptgen 51-200" WARNING "No reset interface found in current_board, Users may need to specify the location constraints manually."
}
# check for differential clock, exclude any special clocks which has TYPE property.
set board_clock_busifs ""
foreach busif [get_board_part_interfaces -filter "BUSDEF_NAME == diff_clock_rtl"] {
set type [get_property PARAM.TYPE $busif]
if { $type == "" } {
set board_clock_busifs $busif
break
}
}
if { $board_clock_busifs ne "" } {
apply_board_connection -board_interface $board_clock_busifs -ip_intf sys_clk_0/CLK_IN1_D -diagram [current_bd_design]
set is_board_clock_found 1
} else {
# check for single ended clock
set board_sclock_busifs [lindex [get_board_part_interfaces -filter "BUSDEF_NAME == clock_rtl"] 0 ]
if { $board_sclock_busifs ne "" } {
apply_board_connection -board_interface $board_sclock_busifs -ip_intf sys_clk_0/clock_CLK_IN1 -diagram [current_bd_design]
set external_clk [get_bd_ports -quiet -of_objects [get_bd_nets -quiet -of_objects [get_bd_pins -quiet sys_clk_0/clk_in1]]]
if { $external_clk ne "" } {
set external_clock_port [get_property NAME $external_clk]
}
set is_board_clock_found 1
} else {
send_msg "ptgen 51-200" WARNING "No clock interface found in current_board, Users may need to specify the location constraints manually."
}
}
} else {
send_msg "ptgen 51-201" WARNING "No board selected in current_project. Users may need to specify the location constraints manually."
}
#if there is no corresponding board interface found, assume constraints will be provided manually while pin planning.
if { $is_board_reset_found == 0 } {
create_bd_port -dir I -type rst reset_rtl
set_property CONFIG.POLARITY [get_property CONFIG.POLARITY [get_bd_pins sys_clk_0/reset]] [get_bd_ports reset_rtl]
connect_bd_net [get_bd_pins sys_reset_0/ext_reset_in] [get_bd_ports reset_rtl]
connect_bd_net [get_bd_ports reset_rtl] [get_bd_pins sys_clk_0/reset]
set external_reset_port reset_rtl
}
if { $is_board_clock_found == 0 } {
create_bd_port -dir I -type clk clock_rtl
connect_bd_net [get_bd_pins sys_clk_0/clk_in1] [get_bd_ports clock_rtl]
set external_clock_port clock_rtl
}
#Avoid IPI DRC, make clock port synchronous to reset
if { $external_clock_port ne "" && $external_reset_port ne "" } {
set_property CONFIG.ASSOCIATED_RESET $external_reset_port [get_bd_ports $external_clock_port]
}
# Connect other sys_reset pins
connect_bd_net [get_bd_pins sys_reset_0/slowest_sync_clk] [get_bd_pins sys_clk_0/clk_out1]
connect_bd_net [get_bd_pins sys_clk_0/locked] [get_bd_pins sys_reset_0/dcm_locked]
# Create instance: esaxi_0, and set properties
set esaxi_0 [ create_bd_cell -type ip -vlnv adapteva.com:Adapteva:esaxi:1.0 esaxi_0 ]
# Create instance: jtag_axi_0, and set properties
set jtag_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi jtag_axi_0 ]
set_property -dict [list CONFIG.PROTOCOL {0}] [get_bd_cells jtag_axi_0]
connect_bd_net [get_bd_pins jtag_axi_0/aclk] [get_bd_pins sys_clk_0/clk_out1]
connect_bd_net [get_bd_pins jtag_axi_0/aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
# Create instance: axi_peri_interconnect, and set properties
set axi_peri_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_peri_interconnect ]
connect_bd_net [get_bd_pins axi_peri_interconnect/ACLK] [get_bd_pins sys_clk_0/clk_out1]
connect_bd_net [get_bd_pins axi_peri_interconnect/ARESETN] [get_bd_pins sys_reset_0/interconnect_aresetn]
set_property -dict [ list CONFIG.NUM_SI {1} ] $axi_peri_interconnect
connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
connect_bd_intf_net [get_bd_intf_pins jtag_axi_0/M_AXI] [get_bd_intf_pins axi_peri_interconnect/S00_AXI]
set_property -dict [ list CONFIG.NUM_MI {1} ] $axi_peri_interconnect
connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
# Connect all clock & reset of esaxi_0 slave interfaces..
connect_bd_intf_net [get_bd_intf_pins axi_peri_interconnect/M00_AXI] [get_bd_intf_pins esaxi_0/S00_AXI]
connect_bd_net [get_bd_pins esaxi_0/s00_axi_aclk] [get_bd_pins sys_clk_0/clk_out1]
connect_bd_net [get_bd_pins esaxi_0/s00_axi_aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
# Auto assign address
assign_bd_address
# Copy all address to esaxi_v1_0_include.tcl file
set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd
upvar 1 $offsetfile offset_file
set offset_file "${bd_path}/esaxi_v1_0_include.tcl"
set fp [open $offset_file "w"]
puts $fp "# Configuration address parameters"
set offset [get_property OFFSET [get_bd_addr_segs /jtag_axi_0/Data/SEG_esaxi_0_S00_AXI_* ]]
puts $fp "set s00_axi_addr ${offset}"
close $fp
}
# Set IP Repository and Update IP Catalogue
set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores adapteva.com:Adapteva:esaxi:1.0]]]]
set hw_test_file ${ip_path}/example_designs/debug_hw_design/esaxi_v1_0_hw_test.tcl
set repo_paths [get_property ip_repo_paths [current_fileset]]
if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } {
set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset]
update_ip_catalog
}
set design_name ""
set all_bd {}
set all_bd_files [get_files *.bd -quiet]
foreach file $all_bd_files {
set file_name [string range $file [expr {[string last "/" $file] + 1}] end]
set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]]
lappend all_bd $bd_name
}
for { set i 1 } { 1 } { incr i } {
set design_name "esaxi_v1_0_hw_${i}"
if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } {
break
}
}
set intf_address_include_file ""
create_ipi_design intf_address_include_file ${design_name}
save_bd_design
validate_bd_design
set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force]
import_files -force -norecurse $wrapper_file
puts "-------------------------------------------------------------------------------------------------"
puts "INFO NEXT STEPS : Until this stage, debug hardware design has been created, "
puts " please perform following steps to test design in targeted board."
puts "1. Generate bitstream"
puts "2. Setup your targeted board, open hardware manager and open new(or existing) hardware target"
puts "3. Download generated bitstream"
puts "4. Run generated hardware test using below command, this invokes basic read/write operation"
puts " to every interface present in the peripheral : xilinx.com:user:myip:1.0"
puts " : source -notrace ${hw_test_file}"
puts "-------------------------------------------------------------------------------------------------"

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# Runtime Tcl commands to interact with - esaxi_v1_0
# Sourcing design address info tcl
set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd
source ${bd_path}/esaxi_v1_0_include.tcl
# jtag axi master interface hardware name, change as per your design.
set jtag_axi_master hw_axi_1
set ec 0
# hw test script
# Delete all previous axis transactions
if { [llength [get_hw_axi_txns -quiet]] } {
delete_hw_axi_txn [get_hw_axi_txns -quiet]
}
# Test all full slaves.
set wdata_2 04040404030303030202020201010101
# Test: S00_AXI
# Create a burst write transaction at s00_axi_addr address
create_hw_axi_txn w_s00_axi_addr [get_hw_axis $jtag_axi_master] -type write -address $s00_axi_addr -len 4 -data $wdata_2 -burst INCR
# Create a burst read transaction at s00_axi_addr address
create_hw_axi_txn r_s00_axi_addr [get_hw_axis $jtag_axi_master] -type read -address $s00_axi_addr -len 4 -burst INCR
# Initiate transactions
run_hw_axi r_s00_axi_addr
run_hw_axi w_s00_axi_addr
run_hw_axi r_s00_axi_addr
set rdata_tmp [get_property DATA [get_hw_axi_txn r_s00_axi_addr]]
# Compare read data
if { $rdata_tmp == $wdata_2 } {
puts "Data comparison test pass for - S00_AXI"
} else {
puts "Data comparison test fail for - S00_AXI, expected-$wdata_2 actual-$rdata_tmp"
inc ec
}
# Check error flag
if { $ec == 0 } {
puts "PTGEN_TEST: PASSED!"
} else {
puts "PTGEN_TEST: FAILED!"
}

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`timescale 1 ns / 1 ps
module esaxi_v1_0 #
(
// Users to add parameters here
parameter [11:0] C_READ_TAG_ADDR = 12'h810,
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_ID_WIDTH = 1,
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 30,
parameter integer C_S00_AXI_AWUSER_WIDTH = 0,
parameter integer C_S00_AXI_ARUSER_WIDTH = 0,
parameter integer C_S00_AXI_WUSER_WIDTH = 0,
parameter integer C_S00_AXI_RUSER_WIDTH = 0,
parameter integer C_S00_AXI_BUSER_WIDTH = 0
)
(
// Users to add ports here
// FIFO write port, write requests
output wire [102:0] emwr_wr_data,
output wire emwr_wr_en,
input wire emwr_full,
input wire emwr_prog_full,
// FIFO write port, read requests
output wire [102:0] emrq_wr_data,
output wire emrq_wr_en,
input wire emrq_full,
input wire emrq_prog_full,
// FIFO read port, read responses
input wire [102:0] emrr_rd_data,
output wire emrr_rd_en,
input wire emrr_empty,
// Control bits from eConfig
input wire [3:0] ecfg_tx_ctrl_mode,
input wire [11:0] ecfg_coreid,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ID_WIDTH-1 : 0] s00_axi_awid,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [7 : 0] s00_axi_awlen,
input wire [2 : 0] s00_axi_awsize,
input wire [1 : 0] s00_axi_awburst,
input wire s00_axi_awlock,
input wire [3 : 0] s00_axi_awcache,
input wire [2 : 0] s00_axi_awprot,
input wire [3 : 0] s00_axi_awqos,
input wire [3 : 0] s00_axi_awregion,
input wire [C_S00_AXI_AWUSER_WIDTH-1 : 0] s00_axi_awuser,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wlast,
input wire [C_S00_AXI_WUSER_WIDTH-1 : 0] s00_axi_wuser,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [C_S00_AXI_ID_WIDTH-1 : 0] s00_axi_bid,
output wire [1 : 0] s00_axi_bresp,
output wire [C_S00_AXI_BUSER_WIDTH-1 : 0] s00_axi_buser,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ID_WIDTH-1 : 0] s00_axi_arid,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [7 : 0] s00_axi_arlen,
input wire [2 : 0] s00_axi_arsize,
input wire [1 : 0] s00_axi_arburst,
input wire s00_axi_arlock,
input wire [3 : 0] s00_axi_arcache,
input wire [2 : 0] s00_axi_arprot,
input wire [3 : 0] s00_axi_arqos,
input wire [3 : 0] s00_axi_arregion,
input wire [C_S00_AXI_ARUSER_WIDTH-1 : 0] s00_axi_aruser,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_ID_WIDTH-1 : 0] s00_axi_rid,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rlast,
output wire [C_S00_AXI_RUSER_WIDTH-1 : 0] s00_axi_ruser,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
// Instantiation of Axi Bus Interface S00_AXI
esaxi_v1_0_S00_AXI # (
.C_READ_TAG_ADDR(C_READ_TAG_ADDR),
.C_S_AXI_ID_WIDTH(C_S00_AXI_ID_WIDTH),
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH),
.C_S_AXI_AWUSER_WIDTH(C_S00_AXI_AWUSER_WIDTH),
.C_S_AXI_ARUSER_WIDTH(C_S00_AXI_ARUSER_WIDTH),
.C_S_AXI_WUSER_WIDTH(C_S00_AXI_WUSER_WIDTH),
.C_S_AXI_RUSER_WIDTH(C_S00_AXI_RUSER_WIDTH),
.C_S_AXI_BUSER_WIDTH(C_S00_AXI_BUSER_WIDTH)
) esaxi_v1_0_S00_AXI_inst (
.emwr_wr_data (emwr_wr_data),
.emwr_wr_en (emwr_wr_en),
.emwr_full (emwr_full),
.emwr_prog_full (emwr_prog_full),
.emrq_wr_data (emrq_wr_data),
.emrq_wr_en (emrq_wr_en),
.emrq_full (emrq_full),
.emrq_prog_full (emrq_prog_full),
.emrr_rd_data (emrr_rd_data),
.emrr_rd_en (emrr_rd_en),
.emrr_empty (emrr_empty),
.ecfg_tx_ctrl_mode (ecfg_tx_ctrl_mode),
.ecfg_coreid (ecfg_coreid),
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWID(s00_axi_awid),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWLEN(s00_axi_awlen),
.S_AXI_AWSIZE(s00_axi_awsize),
.S_AXI_AWBURST(s00_axi_awburst),
.S_AXI_AWLOCK(s00_axi_awlock),
.S_AXI_AWCACHE(s00_axi_awcache),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWQOS(s00_axi_awqos),
.S_AXI_AWREGION(s00_axi_awregion),
.S_AXI_AWUSER(s00_axi_awuser),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WLAST(s00_axi_wlast),
.S_AXI_WUSER(s00_axi_wuser),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BID(s00_axi_bid),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BUSER(s00_axi_buser),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARID(s00_axi_arid),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARLEN(s00_axi_arlen),
.S_AXI_ARSIZE(s00_axi_arsize),
.S_AXI_ARBURST(s00_axi_arburst),
.S_AXI_ARLOCK(s00_axi_arlock),
.S_AXI_ARCACHE(s00_axi_arcache),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARQOS(s00_axi_arqos),
.S_AXI_ARREGION(s00_axi_arregion),
.S_AXI_ARUSER(s00_axi_aruser),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RID(s00_axi_rid),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RLAST(s00_axi_rlast),
.S_AXI_RUSER(s00_axi_ruser),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready)
);
// Add user logic here
// User logic ends
endmodule

566
esaxi/hdl/esaxi_v1_0_S00_AXI.v Normal file
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@ -0,0 +1,566 @@
`timescale 1 ns / 1 ps
module esaxi_v1_0_S00_AXI #
(
// Users to add parameters here
parameter [11:0] C_READ_TAG_ADDR = 12'h810,
// User parameters ends
// Do not modify the parameters beyond this line
// Width of ID for for write address, write data, read address and read data
parameter integer C_S_AXI_ID_WIDTH = 1,
// Width of S_AXI data bus
parameter integer C_S_AXI_DATA_WIDTH = 32,
// Width of S_AXI address bus
parameter integer C_S_AXI_ADDR_WIDTH = 30,
// Width of optional user defined signal in write address channel
parameter integer C_S_AXI_AWUSER_WIDTH = 0,
// Width of optional user defined signal in read address channel
parameter integer C_S_AXI_ARUSER_WIDTH = 0,
// Width of optional user defined signal in write data channel
parameter integer C_S_AXI_WUSER_WIDTH = 0,
// Width of optional user defined signal in read data channel
parameter integer C_S_AXI_RUSER_WIDTH = 0,
// Width of optional user defined signal in write response channel
parameter integer C_S_AXI_BUSER_WIDTH = 0
)
(
// Users to add ports here
// FIFO write port, write requests
output reg [102:0] emwr_wr_data,
output reg emwr_wr_en,
input wire emwr_full,
input wire emwr_prog_full,
// FIFO write port, read requests
output reg [102:0] emrq_wr_data,
output reg emrq_wr_en,
input wire emrq_full,
input wire emrq_prog_full,
// FIFO read port, read responses
input wire [102:0] emrr_rd_data,
output wire emrr_rd_en,
input wire emrr_empty,
// Control bits from eConfig
input wire [3:0] ecfg_tx_ctrl_mode,
input wire [11:0] ecfg_coreid,
// User ports ends
// Do not modify the ports beyond this line
// Global Clock Signal
input wire S_AXI_ACLK,
// Global Reset Signal. This Signal is Active LOW
input wire S_AXI_ARESETN,
// Write Address ID
input wire [C_S_AXI_ID_WIDTH-1 : 0] S_AXI_AWID,
// Write address
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
// Burst length. The burst length gives the exact number of transfers in a burst
input wire [7 : 0] S_AXI_AWLEN,
// Burst size. This signal indicates the size of each transfer in the burst
input wire [2 : 0] S_AXI_AWSIZE,
// Burst type. The burst type and the size information,
// determine how the address for each transfer within the burst is calculated.
input wire [1 : 0] S_AXI_AWBURST,
// Lock type. Provides additional information about the
// atomic characteristics of the transfer.
input wire S_AXI_AWLOCK,
// Memory type. This signal indicates how transactions
// are required to progress through a system.
input wire [3 : 0] S_AXI_AWCACHE,
// Protection type. This signal indicates the privilege
// and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_AWPROT,
// Quality of Service, QoS identifier sent for each
// write transaction.
input wire [3 : 0] S_AXI_AWQOS,
// Region identifier. Permits a single physical interface
// on a slave to be used for multiple logical interfaces.
input wire [3 : 0] S_AXI_AWREGION,
// Optional User-defined signal in the write address channel.
input wire [C_S_AXI_AWUSER_WIDTH-1 : 0] S_AXI_AWUSER,
// Write address valid. This signal indicates that
// the channel is signaling valid write address and
// control information.
input wire S_AXI_AWVALID,
// Write address ready. This signal indicates that
// the slave is ready to accept an address and associated
// control signals.
output wire S_AXI_AWREADY,
// Write Data
input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
// Write strobes. This signal indicates which byte
// lanes hold valid data. There is one write strobe
// bit for each eight bits of the write data bus.
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
// Write last. This signal indicates the last transfer
// in a write burst.
input wire S_AXI_WLAST,
// Optional User-defined signal in the write data channel.
input wire [C_S_AXI_WUSER_WIDTH-1 : 0] S_AXI_WUSER,
// Write valid. This signal indicates that valid write
// data and strobes are available.
input wire S_AXI_WVALID,
// Write ready. This signal indicates that the slave
// can accept the write data.
output wire S_AXI_WREADY,
// Response ID tag. This signal is the ID tag of the
// write response.
output wire [C_S_AXI_ID_WIDTH-1 : 0] S_AXI_BID,
// Write response. This signal indicates the status
// of the write transaction.
output wire [1 : 0] S_AXI_BRESP,
// Optional User-defined signal in the write response channel.
output wire [C_S_AXI_BUSER_WIDTH-1 : 0] S_AXI_BUSER,
// Write response valid. This signal indicates that the
// channel is signaling a valid write response.
output wire S_AXI_BVALID,
// Response ready. This signal indicates that the master
// can accept a write response.
input wire S_AXI_BREADY,
// Read address ID. This signal is the identification
// tag for the read address group of signals.
input wire [C_S_AXI_ID_WIDTH-1 : 0] S_AXI_ARID,
// Read address. This signal indicates the initial
// address of a read burst transaction.
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
// Burst length. The burst length gives the exact number of transfers in a burst
input wire [7 : 0] S_AXI_ARLEN,
// Burst size. This signal indicates the size of each transfer in the burst
input wire [2 : 0] S_AXI_ARSIZE,
// Burst type. The burst type and the size information,
// determine how the address for each transfer within the burst is calculated.
input wire [1 : 0] S_AXI_ARBURST,
// Lock type. Provides additional information about the
// atomic characteristics of the transfer.
input wire S_AXI_ARLOCK,
// Memory type. This signal indicates how transactions
// are required to progress through a system.
input wire [3 : 0] S_AXI_ARCACHE,
// Protection type. This signal indicates the privilege
// and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_ARPROT,
// Quality of Service, QoS identifier sent for each
// read transaction.
input wire [3 : 0] S_AXI_ARQOS,
// Region identifier. Permits a single physical interface
// on a slave to be used for multiple logical interfaces.
input wire [3 : 0] S_AXI_ARREGION,
// Optional User-defined signal in the read address channel.
input wire [C_S_AXI_ARUSER_WIDTH-1 : 0] S_AXI_ARUSER,
// Write address valid. This signal indicates that
// the channel is signaling valid read address and
// control information.
input wire S_AXI_ARVALID,
// Read address ready. This signal indicates that
// the slave is ready to accept an address and associated
// control signals.
output wire S_AXI_ARREADY,
// Read ID tag. This signal is the identification tag
// for the read data group of signals generated by the slave.
output wire [C_S_AXI_ID_WIDTH-1 : 0] S_AXI_RID,
// Read Data
output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
// Read response. This signal indicates the status of
// the read transfer.
output wire [1 : 0] S_AXI_RRESP,
// Read last. This signal indicates the last transfer
// in a read burst.
output wire S_AXI_RLAST,
// Optional User-defined signal in the read address channel.
output wire [C_S_AXI_RUSER_WIDTH-1 : 0] S_AXI_RUSER,
// Read valid. This signal indicates that the channel
// is signaling the required read data.
output wire S_AXI_RVALID,
// Read ready. This signal indicates that the master can
// accept the read data and response information.
input wire S_AXI_RREADY
);
// AXI4FULL signals
reg [31:0] axi_awaddr; // 32b for Epiphany addr
reg [1:0] axi_awburst;
reg [2:0] axi_awsize;
reg axi_awready;
reg axi_wready;
reg [C_S_AXI_ID_WIDTH-1:0] axi_bid;
reg [1:0] axi_bresp;
reg axi_bvalid;
reg [31:0] axi_araddr; // 32b for Epiphany addr
reg [7:0] axi_arlen;
reg [1:0] axi_arburst;
reg [2:0] axi_arsize;
reg axi_arready;
reg [C_S_AXI_ID_WIDTH-1:0] axi_rid;
reg [C_S_AXI_DATA_WIDTH-1:0] axi_rdata;
reg [1:0] axi_rresp;
reg axi_rlast;
reg axi_rvalid;
//local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
//ADDR_LSB is used for addressing 32/64 bit registers/memories
//ADDR_LSB = 2 for 32 bits (n downto 2)
//ADDR_LSB = 3 for 64 bits (n downto 3)
localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32)+ 1;
// I/O Connections assignments
assign S_AXI_AWREADY = axi_awready;
assign S_AXI_WREADY = axi_wready;
assign S_AXI_BRESP = axi_bresp;
assign S_AXI_BID = axi_bid;
assign S_AXI_BVALID = axi_bvalid;
assign S_AXI_ARREADY = axi_arready;
assign S_AXI_RDATA = axi_rdata;
assign S_AXI_RRESP = axi_rresp;
assign S_AXI_RLAST = axi_rlast;
assign S_AXI_RVALID = axi_rvalid;
assign S_AXI_RID = axi_rid;
assign S_AXI_BUSER = 'd0;
assign S_AXI_BUSER = 'd0;
assign S_AXI_RUSER = 'd0;
// Implement write address channel
reg write_active;
reg b_wait; // Waiting to issue write response (unlikely?)
wire last_wr_beat = axi_wready & S_AXI_WVALID & S_AXI_WLAST;
// axi_awready is asserted when there is no write transfer in progress
always @( posedge S_AXI_ACLK ) begin
if( S_AXI_ARESETN == 1'b0 ) begin
axi_awready <= 1'b0;
write_active <= 1'b0;
end else begin
// We're always ready for an address cycle if we're not doing something else
// NOTE: Might make this faster by going ready on last beat instead of after,
// but if we want the very best each channel should be FIFO'd.
if( ~axi_awready & ~write_active & ~b_wait )
axi_awready <= 1'b1;
else if( S_AXI_AWVALID )
axi_awready <= 1'b0;
// The write cycle is "active" as soon as we capture an address, it
// ends on the last beat.
if( axi_awready & S_AXI_AWVALID )
write_active <= 1'b1;
else if( last_wr_beat )
write_active <= 1'b0;
end // else: !if( S_AXI_ARESETN == 1'b0 )
end // always @ ( posedge S_AXI_ACLK )
// Capture address & other AW info, update address during cycle
always @( posedge S_AXI_ACLK ) begin
if ( S_AXI_ARESETN == 1'b0 ) begin
axi_bid <= 'd0; // capture for write response
axi_awaddr <= 'd0;
axi_awsize <= 3'd0;
axi_awburst <= 2'd0;
end else begin
if( axi_awready & S_AXI_AWVALID ) begin
axi_bid <= S_AXI_AWID;
axi_awaddr <= { ecfg_coreid[11:C_S_AXI_ADDR_WIDTH-20],
S_AXI_AWADDR };
axi_awsize <= S_AXI_AWSIZE; // 0=byte, 1=16b, 2=32b
axi_awburst <= S_AXI_AWBURST; // type, 0=fixed, 1=incr, 2=wrap
end else if( S_AXI_WVALID & axi_wready ) begin
if( axi_awburst == 2'b01 ) begin //incremental burst
// The write address for all the beats in the transaction are increments by the data width.
// NOTE: This should be based on awsize instead to support narrow bursts, I think.
axi_awaddr[31:ADDR_LSB] <= axi_awaddr[31 - 1:ADDR_LSB] + 1;
//awaddr aligned to data width
axi_awaddr[ADDR_LSB-1:0] <= {ADDR_LSB{1'b0}};
end // Both FIXED & WRAPPING types are treated as FIXED, no update.
end // if ( S_AXI_WVALID & axi_wready )
end // else: !if( S_AXI_ARESETN == 1'b0 )
end // always @ ( posedge S_AXI_ACLK )
// Write Channel Implementation
always @( posedge S_AXI_ACLK ) begin
if( S_AXI_ARESETN == 1'b0 ) begin
axi_wready <= 1'b0;
end else begin
if( last_wr_beat )
axi_wready <= 1'b0;
else if( write_active )
axi_wready <= ~emwr_prog_full;
end // else: !if( S_AXI_ARESETN == 1'b0 )
end // always @ ( posedge S_AXI_ACLK )
// Implement write response logic generation
// The write response and response valid signals are asserted by the slave
// at the end of each transaction, burst or single.
always @( posedge S_AXI_ACLK ) begin
if ( S_AXI_ARESETN == 1'b0 ) begin
axi_bvalid <= 1'b0;
axi_bresp <= 2'b0;
b_wait <= 1'b0;
end else begin
if( last_wr_beat ) begin
axi_bvalid <= 1'b1;
axi_bresp <= 2'b0; // 'OKAY' response
b_wait <= ~S_AXI_BREADY; // NOTE: Assumes bready will not drop without valid?
end else if (S_AXI_BREADY & axi_bvalid) begin
axi_bvalid <= 1'b0;
b_wait <= 1'b0;
end
end // else: !if( S_AXI_ARESETN == 1'b0 )
end // always @ ( posedge S_AXI_ACLK )
// Read registers
reg read_active;
reg [31:0] read_addr;
wire last_rd_beat = axi_rvalid & axi_rlast & S_AXI_RREADY;
// Read request channel
always @( posedge S_AXI_ACLK ) begin
if ( S_AXI_ARESETN == 1'b0 ) begin
axi_arready <= 1'b0;
read_active <= 1'b0;
end else begin
if( ~axi_arready & ~read_active )
axi_arready <= 1'b1;
else if( S_AXI_ARVALID )
axi_arready <= 1'b0;
if( axi_arready & S_AXI_ARVALID )
read_active <= 1'b1;
else if( last_rd_beat )
read_active <= 1'b0;
end // else: !if( S_AXI_ARESETN == 1'b0 )
end // always @ ( posedge S_AXI_ACLK )
// Implement axi_araddr, etc. latching & counting
always @( posedge S_AXI_ACLK ) begin
if ( S_AXI_ARESETN == 1'b0 ) begin
axi_araddr <= 0;
axi_arlen <= 8'd0;
axi_arburst <= 2'd0;
axi_arsize <= 2'b0;
axi_rlast <= 1'b0;
axi_rid <= 'd0;
end else begin
if( axi_arready & S_AXI_ARVALID ) begin
axi_araddr <= { ecfg_coreid[11:C_S_AXI_ADDR_WIDTH-20],
S_AXI_ARADDR }; // start address of transfer
axi_arlen <= S_AXI_ARLEN;
axi_arburst <= S_AXI_ARBURST;
axi_arsize <= S_AXI_ARSIZE;
axi_rlast <= ~(|S_AXI_ARLEN);
axi_rid <= S_AXI_ARID;
end else if(axi_rvalid & S_AXI_RREADY) begin
axi_arlen <= axi_arlen - 1;
if(axi_arlen == 8'd1)
axi_rlast <= 1'b1;
if( S_AXI_ARBURST == 2'b01) begin //incremental burst
// The read address for all the beats in the transaction are increments by awsize
// NOTE: This should be based on awsize instead to support narrow bursts, I think.
axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] <= axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1;
//araddr aligned to 4 byte boundary
axi_araddr[ADDR_LSB-1:0] <= {ADDR_LSB{1'b0}};
//for awsize = 4 bytes (010)
end
end // if (axi_rvalid & S_AXI_RREADY)
end // else: !if( S_AXI_ARESETN == 1'b0 )
end // always @ ( posedge S_AXI_ACLK )
// ------------------------------------------
// -- Write Data Handler
// ------------------------------------------
reg [31:0] aligned_data;
reg [31:0] aligned_addr;
reg [1:0] wsize;
reg pre_wr_en; // delay for data alignment
reg [3:0] ctrl_mode; // Sync'd from ecfg
always @( posedge S_AXI_ACLK ) begin
if ( S_AXI_ARESETN == 1'b0 ) begin
aligned_data <= 'd0;
aligned_addr <= 'd0;
wsize <= 2'd0;
emwr_wr_data <= 'd0;
pre_wr_en <= 1'b0;
emwr_wr_en <= 1'b0;
ctrl_mode <= 'd0;
end else begin
ctrl_mode <= ecfg_tx_ctrl_mode; // No timing on this
// Set lsbs of address based on write strobes,
// right-justify data.
aligned_addr[31:2] <= axi_awaddr[31:2];
if( S_AXI_WSTRB[0] ) begin
aligned_data <= S_AXI_WDATA[31:0];
aligned_addr[1:0] <= 2'd0;
end else if(S_AXI_WSTRB[1] ) begin
aligned_data <= {8'd0, S_AXI_WDATA[31:8]};
aligned_addr[1:0] <= 2'd1;
end else if(S_AXI_WSTRB[2] ) begin
aligned_data <= {16'd0, S_AXI_WDATA[31:16]};
aligned_addr[1:0] <= 2'd2;
end else begin
aligned_data <= {24'd0, S_AXI_WDATA[31:24]};
aligned_addr[1:0] <= 2'd3;
end
wsize <= axi_awsize[1:0];
pre_wr_en <= axi_wready & S_AXI_WVALID;
emwr_wr_en <= pre_wr_en;
emwr_wr_data <=
{ 1'b1, // write
wsize, // only up to 32b
ctrl_mode,
aligned_addr, // dstaddr
32'd0, // srcaddr ignored
aligned_data};
end // else: !if( S_AXI_ARESETN == 1'b0 )
end // always @ ( posedge S_AXI_ACLK )
// ------------------------------------------
// -- Read Data Handler
// -- Reads are performed by sending a read
// -- request out the TX port and waiting for
// -- data to come back through the RX port.
// --
// -- Because eLink reads are not generally
// -- returned in order, we will only allow
// -- one at a time. That's OK because reads
// -- are to be avoided for speed anyway.
// ------------------------------------------
// Process to issue eLink read requests
// Since we're only sending one req at a time we can ignore the FIFO flags
reg ractive_reg; // Need leading edge of active for 1st req
reg rnext;
always @( posedge S_AXI_ACLK ) begin
if ( S_AXI_ARESETN == 1'b0 ) begin
emrq_wr_en <= 1'b0;
emrq_wr_data <= 'd0;
ractive_reg <= 1'b0;
rnext <= 1'b0;
end else begin
ractive_reg <= read_active;
rnext <= axi_rvalid & S_AXI_RREADY & ~axi_rlast;
emrq_wr_en <= ( ~ractive_reg & read_active ) | rnext;
emrq_wr_data <=
{ 1'b0, // !write
axi_arsize[1:0], // 32b max
ctrl_mode,
axi_araddr, // dstaddr (read from)
{C_READ_TAG_ADDR, 20'd0}, // srcaddr (tag)
32'd0 // no data
};
end // else: !if( S_AXI_ARESETN == 1'b0 )
end // always @ ( posedge S_AXI_ACLK )
// Handle eLink response data
// always read response data immediately
assign emrr_rd_en = ~emrr_empty;
always @( posedge S_AXI_ACLK ) begin
if ( S_AXI_ARESETN == 1'b0 ) begin
axi_rvalid <= 1'b0;
axi_rdata <= 'd0;
axi_rresp <= 2'd0;
end else begin
if( ~emrr_empty ) begin
axi_rvalid <= 1'b1;
axi_rresp <= 2'd0;
case( axi_araddr[1:0] )
2'b00: axi_rdata <= emrr_rd_data[31:0];
2'b01: axi_rdata <= {emrr_rd_data[23:0], 8'd0};
2'b10: axi_rdata <= {emrr_rd_data[15:0], 16'd0};
default: axi_rdata <= {emrr_rd_data[7:0], 24'd0};
endcase // case ( axi_araddr[1:0] }...
end else if( S_AXI_RREADY ) begin // if ( ~emrr_empty )
axi_rvalid <= 1'b0;
end
end // else: !if( S_AXI_ARESETN == 1'b0 )
end // always @ ( posedge S_AXI_ACLK )
endmodule

95
esaxi/ip_prj/ip_prj.xpr Normal file
View File

@ -0,0 +1,95 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2014.3 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="2" Path="/mnt/windowsC/Adapteva/Parallella/parallella-hwelink/fpga/src/esaxi/ip_prj/ip_prj.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="d0c97841342f4bc0bb30885fb82d8902"/>
<Option Name="Part" Val="xc7z020clg400-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="BoardPart" Val=""/>
<Option Name="SourceMgmtMode" Val="DisplayOnly"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="IPRepoPath" Val="$PPRDIR/../../../src"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../hdl/esaxi_v1_0_S00_AXI.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../hdl/esaxi_v1_0.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../component.xml">
<FileInfo SFType="IPXACT"/>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="esaxi_v1_0"/>
<Option Name="TopRTLFile" Val="$PPRDIR/../hdl/esaxi_v1_0.v"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Filter Type="Srcs"/>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="esaxi_v1_0_S00_AXI"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="QuestaSim/ModelSim Simulator"/>
</Simulator>
<Simulator Name="IES">
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
</Simulator>
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="9">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2014"/>
<Step Id="synth_design"/>
</Strategy>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" State="current" SynthRun="synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
</Run>
</Runs>
</Project>

150
esaxi/xgui/esaxi_v1_0.tcl Normal file
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@ -0,0 +1,150 @@
# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
}
proc update_PARAM_VALUE.C_READ_TAG_ADDR { PARAM_VALUE.C_READ_TAG_ADDR } {
# Procedure called to update C_READ_TAG_ADDR when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_READ_TAG_ADDR { PARAM_VALUE.C_READ_TAG_ADDR } {
# Procedure called to validate C_READ_TAG_ADDR
return true
}
proc update_PARAM_VALUE.C_S00_AXI_ID_WIDTH { PARAM_VALUE.C_S00_AXI_ID_WIDTH } {
# Procedure called to update C_S00_AXI_ID_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S00_AXI_ID_WIDTH { PARAM_VALUE.C_S00_AXI_ID_WIDTH } {
# Procedure called to validate C_S00_AXI_ID_WIDTH
return true
}
proc update_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
# Procedure called to update C_S00_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
# Procedure called to validate C_S00_AXI_DATA_WIDTH
return true
}
proc update_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
# Procedure called to update C_S00_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
# Procedure called to validate C_S00_AXI_ADDR_WIDTH
return true
}
proc update_PARAM_VALUE.C_S00_AXI_AWUSER_WIDTH { PARAM_VALUE.C_S00_AXI_AWUSER_WIDTH } {
# Procedure called to update C_S00_AXI_AWUSER_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S00_AXI_AWUSER_WIDTH { PARAM_VALUE.C_S00_AXI_AWUSER_WIDTH } {
# Procedure called to validate C_S00_AXI_AWUSER_WIDTH
return true
}
proc update_PARAM_VALUE.C_S00_AXI_ARUSER_WIDTH { PARAM_VALUE.C_S00_AXI_ARUSER_WIDTH } {
# Procedure called to update C_S00_AXI_ARUSER_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S00_AXI_ARUSER_WIDTH { PARAM_VALUE.C_S00_AXI_ARUSER_WIDTH } {
# Procedure called to validate C_S00_AXI_ARUSER_WIDTH
return true
}
proc update_PARAM_VALUE.C_S00_AXI_WUSER_WIDTH { PARAM_VALUE.C_S00_AXI_WUSER_WIDTH } {
# Procedure called to update C_S00_AXI_WUSER_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S00_AXI_WUSER_WIDTH { PARAM_VALUE.C_S00_AXI_WUSER_WIDTH } {
# Procedure called to validate C_S00_AXI_WUSER_WIDTH
return true
}
proc update_PARAM_VALUE.C_S00_AXI_RUSER_WIDTH { PARAM_VALUE.C_S00_AXI_RUSER_WIDTH } {
# Procedure called to update C_S00_AXI_RUSER_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S00_AXI_RUSER_WIDTH { PARAM_VALUE.C_S00_AXI_RUSER_WIDTH } {
# Procedure called to validate C_S00_AXI_RUSER_WIDTH
return true
}
proc update_PARAM_VALUE.C_S00_AXI_BUSER_WIDTH { PARAM_VALUE.C_S00_AXI_BUSER_WIDTH } {
# Procedure called to update C_S00_AXI_BUSER_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S00_AXI_BUSER_WIDTH { PARAM_VALUE.C_S00_AXI_BUSER_WIDTH } {
# Procedure called to validate C_S00_AXI_BUSER_WIDTH
return true
}
proc update_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
# Procedure called to update C_S00_AXI_BASEADDR when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
# Procedure called to validate C_S00_AXI_BASEADDR
return true
}
proc update_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
# Procedure called to update C_S00_AXI_HIGHADDR when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
# Procedure called to validate C_S00_AXI_HIGHADDR
return true
}
proc update_MODELPARAM_VALUE.C_S00_AXI_ID_WIDTH { MODELPARAM_VALUE.C_S00_AXI_ID_WIDTH PARAM_VALUE.C_S00_AXI_ID_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_ID_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_ID_WIDTH}
}
proc update_MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH}
}
proc update_MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH}
}
proc update_MODELPARAM_VALUE.C_S00_AXI_AWUSER_WIDTH { MODELPARAM_VALUE.C_S00_AXI_AWUSER_WIDTH PARAM_VALUE.C_S00_AXI_AWUSER_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_AWUSER_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_AWUSER_WIDTH}
}
proc update_MODELPARAM_VALUE.C_S00_AXI_ARUSER_WIDTH { MODELPARAM_VALUE.C_S00_AXI_ARUSER_WIDTH PARAM_VALUE.C_S00_AXI_ARUSER_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_ARUSER_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_ARUSER_WIDTH}
}
proc update_MODELPARAM_VALUE.C_S00_AXI_WUSER_WIDTH { MODELPARAM_VALUE.C_S00_AXI_WUSER_WIDTH PARAM_VALUE.C_S00_AXI_WUSER_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_WUSER_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_WUSER_WIDTH}
}
proc update_MODELPARAM_VALUE.C_S00_AXI_RUSER_WIDTH { MODELPARAM_VALUE.C_S00_AXI_RUSER_WIDTH PARAM_VALUE.C_S00_AXI_RUSER_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_RUSER_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_RUSER_WIDTH}
}
proc update_MODELPARAM_VALUE.C_S00_AXI_BUSER_WIDTH { MODELPARAM_VALUE.C_S00_AXI_BUSER_WIDTH PARAM_VALUE.C_S00_AXI_BUSER_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_BUSER_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_BUSER_WIDTH}
}
proc update_MODELPARAM_VALUE.C_READ_TAG_ADDR { MODELPARAM_VALUE.C_READ_TAG_ADDR PARAM_VALUE.C_READ_TAG_ADDR } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_READ_TAG_ADDR}] ${MODELPARAM_VALUE.C_READ_TAG_ADDR}
}

129
fifos/hdl/fifo.v
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@ -1,129 +0,0 @@
/*
Copyright (C) 2013 Adapteva, Inc.
Contributed by Andreas Olofsson, Roman Trogan <support@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module fifo
(/*AUTOARG*/
// Outputs
rd_data, rd_fifo_empty, wr_fifo_full,
// Inputs
reset, wr_clk, rd_clk, wr_write, wr_data, rd_read
);
parameter DW = 104;
parameter AW = 2;
//##########
//# INPUTS
//##########
input reset;
input wr_clk; //write clock
input rd_clk; //read clock
input wr_write;
input [DW-1:0] wr_data;
input rd_read;
//###########
//# OUTPUTS
//###########
output [DW-1:0] rd_data;
output rd_fifo_empty;
output wr_fifo_full;
/*AUTOINPUT*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [AW-1:0] rd_addr; // From fifo_empty_block of fifo_empty_block.v
wire [AW:0] rd_gray_pointer; // From fifo_empty_block of fifo_empty_block.v
wire [AW:0] rd_wr_gray_pointer; // From sync2rd_wr_gray_pointer of synchronizer.v
wire [AW-1:0] wr_addr; // From fifo_full_block of fifo_full_block.v
wire [AW:0] wr_gray_pointer; // From fifo_full_block of fifo_full_block.v
wire [AW:0] wr_rd_gray_pointer; // From sync2wr_rd_gray_pointer of synchronizer.v
// End of automatics
//Dual Ported Memory
fifo_mem #(.DW(DW),
.AW(AW)) fifo_mem (/*AUTOINST*/
// Outputs
.rd_data (rd_data[DW-1:0]),
// Inputs
.wr_clk (wr_clk),
.wr_write (wr_write),
.wr_data (wr_data[DW-1:0]),
.wr_addr (wr_addr[AW-1:0]),
.rd_addr (rd_addr[AW-1:0]));
//Read State Machine
fifo_empty_block #(.AW(AW)) fifo_empty_block(/*AUTOINST*/
// Outputs
.rd_fifo_empty (rd_fifo_empty),
.rd_addr (rd_addr[AW-1:0]),
.rd_gray_pointer(rd_gray_pointer[AW:0]),
// Inputs
.reset (reset),
.rd_clk (rd_clk),
.rd_wr_gray_pointer(rd_wr_gray_pointer[AW:0]),
.rd_read (rd_read));
//Write State Machine
fifo_full_block #(.AW(AW)) fifo_full_block(/*AUTOINST*/
// Outputs
.wr_fifo_full (wr_fifo_full),
.wr_addr (wr_addr[AW-1:0]),
.wr_gray_pointer (wr_gray_pointer[AW:0]),
// Inputs
.reset (reset),
.wr_clk (wr_clk),
.wr_rd_gray_pointer(wr_rd_gray_pointer[AW:0]),
.wr_write (wr_write));
//Syncrhonizing Gray Pointers between rd/wr domains
/*synchronizer AUTO_TEMPLATE (.clk (@"(substring vl-cell-name 5 7)"_clk),
.reset(reset),
.in (@"(substring vl-cell-name 8)"[AW:0]),
.out (@"(substring vl-cell-name 5)"[AW:0]),
);
*/
synchronizer #(.DW(AW+1)) sync2wr_rd_gray_pointer (/*AUTOINST*/
// Outputs
.out (wr_rd_gray_pointer[AW:0]), // Templated
// Inputs
.in (rd_gray_pointer[AW:0]), // Templated
.clk (wr_clk), // Templated
.reset (reset)); // Templated
synchronizer #(.DW(AW+1)) sync2rd_wr_gray_pointer(/*AUTOINST*/
// Outputs
.out (rd_wr_gray_pointer[AW:0]), // Templated
// Inputs
.in (wr_gray_pointer[AW:0]), // Templated
.clk (rd_clk), // Templated
.reset (reset)); // Templated
endmodule // fifo

94
fifos/hdl/fifo_empty_block.v
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@ -1,94 +0,0 @@
/*
Copyright (C) 2013 Adapteva, Inc.
Contributed by Andreas Olofsson, Roman Trogan <support@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module fifo_empty_block (/*AUTOARG*/
// Outputs
rd_fifo_empty, rd_addr, rd_gray_pointer,
// Inputs
reset, rd_clk, rd_wr_gray_pointer, rd_read
);
parameter AW = 2; // Number of bits to access all the entries
//##########
//# INPUTS
//##########
input reset;
input rd_clk;
input [AW:0] rd_wr_gray_pointer;//from other clock domain
input rd_read;
//###########
//# OUTPUTS
//###########
output rd_fifo_empty;
output [AW-1:0] rd_addr;
output [AW:0] rd_gray_pointer;
//#########
//# REGS
//#########
reg [AW:0] rd_gray_pointer;
reg [AW:0] rd_binary_pointer;
reg rd_fifo_empty;
//##########
//# WIRES
//##########
wire rd_fifo_empty_next;
wire [AW:0] rd_binary_next;
wire [AW:0] rd_gray_next;
//Counter States
always @(posedge rd_clk or posedge reset)
if(reset)
begin
rd_binary_pointer[AW:0] <= {(AW+1){1'b0}};
rd_gray_pointer[AW:0] <= {(AW+1){1'b0}};
end
else if(rd_read)
begin
rd_binary_pointer[AW:0] <= rd_binary_next[AW:0];
rd_gray_pointer[AW:0] <= rd_gray_next[AW:0];
end
//Read Address
assign rd_addr[AW-1:0] = rd_binary_pointer[AW-1:0];
//Updating binary pointer
assign rd_binary_next[AW:0] = rd_binary_pointer[AW:0] +
{{(AW){1'b0}},rd_read};
//Gray Pointer Conversion (for more reliable synchronization)!
assign rd_gray_next[AW:0] = {1'b0,rd_binary_next[AW:1]} ^
rd_binary_next[AW:0];
//# FIFO empty indication
assign rd_fifo_empty_next = (rd_gray_next[AW:0]==rd_wr_gray_pointer[AW:0]);
always @ (posedge rd_clk or posedge reset)
if(reset)
rd_fifo_empty <= 1'b1;
else
rd_fifo_empty <= rd_fifo_empty_next;
endmodule // fifo_empty_block

98
fifos/hdl/fifo_full_block.v
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@ -1,98 +0,0 @@
/*
Copyright (C) 2013 Adapteva, Inc.
Contributed by Andreas Olofsson, Roman Trogan <support@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module fifo_full_block (/*AUTOARG*/
// Outputs
wr_fifo_full, wr_addr, wr_gray_pointer,
// Inputs
reset, wr_clk, wr_rd_gray_pointer, wr_write
);
parameter AW = 2; // Number of bits to access all the entries
//##########
//# INPUTS
//##########
input reset;
input wr_clk;
input [AW:0] wr_rd_gray_pointer;//synced from read domain
input wr_write;
//###########
//# OUTPUTS
//###########
output wr_fifo_full;
output [AW-1:0] wr_addr;
output [AW:0] wr_gray_pointer;//for read domain
//#########
//# REGS
//#########
reg [AW:0] wr_gray_pointer;
reg [AW:0] wr_binary_pointer;
reg wr_fifo_full;
//##########
//# WIRES
//##########
wire wr_fifo_full_next;
wire [AW:0] wr_gray_next;
wire [AW:0] wr_binary_next;
//Counter States
always @(posedge wr_clk or posedge reset)
if(reset)
begin
wr_binary_pointer[AW:0] <= {(AW+1){1'b0}};
wr_gray_pointer[AW:0] <= {(AW+1){1'b0}};
end
else if(wr_write)
begin
wr_binary_pointer[AW:0] <= wr_binary_next[AW:0];
wr_gray_pointer[AW:0] <= wr_gray_next[AW:0];
end
//Write Address
assign wr_addr[AW-1:0] = wr_binary_pointer[AW-1:0];
//Updating binary pointer
assign wr_binary_next[AW:0] = wr_binary_pointer[AW:0] +
{{(AW){1'b0}},wr_write};
//Gray Pointer Conversion (for more reliable synchronization)!
assign wr_gray_next[AW:0] = {1'b0,wr_binary_next[AW:1]} ^
wr_binary_next[AW:0];
//FIFO full indication
assign wr_fifo_full_next =
(wr_gray_next[AW-2:0] == wr_rd_gray_pointer[AW-2:0]) &
(wr_gray_next[AW] ^ wr_rd_gray_pointer[AW]) &
(wr_gray_next[AW-1] ^ wr_rd_gray_pointer[AW-1]);
always @ (posedge wr_clk or posedge reset)
if(reset)
wr_fifo_full <= 1'b0;
else
wr_fifo_full <=wr_fifo_full_next;
endmodule // fifo_full_block

60
fifos/hdl/fifo_mem.v
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@ -1,60 +0,0 @@
/*
Copyright (C) 2013 Adapteva, Inc.
Contributed by Roman Trogan <support@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module fifo_mem (/*AUTOARG*/
// Outputs
rd_data,
// Inputs
wr_clk, wr_write, wr_data, wr_addr, rd_addr
);
parameter DW = 104;
parameter AW = 2;
localparam MD = 1<<AW;
//#########
//# INPUTS
//#########
input wr_clk; //write clock
input wr_write;
input [DW-1:0] wr_data;
input [AW-1:0] wr_addr;
input [AW-1:0] rd_addr;
//##########
//# OUTPUTS
//##########
output [DW-1:0] rd_data;
//########
//# REGS
//########
reg [DW-1:0] mem[MD-1:0];
//Write
always @(posedge wr_clk)
if(wr_write)
mem[wr_addr[AW-1:0]] <= wr_data[DW-1:0];
//Read
assign rd_data[DW-1:0] = mem[rd_addr[AW-1:0]];
endmodule // fifo_mem

12
interfaces/eClockCfg.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>adapteva.com</spirit:vendor>
<spirit:library>Adapteva</spirit:library>
<spirit:name>eClockCfg</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:directConnection>true</spirit:directConnection>
<spirit:isAddressable>false</spirit:isAddressable>
<spirit:maxMasters>1</spirit:maxMasters>
<spirit:maxSlaves>1</spirit:maxSlaves>
<spirit:description>CCLK Configuration Controls</spirit:description>
</spirit:busDefinition>

49
interfaces/eClockCfg_rtl.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>adapteva.com</spirit:vendor>
<spirit:library>Adapteva</spirit:library>
<spirit:name>eClockCfg_rtl</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busType spirit:vendor="adapteva.com" spirit:library="Adapteva" spirit:name="eClockCfg" spirit:version="1.0"/>
<spirit:ports>
<spirit:port>
<spirit:logicalName>div</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>4</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:width>4</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>pllcfg</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>4</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:width>4</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>en</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
</spirit:ports>
</spirit:abstractionDefinition>

12
interfaces/eConfig.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>adapteva.com</spirit:vendor>
<spirit:library>Adapteva</spirit:library>
<spirit:name>eConfig</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:directConnection>false</spirit:directConnection>
<spirit:isAddressable>false</spirit:isAddressable>
<spirit:maxMasters>1</spirit:maxMasters>
<spirit:maxSlaves>3</spirit:maxSlaves>
<spirit:description>Configuration for eLink transceivers</spirit:description>
</spirit:busDefinition>

179
interfaces/eConfig_rtl.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>adapteva.com</spirit:vendor>
<spirit:library>Adapteva</spirit:library>
<spirit:name>eConfig_rtl</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busType spirit:vendor="adapteva.com" spirit:library="Adapteva" spirit:name="eConfig" spirit:version="1.0"/>
<spirit:ports>
<spirit:port>
<spirit:logicalName>sw_reset</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>tx_enable</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>tx_mmu_mode</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>tx_gpio_mode</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>tx_ctrl_mode</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>4</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:width>4</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>tx_clkdiv</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>4</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:width>4</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>rx_enable</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>rx_mmu_mode</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>rx_gpio_mode</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>rx_loopback_mode</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>coreid</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>12</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:width>12</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>datain</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>11</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:width>11</spirit:width>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>dataout</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>11</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:width>11</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
</spirit:ports>
</spirit:abstractionDefinition>

18
interfaces/eLink.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>adapteva.com</spirit:vendor>
<spirit:library>interface</spirit:library>
<spirit:name>eLink</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:directConnection>true</spirit:directConnection>
<spirit:isAddressable>true</spirit:isAddressable>
<spirit:maxMasters>1</spirit:maxMasters>
<spirit:maxSlaves>1</spirit:maxSlaves>
<spirit:description>Epiphany eLink Interface</spirit:description>
<spirit:vendorExtensions>
<xilinx:busDefinitionInfo>
<xilinx:displayName>eLink</xilinx:displayName>
</xilinx:busDefinitionInfo>
<xilinx:busDefinitionInfo><xilinx:displayName>eLink</xilinx:displayName></xilinx:busDefinitionInfo>
</spirit:vendorExtensions>
</spirit:busDefinition>

187
interfaces/eLink_rtl.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>adapteva.com</spirit:vendor>
<spirit:library>interface</spirit:library>
<spirit:name>eLink_rtl</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busType spirit:vendor="adapteva.com" spirit:library="interface" spirit:name="eLink" spirit:version="1.0"/>
<spirit:ports>
<spirit:port>
<spirit:logicalName>data_p</spirit:logicalName>
<spirit:description>Data</spirit:description>
<spirit:wire>
<spirit:qualifier>
<spirit:isData>true</spirit:isData>
</spirit:qualifier>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>8</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>8</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>data_n</spirit:logicalName>
<spirit:description>Data</spirit:description>
<spirit:wire>
<spirit:qualifier>
<spirit:isData>true</spirit:isData>
</spirit:qualifier>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>8</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>8</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
<spirit:defaultValue>255</spirit:defaultValue>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>frame_p</spirit:logicalName>
<spirit:description>Frame</spirit:description>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>frame_n</spirit:logicalName>
<spirit:description>Frame</spirit:description>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
<spirit:defaultValue>1</spirit:defaultValue>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>lclk_p</spirit:logicalName>
<spirit:description>Clock</spirit:description>
<spirit:wire>
<spirit:qualifier>
<spirit:isClock>true</spirit:isClock>
</spirit:qualifier>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>lclk_n</spirit:logicalName>
<spirit:description>Clock</spirit:description>
<spirit:wire>
<spirit:qualifier>
<spirit:isClock>true</spirit:isClock>
</spirit:qualifier>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
<spirit:defaultValue>1</spirit:defaultValue>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>wr_wait_p</spirit:logicalName>
<spirit:description>Write Wait</spirit:description>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onSlave>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>wr_wait_n</spirit:logicalName>
<spirit:description>Write Wait</spirit:description>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onSlave>
<spirit:defaultValue>1</spirit:defaultValue>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>rd_wait_p</spirit:logicalName>
<spirit:description>Read Wait</spirit:description>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onSlave>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>rd_wait_n</spirit:logicalName>
<spirit:description>Read Wait</spirit:description>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onSlave>
<spirit:defaultValue>1</spirit:defaultValue>
</spirit:wire>
</spirit:port>
</spirit:ports>
<spirit:vendorExtensions>
<xilinx:abstractionDefinitionInfo>
<xilinx:displayName>eLink</xilinx:displayName>
</xilinx:abstractionDefinitionInfo>
</spirit:vendorExtensions>
</spirit:abstractionDefinition>

14
interfaces/eMesh.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>adapteva.com</spirit:vendor>
<spirit:library>Adapteva</spirit:library>
<spirit:name>eMesh</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:directConnection>true</spirit:directConnection>
<spirit:isAddressable>false</spirit:isAddressable>
<spirit:maxMasters>1</spirit:maxMasters>
<spirit:maxSlaves>2</spirit:maxSlaves>
<spirit:description>Adapteva eMesh high-performance interface</spirit:description>
<spirit:vendorExtensions> <xilinx:busDefinitionInfo><xilinx:displayName>eMesh</xilinx:displayName></xilinx:busDefinitionInfo>
</spirit:vendorExtensions>
</spirit:busDefinition>

168
interfaces/eMesh_rtl.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>adapteva.com</spirit:vendor>
<spirit:library>Adapteva</spirit:library>
<spirit:name>eMesh_rtl</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busType spirit:vendor="adapteva.com" spirit:library="Adapteva" spirit:name="eMesh" spirit:version="1.0"/>
<spirit:ports>
<spirit:port>
<spirit:logicalName>access</spirit:logicalName>
<spirit:description>valid</spirit:description>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>write</spirit:logicalName>
<spirit:description>write / not read</spirit:description>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>out</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>datamode</spirit:logicalName>
<spirit:description>data mode</spirit:description>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>2</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>2</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>ctrlmode</spirit:logicalName>
<spirit:description>control mode</spirit:description>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>4</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>4</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>dstaddr</spirit:logicalName>
<spirit:description>destination addr</spirit:description>
<spirit:wire>
<spirit:qualifier>
<spirit:isAddress>true</spirit:isAddress>
</spirit:qualifier>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>32</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>32</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>srcaddr</spirit:logicalName>
<spirit:description>source addr / high data</spirit:description>
<spirit:wire>
<spirit:qualifier>
<spirit:isAddress>true</spirit:isAddress>
</spirit:qualifier>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>32</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>32</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>data</spirit:logicalName>
<spirit:description>data</spirit:description>
<spirit:wire>
<spirit:qualifier>
<spirit:isData>true</spirit:isData>
</spirit:qualifier>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>32</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>32</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>wr_wait</spirit:logicalName>
<spirit:description>write pushback</spirit:description>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>optional</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:width>1</spirit:width>
</spirit:onSlave>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>rd_wait</spirit:logicalName>
<spirit:description>read pushback</spirit:description>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>optional</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:width>1</spirit:width>
<spirit:direction>out</spirit:direction>
</spirit:onSlave>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:wire>
</spirit:port>
</spirit:ports>
<spirit:vendorExtensions>
<xilinx:abstractionDefinitionInfo>
<xilinx:displayName>eMesh</xilinx:displayName>
</xilinx:abstractionDefinitionInfo>
</spirit:vendorExtensions>
</spirit:abstractionDefinition>