diff --git a/padring/hdl/oh_padring.v b/padring/hdl/oh_padring.v
index b849082..530b66c 100644
--- a/padring/hdl/oh_padring.v
+++ b/padring/hdl/oh_padring.v
@@ -32,8 +32,9 @@ module oh_padring
     parameter WE_VSS     =  8 
     )
    (
-    //CORE SIGNALS
+    //CONTINUOUS GROUND
     inout 		   vss,
+    
     inout 		   vdd,
     //NORTH
     inout [NO_DOMAINS-1:0] no_vddio,
diff --git a/padring/hdl/oh_pads_power.v b/padring/hdl/oh_pads_power.v
deleted file mode 100644
index f5301ca..0000000
--- a/padring/hdl/oh_pads_power.v
+++ /dev/null
@@ -1,61 +0,0 @@
-//#############################################################################
-//# Function:  Core Power/Ground Pads                                         #
-//# Copyright: OH Project Authors. ALl rights Reserved.                       #
-//# License:   MIT (see LICENSE file in OH repository)                        # 
-//#############################################################################
-
-module oh_pads_power 
-  #(parameter NVDD   =  1,   // Number of vdd pads
-    parameter NVSS   =  1,   // Number of vss pads
-    parameter DIR    = "NO"  // Side: "NO", "SO", "EA", "WE"
-    )
-   (
-    inout vss, // core ground
-    inout vdd, // pre-driver supply
-    inout vddio, // io digital supply
-    inout vssio, // io ground
-    inout poc // power on control signal
-    );
-
-`ifdef CFG_ASIC   
-
-   //#############################
-   //# CORE VDD PADS
-   //#############################
-   genvar  i;   
-   generate
-      for(i=0;i<NVDD;i=i+1)
-	begin : g00
-	   asic_vddpad #(.DIR(DIR))	   
-	   ivdd (.vdd    (vdd),
-		 .vss    (vss),
-		 .vddio  (vddio),
-		 .vssio  (vssio),
-		 .poc    (poc));
-	end      
-   endgenerate
-   
-   //#############################
-   //# CORE ROUND PADS
-   //############################# 
-
-   generate
-      for(i=0;i<NVSS;i=i+1)
-	begin : g10
-	   asic_vsspad #(.DIR(DIR))
-	   ivss (
-		 .vdd    (vdd),
-		 .vss    (vss),
-		 .vddio  (vddio),
-		 .vssio  (vssio),
-		 .poc    (poc));
-	end      
-   endgenerate
-
-`endif
-   
-endmodule // oh_pads_power
-
-// Local Variables:
-// verilog-library-directories:("." "/home/aolofsson/models/verilog") 
-// End: