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Fixing SPI pushback contention bug (typo)

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This commit is contained in:
Andreas Olofsson 2016-03-10 16:57:37 -05:00
parent 383dd50b99
commit 4589062821
2 changed files with 13 additions and 10 deletions
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11
spi/dv/dut_spi.v
View File

@ -5,7 +5,7 @@ module dut(/*AUTOARG*/
clk1, clk2, nreset, vdd, vss, access_in, packet_in, wait_in
);
parameter SREGS = 40;
parameter UREGS = 13;
parameter AW = 32;
parameter DW = 32;
parameter CW = 2;
@ -58,15 +58,16 @@ module dut(/*AUTOARG*/
//###################
assign clkout = clk1;
assign clk = clk1;
assign wait_out = 1'b0;
assign dut_active = 1'b1;
//######################################################################
//# DUT
//######################################################################
//drive through master, observe on slave
spi #(.AW(AW),
.SREGS(SREGS)
.UREGS(UREGS)
)
master (.m_miso (s_miso),
@ -92,7 +93,7 @@ module dut(/*AUTOARG*/
.packet_in (packet_in[PW-1:0]));
spi #(.AW(AW),
.SREGS(SREGS)
.UREGS(UREGS)
)
slave ( .s_sclk (m_sclk),
@ -105,12 +106,12 @@ module dut(/*AUTOARG*/
.m_sclk (),
.m_mosi (),
.m_ss (),
.wait_out (),
/*AUTOINST*/
// Outputs
.spi_irq (spi_irq),
.access_out (access_out),
.packet_out (packet_out[PW-1:0]),
.wait_out (wait_out),
.s_miso (s_miso),
// Inputs
.nreset (nreset),

12
spi/hdl/spi.v
View File

@ -20,7 +20,7 @@ module spi (/*AUTOARG*/
parameter AW = 32; // data width of fifo
parameter PW = 2*AW+40; // packet size
parameter SREGS = 40; // number of slave addresses (min 40)
parameter UREGS = 13; // number of user slave regs
//clk, reset, irq
input nreset; // asynch active low reset
@ -62,7 +62,7 @@ module spi (/*AUTOARG*/
wire m_wait_out; // From spi_master of spi_master.v
wire s_access_out; // From spi_slave of spi_slave.v
wire [PW-1:0] s_packet_out; // From spi_slave of spi_slave.v
wire [SREGS*8-1:0] s_spi_regs; // From spi_slave of spi_slave.v
wire [511:0] s_spi_regs; // From spi_slave of spi_slave.v
wire s_wait_out; // From spi_slave of spi_slave.v
// End of automatics
@ -107,10 +107,10 @@ module spi (/*AUTOARG*/
*/
spi_slave #(.AW(AW),
.SREGS(SREGS))
.UREGS(UREGS))
spi_slave (/*AUTOINST*/
// Outputs
.spi_regs (s_spi_regs[SREGS*8-1:0]), // Templated
.spi_regs (s_spi_regs[511:0]), // Templated
.spi_irq (spi_irq), // Templated
.miso (s_miso), // Templated
.access_out (s_access_out), // Templated
@ -130,10 +130,12 @@ module spi (/*AUTOARG*/
//# EMESH MUX
//###########################################################
assign wait_out = s_wait_out | m_wait_out;
emesh_mux #(.N(2),
.AW(AW))
emesh_mux (// Outputs
.wait_out ({s_wait_out, m_wait_out}),
.wait_out (),
.access_out (access_out),
.packet_out (packet_out[PW-1:0]),
// Inputs