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Changing block name to avoid conflict with "soft" constraints

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aolofsson 2022-06-12 22:48:14 -04:00
parent 5258c5c357
commit 46310f842e
1 changed files with 10 additions and 10 deletions
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20
src/stdlib/hdl/oh_memory_sp.v
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@ -37,24 +37,23 @@ module oh_memory_sp
); );
generate generate
if(SYN == "TRUE") begin: soft
//######################################### if(SYN == "TRUE") begin: rtl
// Generic RAM for synthesis // Generic RTL RAM
//######################################### reg [N-1:0] ram [0:DEPTH-1];
//local variables wire [N-1:0] rdata;
reg [N-1:0] ram [0:DEPTH-1]; integer i;
wire [N-1:0] rdata;
integer i;
//write port //write port
always @(posedge clk) always @(posedge clk)
for (i=0;i<N;i=i+1) for (i=0;i<N;i=i+1)
if (en & wem[i]) if (en & wem[i])
ram[addr[AW-1:0]][i] <= din[i]; ram[addr[AW-1:0]][i] <= din[i];
//read port //read port
assign rdata[N-1:0] = ram[addr[AW-1:0]]; assign rdata[N-1:0] = ram[addr[AW-1:0]];
//Configurable output register //configurable output register
reg [N-1:0] rd_reg; reg [N-1:0] rd_reg;
always @ (posedge clk) always @ (posedge clk)
if(en) if(en)
@ -63,8 +62,9 @@ module oh_memory_sp
//Drive output from register or RAM directly //Drive output from register or RAM directly
assign dout[N-1:0] = (REG==1) ? rd_reg[N-1:0] : rdata[N-1:0]; assign dout[N-1:0] = (REG==1) ? rd_reg[N-1:0] : rdata[N-1:0];
end end // block: rtl
else begin: hard else begin: hard
// Hard macro ASIC RAM
asic_memory_sp #(.N(N), asic_memory_sp #(.N(N),
.DEPTH(DEPTH), .DEPTH(DEPTH),
.SHAPE(SHAPE), .SHAPE(SHAPE),