FPGA/oh
1
0
Fork 0
mirror of https://github.com/aolofsson/oh.git synced 2025-01-17 20:02:53 +08:00
Code Issues Projects Releases Wiki Activity

Fixing wait circuit in dut (randome wait gen was removed from top)

Browse Source
This commit is contained in:
Andreas Olofsson 2015-11-13 16:27:06 -05:00
parent fbcf58d642
commit 4637f90546
1 changed files with 5 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
elink/dv/dut_elink.v
View File

@ -313,16 +313,14 @@ module dut(/*AUTOARG*/
wire emem_wait;
//"Arbitration" between read/write transaction
assign emem_access = ~elink1_rxwr_wait & (elink1_rxwr_access | elink1_rxrd_access);
assign emem_access = elink1_rxwr_access | elink1_rxrd_access;
assign emem_packet[PW-1:0] = elink1_rxwr_access ? elink1_rxwr_packet[PW-1:0]:
elink1_rxrd_packet[PW-1:0];
assign elink1_rxrd_wait = emem_wait |
elink1_rxwr_access |
elink1_rxwr_wait;
assign elink1_rxrd_wait = emem_wait | elink1_rxwr_access;
assign elink1_rxwr_wait = emem_wait;
/*ememory AUTO_TEMPLATE (
// Outputs
.\(.*\)_out (elink1_txrr_\1[]),
@ -335,27 +333,16 @@ module dut(/*AUTOARG*/
.clk (clk),
.wait_out (emem_wait),
.coreid (12'h0),
.access_in (emem_access), // Templated
.access_in (emem_access),
/*AUTOINST*/
// Outputs
.access_out (elink1_txrr_access), // Templated
.packet_out (elink1_txrr_packet[PW-1:0]), // Templated
// Inputs
.nreset (nreset),
.packet_in (emem_packet[PW-1:0])); // Templated
//Write wait circuit
reg [7:0] wait_counter;
always @ (posedge clk or negedge nreset)
if(!nreset)
wait_counter[7:0] <= 'b0;
else
wait_counter[7:0] <= wait_counter+1'b1;
assign elink1_rxwr_wait = (|wait_counter[4:0]);//(|wait_counter[3:0]);//1'b0;
endmodule // dv_elink
// Local Variables:
// verilog-library-directories:("." "../hdl" "../../emesh/dv" "../../emesh/hdl")