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Adding stubs files for xilinx IP

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Goal is to create models for all of these
This commit is contained in:
aolofsson 2014-12-14 22:21:01 -05:00
parent 7b6b281862
commit 47fa7ff23d
14 changed files with 397 additions and 0 deletions
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12
stubs/hdl/BUFG.v Normal file
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module BUFG (/*AUTOARG*/
// Outputs
O,
// Inputs
I
);
input I;
output O;
assign O = I;
endmodule // IBUFDS

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stubs/hdl/BUFIO.v Normal file
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module BUFIO (/*AUTOARG*/
// Outputs
O,
// Inputs
I
);
input I;
output O;
endmodule // BUFIO

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stubs/hdl/BUFR.v Normal file
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module BUFR (/*AUTOARG*/
// Outputs
O,
// Inputs
I, CE, CLR
);
parameter BUFR_DIVIDE=0;
parameter SIM_DEVICE=0;
input I;
input CE;
input CLR;
output O;
assign O=I & CE & ~CLR;
endmodule // IBUFDS

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stubs/hdl/IBUFDS.v Normal file
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module IBUFDS (/*AUTOARG*/
// Outputs
O,
// Inputs
I, IB
);
parameter DIFF_TERM=0;
parameter IOSTANDARD=0;
input I;
input IB;
output O;
assign O = I & ~IB;
endmodule // IBUFDS

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stubs/hdl/IBUFGDS.v Normal file
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module IBUFGDS (/*AUTOARG*/
// Outputs
O,
// Inputs
I, IB
);
parameter DIFF_TERM=0;
parameter IOSTANDARD=0;
input I;
input IB;
output O;
assign O = I & ~IB;
endmodule // IBUFGDS

58
stubs/hdl/ISERDESE2.v Normal file
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module ISERDESE2 (/*AUTOARG*/
// Outputs
O, QQ, SHIFTOUT1, SHIFTOUT2, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8,
// Inputs
BITSLIP, CE1, CE2, CLKDIVP, CLK, CLKB, CLKDIV, OCLK, OCLKB,
DYNCLKDIVSEL, DYNCLKSEL, D, DDLY, OFB, RST, SHIFTIN1, SHIFTIN2
);
parameter DATA_RATE=0;
parameter DATA_WIDTH=0;
parameter DYN_CLK_INV_EN=0;
parameter DYN_CLKDIV_INV_EN=0;
parameter INIT_Q1=0;
parameter INIT_Q2=0;
parameter INIT_Q3=0;
parameter INIT_Q4=0;
parameter INTERFACE_TYPE=0;
parameter IOBDELAY=0;
parameter NUM_CE=0;
parameter OFB_USED=0;
parameter SERDES_MODE=0;
parameter SRVAL_Q1=0;
parameter SRVAL_Q2=0;
parameter SRVAL_Q3=0;
parameter SRVAL_Q4=0;
output O;
output QQ;
output SHIFTOUT1;
output SHIFTOUT2;
output Q1;
output Q2;
output Q3;
output Q4;
output Q5;
output Q6;
output Q7;
output Q8;
input BITSLIP;
input CE1;
input CE2;
input CLKDIVP;
input CLK;
input CLKB;
input CLKDIV;
input OCLK;
input OCLKB;
input DYNCLKDIVSEL;
input DYNCLKSEL;
input D;
input DDLY;
input OFB;
input RST;
input SHIFTIN1;
input SHIFTIN2;
endmodule // ISERDESE2

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stubs/hdl/OBUFDS.v Normal file
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module OBUFDS (/*AUTOARG*/
// Outputs
O, OB,
// Inputs
I
);
parameter DIFF_TERM=0;
parameter IOSTANDARD=0;
parameter SLEW=0;
input I;
output O;
output OB;
assign O = I;
assign OB = ~I;
endmodule // OBUFDS

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stubs/hdl/OBUFTDS.v Normal file
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module OBUFTDS (/*AUTOARG*/
// Outputs
O, OB,
// Inputs
I, T
);
parameter IOSTANDARD=0;
parameter SLEW=0;
input I;
input T;
output O;
output OB;
assign O = T ? 1'bz : I;
assign OB = T ? 1'bz : ~I;
endmodule // OBUFTDS

21
stubs/hdl/ODDR.v Normal file
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module ODDR (/*AUTOARG*/
// Outputs
Q,
// Inputs
C, CE, D1, D2, R, S
);
parameter DDR_CLK_EDGE=0;
parameter INIT=0;
parameter SRTYPE=0;
input C;
input CE;
input D1;
input D2;
input R;
input S;
output Q;
endmodule // ODDR

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stubs/hdl/OSERDESE2.v Normal file
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module OSERDESE2 ( /*AUTOARG*/
// Outputs
OFB, OQ, SHIFTOUT1, SHIFTOUT2, TBYTEOUT, TFB, TQ, D1, D2, D3, D4,
D5, D6, D7, D8,
// Inputs
CLK, CLKDIV, OCE, RST, SHIFTIN1, SHIFTIN2, T1, T2, T3, T4, TBYTEIN,
TCE
);
parameter DATA_RATE_OQ=0;
parameter DATA_RATE_TQ=0;
parameter DATA_WIDTH=0;
parameter INIT_OQ=0;
parameter INIT_TQ=0;
parameter SERDES_MODE=0;
parameter SRVAL_OQ=0;
parameter SRVAL_TQ=0;
parameter TBYTE_CTL=0;
parameter TBYTE_SRC=0;
parameter TRISTATE_WIDTH=0;
output OFB;
output OQ;
output SHIFTOUT1;
output SHIFTOUT2;
output TBYTEOUT;
output TFB;
output TQ;
input CLK;
input CLKDIV;
input D1;
input D2;
input D3;
input D4;
input D5;
input D6;
input D7;
input D8;
input OCE;
input RST;
input SHIFTIN1;
input SHIFTIN2;
input T1;
input T2;
input T3;
input T4;
input TBYTEIN;
input TCE;
endmodule // OSERDESE2

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module PLLE2_BASE (/*AUTOARG*/
// Outputs
CLKFB, LOCKED, CLKOUT0, CLKOUT1, CLKOUT2, CLKOUT3, CLKOUT4,
CLKOUT5, CLKFBOUT,
// Inputs
CLKIN1, RST, PWRDWN, CLKFBIN
);
parameter BANDWIDTH = 0;
parameter CLKFBOUT_MULT = 0;
parameter CLKFBOUT_PHASE = 0;
parameter CLKIN1_PERIOD = 0;
parameter CLKOUT0_DIVIDE = 0;
parameter CLKOUT0_DUTY_CYCLE = 0;
parameter CLKOUT0_PHASE = 0;
parameter CLKOUT1_DIVIDE = 0;
parameter CLKOUT1_DUTY_CYCLE = 0;
parameter CLKOUT1_PHASE = 0;
parameter CLKOUT2_DIVIDE = 0;
parameter CLKOUT2_DUTY_CYCLE = 0;
parameter CLKOUT2_PHASE = 0;
parameter CLKOUT3_DIVIDE = 0;
parameter CLKOUT3_DUTY_CYCLE = 0;
parameter CLKOUT3_PHASE = 0;
parameter CLKOUT4_DIVIDE = 0;
parameter CLKOUT4_DUTY_CYCLE = 0;
parameter CLKOUT4_PHASE = 0;
parameter CLKOUT5_DIVIDE = 0;
parameter CLKOUT5_DUTY_CYCLE = 0;
parameter CLKOUT5_PHASE = 0;
parameter DIVCLK_DIVIDE = 0;
parameter REF_JITTER1 = 0;
parameter STARTUP_WAIT = 0;
parameter IOSTANDARD = 0;
input CLKIN1;
input RST;
input PWRDWN;
input CLKFBIN;
output CLKFB;
output LOCKED;
output CLKOUT0;
output CLKOUT1;
output CLKOUT2;
output CLKOUT3;
output CLKOUT4;
output CLKOUT5;
output CLKFBOUT;
endmodule // PLLE2_BASE

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module fifo_103x16(/*AUTOARG*/
// Outputs
dout, empty, full, prog_full,
// Inputs
din, rd_clk, rd_en, rst, wr_clk, wr_en
);
input [102:0] din;
output [102:0] dout;
output empty;
output full;
output prog_full;
input rd_clk;
input rd_en;
input rst;
input wr_clk;
input wr_en;
assign dout = 103'b0;
assign empty = 1'b0;
assign full = 1'b0;
assign prog_full = 1'b0;
endmodule // fifo_103x16

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module fifo_103x32(/*AUTOARG*/
// Outputs
dout, empty, full, prog_full,
// Inputs
din, rd_clk, rd_en, rst, wr_clk, wr_en
);
input [102:0] din;
output [102:0] dout;
output empty;
output full;
output prog_full;
input rd_clk;
input rd_en;
input rst;
input wr_clk;
input wr_en;
assign dout = 103'b0;
assign empty = 1'b0;
assign full = 1'b0;
assign prog_full = 1'b0;
endmodule // fifo_103x32

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module fifo_64x16(/*AUTOARG*/
// Outputs
dout, empty, full, prog_full,
// Inputs
din, rd_clk, rd_en, rst, wr_clk, wr_en
);
input [63:0] din;
output [63:0] dout;
output empty;
output full;
output prog_full;
input rd_clk;
input rd_en;
input rst;
input wr_clk;
input wr_en;
assign dout = 103'b0;
assign empty = 1'b0;
assign full = 1'b0;
assign prog_full = 1'b0;
endmodule // fifo_64x16