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Making register map look more like Epiphany
This commit is contained in:
Andreas Olofsson
parent
395a1b3cb7
commit
49bcc348e4
122
elink/README.md
122
elink/README.md
@ -19,31 +19,24 @@ rxi_lclk{p/n} | I | RX clock aligned in the center of the data eye
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rxi_data{p/n}[7:0]| I | RX dual data rate (DDR) that transmits packet
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rxo_rd_wait{p/n} | O | RX push back (output) for read transactions
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rxo_wr_wait{p/n} | O | RX push back (output) for write transactions
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cclk_{p/n} | O | Epiphany differential high speed clock
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chip_resetb | O | Epiphany reset (active low)
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colid[3:0] | O | Epiphany column chip coordinate
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rowid[3:0] | O | Epiphany row chip coordinate
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The Epiphany specific output signals can be left unconnected in systems that
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don't include Epiphany chips.
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###SYSTEM SIDE INTERFACE
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SIGNAL |DIR| DESCRIPTION
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------------------|---|--------------
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elinkid[11:0] | I | Address ID of elink
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hard_reset | I | Reset input
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reset | I | Reset input
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clkin | I | Clock input for CCLK/LCLK PLL
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sys_clk | I | System clock for FIFOs
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clkbypass[2:0] | I | Clocks inputs for bypassing PLL
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testmode | I | Puts elink transmitter in test mode
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rx_lclk_div4 | O | rxi_lclk clock divided by 4
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tx_lclk_div4 | O | txo_lclk clock divided by 4
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clkbypass[2:0] | I | Clocks inputs for bypassing PLL
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embox_not_empty | O | Mailbox not empty (connect to interrupt line)
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embox_full | O | Mailbox is full indicator
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timeout | O | Read request timeout indicator
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mi_en | I | Congiruation access enable
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mi_we | I | Configuration write
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mi_addr[19:0] | I | Configuration register address
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mi_din[31:0] | I | Configuration data input
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mi_dout[31:0] | O | Configuration readback data
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txwr_access | I | TX write
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txwr_packet[103:0]| I | TX write packet
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txwr_wait | O | TX write wait (pushback)
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@ -63,6 +56,18 @@ rxrr_access | O | RX read-response
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rxrr_packet[103:0]| O | RX read-response packet
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rxrr_wait | I | RX read-response wait (pushback)
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###EPIPHANY SIGNALS
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SIGNAL |DIR| DESCRIPTION
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------------------|---|--------------
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cclk_{p/n} | O | Epiphany differential high speed clock
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chip_resetb | O | Epiphany reset (active low)
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colid[3:0] | O | Epiphany column chip coordinate
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rowid[3:0] | O | Epiphany row chip coordinate
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The Epiphany specific output signals can be left unconnected in systems that
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don't include Epiphany chips.
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###I/O PROTOCOL
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The default protocol for the elink is the Epiphany chip to chip interface.
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The Epiphany protocol uses a source synchronous clocks, a packet frame signal,
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@ -130,8 +135,8 @@ using the rx and tx parallel interfaces. Read, write, and read response
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transactions have independent channels into the elink. Data from a receiver
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read request is expected to return on the read response transmit chanel.
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The "access" signals indicate a valid transaction. The wait signals indicate
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that the receiving block is not ready to receive the packet. An elink packet
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The "access" signals indicate a valid transaction. The wait signals indicate
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that the receiving block is not ready to receive the packet. An elink packet
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has the following bit ordering.
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PACKET FIELD | BITS | DESCRIPTION
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@ -155,30 +160,52 @@ added to the 12 bit elink ID that maps to address bits 31:20. As an example,
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if the elink ID is 0x810, then writing to the E_RESET register would be done to
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address 0x810D0000.
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REGISTER | ADDRESS | DESCRIPTION
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---------------|---------|------------------
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E_RESET | 0xD0000 | Soft reset
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E_CLK | 0xD0004 | Clock configuration
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E_CHIPID | 0xD0008 | Chip ID to drive to Epiphany pins
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E_VERSION | 0xD000C | Version number
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ETX_CFG | 0xD0040 | TX configuration
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ETX_STATUS | 0xD0044 | TX status
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ETX_GPIO | 0xD0048 | TX data in GPIO mode
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ETX_MMU | 0xD8000 | TX MMU table
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ERX_CFG | 0xE0000 | RX configuration
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ERX_STATUS | 0xE0004 | RX status register
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ERX_GPIO | 0xE0008 | RX data in GPIO mode
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ERX_RR | 0xE000c | RX read response address
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ERX_OFFSET | 0xE0000 | RX memory offset in remap mode
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ERX_MAILBOXLO | 0xE0040 | RX mailbox (lower 32 bit)
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ERX_MAILBOXHI | 0xE0044 | RX mailbox (upper 32 bits)
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ERX_DMACFG | 0xE0080 | RX DMA configuration
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ERX_DMACOUNT | 0xE0084 | RX DMA count
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ERX_DMASTRIDE | 0xE0088 | RX DMA stride
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ERX_DMASRCADDR | 0xE008c | RX DMA source addres
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ERX_DMADSTADDR | 0xE0090 | RX DMA destination address
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ERX_DMASTATUS | 0xE0094 | RX DMA status
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ERX_MMU | 0xE8000 | RX MMU table
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REGISTER | A | ADDRESS | DESCRIPTION
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---------------|----|---------|------------------
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E_RESET | W | 0xF0200 | Soft reset
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E_CLK | W | 0xF0204 | Clock configuration
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E_CHIPID | W | 0xF0208 | Chip ID to drive to Epiphany pins
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E_VERSION | RW | 0xF020C | Version number (static)
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ETX_CFG | W | 0xF0240 | TX configuration
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ETX_STATUS | R | 0xF0244 | TX status
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ETX_GPIO | W | 0xF0248 | TX data in GPIO mode
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ERX_CFG | W | 0xF0300 | RX configuration
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ERX_STATUS | R | 0xF0304 | RX status register
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ERX_GPIO | R | 0xF0308 | RX data in GPIO mode
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ERX_RR | RW | 0xF030c | RX read response address
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ERX_OFFSET | W | 0xF0310 | RX memory offset in remap mode
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ERX_MAILBOXLO | RW | 0xF0314 | RX mailbox (lower 32 bit)
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ERX_MAILBOXHI | RW | 0xF031c | RX mailbox (upper 32 bits)
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ETX_DMACFG | W | 0xF0500 | RX DMA configuration
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ETX_DMACOUNT | W | 0xF0504 | RX DMA count
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ETX_DMASTRIDE | W | 0xF0508 | RX DMA stride0xE0000
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ETX_DMASRCADDR | W | 0xF050c | RX DMA source addres
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ETX_DMADSTADDR | W | 0xF0510 | RX DMA destination address
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ETX_DMAAUTO0 | W | 0xF0514 | RX DMA slave buffer (lo)
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ETX_DMAAUTO1 | W | 0xF0518 | RX DMA slave buffer (hi)
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ETX_DMASTATUS | W | 0xF051c | RX DMA status
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ERX_DMACFG | W | 0xF0520 | TX DMA configuration
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ERX_DMACOUNT | W | 0xF0524 | TX DMA count
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ERX_DMASTRIDE | W | 0xF0528 | TX DMA stride
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ETX_DMASRCADDR | W | 0xF050c | TX DMA source addres
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ERX_DMADSTADDR | W | 0xF0530 | TX DMA destination address
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ERX_DMAAUTO0 | W | 0xF0534 | TX DMA slave buffer (lo)
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ERX_DMAAUTO1 | W | 0xF0538 | TX DMA slERXave buffer (hi)
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ERX_DMASTATUS | W | 0xF053c | TX DMA status
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ETX_DMADESCR0 | W | 0xF0540 | RX DMA {reserved,config}
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ETX_DMADESCR1 | W | 0xF0544 | TX DMA {dst_stride[15:0],src_stride[15:0]}
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ETX_DMADESCR2 | W | 0xF0548 | TX DMA {reserved,count[15:0]}
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ETX_DMADESCR3 | W | 0xF054c | TX reserved
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ETX_DMADESCR4 | W | 0xF0550 | TX DMA srcaddr[31:0]
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ETX_DMADESCR5 | W | 0xF0554 | TX DMA dstaddr[31:0]
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ERX_DMADESCR0 | W | 0xF0560 | RX DMA {reserved,config}
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ERX_DMADESCR1 | W | 0xF0564 | RX DMA {dst_stride[15:0],src_stride[15:0]}
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ERX_DMADESCR2 | W | 0xF0568 | RX DMA {reserved,count[15:0]}
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ERX_DMADESCR3 | W | 0xF056c | RX reserved
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ERX_DMADESCR4 | W | 0xF0570 | RX DMA srcaddr[31:0]
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ERX_DMADESCR5 | W | 0xF0574 | RX DMA dstaddr[31:0]
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ETX_MMU | RW | 0xE0000 | TX MMU table
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ERX_MMU | RW | 0xE8000 | RX MMU table
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REGISTER DESCRIPTIONS
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===========================================
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@ -193,7 +220,7 @@ FIELD | DESCRIPTION
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[1] | 0: epiphany chip is active
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| 1: epiphany chip in reset
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[2] | 1: Starts an internal reset and clock sequnce block
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(self resetting bit)
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| (self resetting bit)
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###E_CLK (LABS)
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Transmit and Epiphany clock settings.
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@ -341,13 +368,14 @@ FIELD | DESCRIPTION
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[8] | Data from rxi_frame pin
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###ERX_RR
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Last read response data that was received on rxrr_packet[103:0]
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Last read response data that was received on rxrr_packet[103:0].
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FIELD | DESCRIPTION
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-------- |---------------------------------------------------
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[31:0] | Read response data (lower 32 bits)
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###ERX_OFFSET
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Address offset used in the dynamic address remapping mode
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Address offset used in the dynamic address remapping mode.
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FIELD | DESCRIPTION
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-------- |---------------------------------------------------
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@ -363,14 +391,14 @@ FIELD | DESCRIPTION
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###ERX_MAILBOXHI
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Upper 32 bit word of current entry of RX 64-bit wide mailbox FIFO. Reading this
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register causes the RX FIFO read pointer to increment by one
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register causes the RX FIFO read pointer to increment by one.
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FIELD | DESCRIPTION
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-------- |---------------------------------------------------
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[31:0] | Upper data of RX FIFO
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###DMACFG
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Configuration register for DMA
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Configuration register for DMA.
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FIELD | DESCRIPTION
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-------- |---------------------------------------------------
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@ -398,14 +426,14 @@ FIELD | DESCRIPTION
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[31:0] | The number of transfers remaining
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###DMADSTADDR
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The current 32-bit address being transferred
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The current 32-bit address being transferred.
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FIELD | DESCRIPTION
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-------- |---------------------------------------------------
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[31:0] | Current transaction destination address to write to
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###DMASRCADDR
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The current 32-bit address being read from in master mode
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The current 32-bit address being read from in master mode.
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FIELD | DESCRIPTION
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-------- |---------------------------------------------------
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@ -430,7 +458,7 @@ FIELD | DESCRIPTION
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###ERX_MMU
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A table of N entries for translating incoming 12 bit address to a new value.
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Entries are aligned on 8 byte boundaries
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Entries are aligned on 8 byte boundaries.
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FIELD | DESCRIPTION
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-------- |---------------------------------------------------
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