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Making AW main parameter
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@ -39,7 +39,6 @@ module dut (/*AUTOARG*/
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assign access_out ='b0;
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assign packet_out ='b0;
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assign wait_out ='b0;
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assign reset_done = 1'b1;
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endmodule // dut
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@ -1,3 +1,4 @@
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/* verilator lint_off STMTDLY */
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module dv_ctrl(/*AUTOARG*/
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// Outputs
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nreset, clk, start,
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@ -47,11 +48,13 @@ module dv_ctrl(/*AUTOARG*/
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//WAVEFORM DUMP
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//Better solution?
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`ifndef VERILATOR
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initial
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begin
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$dumpfile("waveform.vcd");
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//$dumpvars(0, dv_top);
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end
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`endif
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endmodule // dv_ctrl
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@ -1,3 +1,4 @@
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/* verilator lint_off STMTDLY */
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module dv_driver (/*AUTOARG*/
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// Outputs
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stim_access, stim_packet, stim_wait, stim_done,
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@ -6,15 +7,13 @@ module dv_driver (/*AUTOARG*/
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);
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//Parameters
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parameter N = 1; // "N" packets wide
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parameter AW = 32; // address width
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parameter IDW = 12; // id width
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parameter NAME = "none"; // north, south etc
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parameter STIMS = 1; // number of stimulus
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//derived parameters
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localparam DW = AW; //always the same
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localparam PW = 2*AW+40;//packet width
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parameter N = 1; // "N" packets wide
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parameter AW = 32; // address width
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parameter IDW = 12; // id width
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parameter NAME = "none"; // north, south etc
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parameter STIMS = 1; // number of stimulus
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parameter MAW = 16; // 64KB memory address width
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localparam PW =2*AW+40; // packet width (derived)
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//Control signals
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input clk;
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@ -138,7 +137,8 @@ module dv_driver (/*AUTOARG*/
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.coreid (coreid[IDW-1:0]),
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.access_in (dut_access[j]),
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.packet_in (dut_packet[(j+1)*PW-1:j*PW]),
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.wait_in (wait_in));
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.wait_in (dut_wait[i])
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);
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end
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endgenerate
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@ -2,9 +2,10 @@
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module dv_top();
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//static variables
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parameter PW = 104;
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parameter N = 1;
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parameter IDW = 12;
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parameter AW = 32;
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parameter PW = 2*AW+40;
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//local variables
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integer r;
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@ -94,7 +95,7 @@ module dv_top();
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);
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*/
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dv_driver #(.PW(PW),
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dv_driver #(.AW(AW),
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.N(N),
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.NAME("test"),
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.IDW(IDW)
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