FPGA/oh
1
0
Fork 0
mirror of https://github.com/aolofsson/oh.git synced 2025-01-17 20:02:53 +08:00
Code Issues Projects Releases Wiki Activity

Fixing edge align circuit

Browse Source 
- duh error
- making output positive edge aligned, the negedge nastyness should be maintained within module...
This commit is contained in:
Andreas Olofsson 2015-11-14 23:33:48 -05:00
parent e70c51670c
commit 4b384be602
1 changed files with 20 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

35
common/hdl/edgealign.v
View File

@ -1,19 +1,22 @@
/* Detects the common aligned positive edge for a
* slow/fast clocks
* slow/fast clocks. The circuit uses the negedge of the fast clock
* to sample the slow clock. Output is positive edge sampled.
*
* NOTE: Assumes clocks are aligned and synchronous!
*
* ___________ ___________
* __/ \___________/ \ SLOWCLK
* __/ \___________/ \ SLOWCLK
* __ __ __ __ __ __
* _/ \__/ \__/ \__/ \__/ \__/ \__/ FASTCLK
* ___________ _________
* __/ \___________/ CLK45
* ___________ ___
* ________/ \___________/ CLK135
* _/ \__/ \__/ \__/ \__/ \__/ \__/ FASTCLK
* ___________ _________
* ___/ 1 1 \_0_____0____/ CLK45
* ____________ ___
* ______/ 1 1 \___0____0___/ CLK90
*
* ____ ______
* \__________________/ \________ FIRSTEDGE
* ____ ______
* \________________/ \________ FIRSTEDGE
*
*
*
*/
@ -29,16 +32,18 @@ module edgealign (/*AUTOARG*/
output firstedge;
reg clk45;
reg clk135;
reg clk90;
reg firstedge;
always @ (negedge fastclk)
begin
clk45 <= slowclk;
clk135 <= clk45;
firstedge <= ~clk45 & ~clk135;
end
clk45 <= slowclk;
always @ (posedge fastclk)
begin
clk90 <= clk45;
firstedge <= ~clk45 & clk90;
end
//TODO: parametrized based on 1/N ratios?
endmodule // edgealign