From 4b384be602c35aef00bcda3601df7e47d2f72e59 Mon Sep 17 00:00:00 2001 From: Andreas Olofsson Date: Sat, 14 Nov 2015 23:33:48 -0500 Subject: [PATCH] Fixing edge align circuit - duh error - making output positive edge aligned, the negedge nastyness should be maintained within module... --- common/hdl/edgealign.v | 35 ++++++++++++++++++++--------------- 1 file changed, 20 insertions(+), 15 deletions(-) diff --git a/common/hdl/edgealign.v b/common/hdl/edgealign.v index 243c6e9..233a372 100644 --- a/common/hdl/edgealign.v +++ b/common/hdl/edgealign.v @@ -1,19 +1,22 @@ /* Detects the common aligned positive edge for a - * slow/fast clocks + * slow/fast clocks. The circuit uses the negedge of the fast clock + * to sample the slow clock. Output is positive edge sampled. * * NOTE: Assumes clocks are aligned and synchronous! * * ___________ ___________ - * __/ \___________/ \ SLOWCLK + * __/ \___________/ \ SLOWCLK * __ __ __ __ __ __ - * _/ \__/ \__/ \__/ \__/ \__/ \__/ FASTCLK - * ___________ _________ - * __/ \___________/ CLK45 - * ___________ ___ - * ________/ \___________/ CLK135 + * _/ \__/ \__/ \__/ \__/ \__/ \__/ FASTCLK + * ___________ _________ + * ___/ 1 1 \_0_____0____/ CLK45 + * ____________ ___ + * ______/ 1 1 \___0____0___/ CLK90 * - * ____ ______ - * \__________________/ \________ FIRSTEDGE + * ____ ______ + * \________________/ \________ FIRSTEDGE + * + * * */ @@ -29,16 +32,18 @@ module edgealign (/*AUTOARG*/ output firstedge; reg clk45; - reg clk135; + reg clk90; reg firstedge; always @ (negedge fastclk) - begin - clk45 <= slowclk; - clk135 <= clk45; - firstedge <= ~clk45 & ~clk135; - end + clk45 <= slowclk; + always @ (posedge fastclk) + begin + clk90 <= clk45; + firstedge <= ~clk45 & clk90; + end + //TODO: parametrized based on 1/N ratios? endmodule // edgealign