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Fixing edge align circuit

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- duh error
- making output positive edge aligned, the negedge nastyness should be maintained within module...
This commit is contained in:
Andreas Olofsson 2015-11-14 23:33:48 -05:00
parent e70c51670c
commit 4b384be602
1 changed files with 20 additions and 15 deletions
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31
common/hdl/edgealign.v
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@ -1,19 +1,22 @@
/* Detects the common aligned positive edge for a /* Detects the common aligned positive edge for a
* slow/fast clocks * slow/fast clocks. The circuit uses the negedge of the fast clock
* to sample the slow clock. Output is positive edge sampled.
* *
* NOTE: Assumes clocks are aligned and synchronous! * NOTE: Assumes clocks are aligned and synchronous!
* *
* ___________ ___________ * ___________ ___________
* __/ \___________/ \ SLOWCLK * __/ \___________/ \ SLOWCLK
* __ __ __ __ __ __ * __ __ __ __ __ __
* _/ \__/ \__/ \__/ \__/ \__/ \__/ FASTCLK * _/ \__/ \__/ \__/ \__/ \__/ \__/ FASTCLK
* ___________ _________ * ___________ _________
* __/ \___________/ CLK45 * ___/ 1 1 \_0_____0____/ CLK45
* ___________ ___ * ____________ ___
* ________/ \___________/ CLK135 * ______/ 1 1 \___0____0___/ CLK90
*
* ____ ______
* \________________/ \________ FIRSTEDGE
*
* *
* ____ ______
* \__________________/ \________ FIRSTEDGE
* *
*/ */
@ -29,14 +32,16 @@ module edgealign (/*AUTOARG*/
output firstedge; output firstedge;
reg clk45; reg clk45;
reg clk135; reg clk90;
reg firstedge; reg firstedge;
always @ (negedge fastclk) always @ (negedge fastclk)
clk45 <= slowclk;
always @ (posedge fastclk)
begin begin
clk45 <= slowclk; clk90 <= clk45;
clk135 <= clk45; firstedge <= ~clk45 & clk90;
firstedge <= ~clk45 & ~clk135;
end end
//TODO: parametrized based on 1/N ratios? //TODO: parametrized based on 1/N ratios?