diff --git a/scripts/setenv.sh b/setenv.sh
similarity index 100%
rename from scripts/setenv.sh
rename to setenv.sh
diff --git a/src/mio/hdl/mio.v b/src/mio/hdl/mio.v
index 21ad0e3..47ba338 100644
--- a/src/mio/hdl/mio.v
+++ b/src/mio/hdl/mio.v
@@ -12,10 +12,10 @@ module mio (/*AUTOARG*/
    //#####################################################################
 
    //parameters
+   parameter  N       = 8;          // Mini IO width
    parameter  AW      = 32;         // address width
    localparam PW      = 2*AW+40;    // emesh packet width
    parameter  MPW     = 128;        // mio packet width (>PW)  
-   parameter  N       = 8;          // Mini IO width
    parameter  DEF_CFG = 0;          // Default config   
    parameter  DEF_CLK = 0;          // Default clock
    parameter  TARGET  = "GENERIC";  // GENERIC,XILINX,ALTERA,GENERIC,ASIC
@@ -24,13 +24,13 @@ module mio (/*AUTOARG*/
    input           clk;           // main core clock   
    input 	   nreset;        // async active low reset
       
-   // tx chip interface
+   // tx chip interface (to IO)
    output 	   tx_clk;        // phase shited io_clk   
    output 	   tx_access;     // access signal for IO
    output [N-1:0]  tx_packet;     // packet for IO
    input 	   tx_wait;       // pushback from IO
    
-   // rx chip interface
+   // rx chip interface (from IO)
    input 	   rx_clk;        // rx clock
    input 	   rx_access;     // rx access
    input [N-1:0]   rx_packet;     // rx packet
diff --git a/src/mio/hdl/mio_if.v b/src/mio/hdl/mio_if.v
index 95b096b..3cd718d 100644
--- a/src/mio/hdl/mio_if.v
+++ b/src/mio/hdl/mio_if.v
@@ -16,7 +16,6 @@ module mio_if (/*AUTOARG*/
    //parameters
    parameter  AW  = 32;            // address width
    parameter  PW  = 2*AW +40;      // emesh packet width
-   parameter  N   = 8;             // number of extra bits in    
    parameter  MPW = PW+8;          // mio packet width  
    
    // reset, clk, config
@@ -88,15 +87,16 @@ module mio_if (/*AUTOARG*/
    //#################################################
 
    // parse packet
-   packet2emesh pe2 (.packet_in		(rx_packet_in[PW-1:0]),
-		     /*AUTOINST*/
-		     // Outputs
-		     .write_in		(write_in),
-		     .datamode_in	(datamode_in[1:0]),
-		     .ctrlmode_in	(ctrlmode_in[4:0]),
-		     .dstaddr_in	(dstaddr_in[AW-1:0]),
-		     .srcaddr_in	(srcaddr_in[AW-1:0]),
-		     .data_in		(data_in[AW-1:0]));
+   packet2emesh #(.AW(AW))
+   pe2 (.packet_in		(rx_packet_in[PW-1:0]),
+	/*AUTOINST*/
+	// Outputs
+	.write_in			(write_in),
+	.datamode_in			(datamode_in[1:0]),
+	.ctrlmode_in			(ctrlmode_in[4:0]),
+	.dstaddr_in			(dstaddr_in[AW-1:0]),
+	.srcaddr_in			(srcaddr_in[AW-1:0]),
+	.data_in			(data_in[AW-1:0]));
       
    // datamode
    assign datamode[1:0] = (datasize[3:0]==4'd1) ? 2'b00 :
@@ -133,16 +133,17 @@ module mio_if (/*AUTOARG*/
                                         srcaddr_in[AW-1:0];
 
    //Construct outgoing packet
-   emesh2packet e2p (/*AUTOINST*/
-		     // Outputs
-		     .packet_out	(packet_out[PW-1:0]),
-		     // Inputs
-		     .write_out		(write_out),
-		     .datamode_out	(datamode_out[1:0]),
-		     .ctrlmode_out	(ctrlmode_out[4:0]),
-		     .dstaddr_out	(dstaddr_out[AW-1:0]),
-		     .data_out		(data_out[AW-1:0]),
-		     .srcaddr_out	(srcaddr_out[AW-1:0]));
+   emesh2packet #(.AW(AW))
+   e2p (/*AUTOINST*/
+	// Outputs
+	.packet_out			(packet_out[PW-1:0]),
+	// Inputs
+	.write_out			(write_out),
+	.datamode_out			(datamode_out[1:0]),
+	.ctrlmode_out			(ctrlmode_out[4:0]),
+	.dstaddr_out			(dstaddr_out[AW-1:0]),
+	.data_out			(data_out[AW-1:0]),
+	.srcaddr_out			(srcaddr_out[AW-1:0]));
    
 endmodule // mio_if