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Adding missing parameters statements in mio_if

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This commit is contained in:
Andreas Olofsson 2016-03-23 20:45:15 -04:00
parent ac5a77ec6c
commit 4b87fdae34
3 changed files with 24 additions and 23 deletions
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0
scripts/setenv.sh → setenv.sh
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6
src/mio/hdl/mio.v
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@ -12,10 +12,10 @@ module mio (/*AUTOARG*/
//##################################################################### //#####################################################################
//parameters //parameters
parameter N = 8; // Mini IO width
parameter AW = 32; // address width parameter AW = 32; // address width
localparam PW = 2*AW+40; // emesh packet width localparam PW = 2*AW+40; // emesh packet width
parameter MPW = 128; // mio packet width (>PW) parameter MPW = 128; // mio packet width (>PW)
parameter N = 8; // Mini IO width
parameter DEF_CFG = 0; // Default config parameter DEF_CFG = 0; // Default config
parameter DEF_CLK = 0; // Default clock parameter DEF_CLK = 0; // Default clock
parameter TARGET = "GENERIC"; // GENERIC,XILINX,ALTERA,GENERIC,ASIC parameter TARGET = "GENERIC"; // GENERIC,XILINX,ALTERA,GENERIC,ASIC
@ -24,13 +24,13 @@ module mio (/*AUTOARG*/
input clk; // main core clock input clk; // main core clock
input nreset; // async active low reset input nreset; // async active low reset
// tx chip interface // tx chip interface (to IO)
output tx_clk; // phase shited io_clk output tx_clk; // phase shited io_clk
output tx_access; // access signal for IO output tx_access; // access signal for IO
output [N-1:0] tx_packet; // packet for IO output [N-1:0] tx_packet; // packet for IO
input tx_wait; // pushback from IO input tx_wait; // pushback from IO
// rx chip interface // rx chip interface (from IO)
input rx_clk; // rx clock input rx_clk; // rx clock
input rx_access; // rx access input rx_access; // rx access
input [N-1:0] rx_packet; // rx packet input [N-1:0] rx_packet; // rx packet

41
src/mio/hdl/mio_if.v
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@ -16,7 +16,6 @@ module mio_if (/*AUTOARG*/
//parameters //parameters
parameter AW = 32; // address width parameter AW = 32; // address width
parameter PW = 2*AW +40; // emesh packet width parameter PW = 2*AW +40; // emesh packet width
parameter N = 8; // number of extra bits in
parameter MPW = PW+8; // mio packet width parameter MPW = PW+8; // mio packet width
// reset, clk, config // reset, clk, config
@ -88,15 +87,16 @@ module mio_if (/*AUTOARG*/
//################################################# //#################################################
// parse packet // parse packet
packet2emesh pe2 (.packet_in (rx_packet_in[PW-1:0]), packet2emesh #(.AW(AW))
/*AUTOINST*/ pe2 (.packet_in (rx_packet_in[PW-1:0]),
// Outputs /*AUTOINST*/
.write_in (write_in), // Outputs
.datamode_in (datamode_in[1:0]), .write_in (write_in),
.ctrlmode_in (ctrlmode_in[4:0]), .datamode_in (datamode_in[1:0]),
.dstaddr_in (dstaddr_in[AW-1:0]), .ctrlmode_in (ctrlmode_in[4:0]),
.srcaddr_in (srcaddr_in[AW-1:0]), .dstaddr_in (dstaddr_in[AW-1:0]),
.data_in (data_in[AW-1:0])); .srcaddr_in (srcaddr_in[AW-1:0]),
.data_in (data_in[AW-1:0]));
// datamode // datamode
assign datamode[1:0] = (datasize[3:0]==4'd1) ? 2'b00 : assign datamode[1:0] = (datasize[3:0]==4'd1) ? 2'b00 :
@ -133,16 +133,17 @@ module mio_if (/*AUTOARG*/
srcaddr_in[AW-1:0]; srcaddr_in[AW-1:0];
//Construct outgoing packet //Construct outgoing packet
emesh2packet e2p (/*AUTOINST*/ emesh2packet #(.AW(AW))
// Outputs e2p (/*AUTOINST*/
.packet_out (packet_out[PW-1:0]), // Outputs
// Inputs .packet_out (packet_out[PW-1:0]),
.write_out (write_out), // Inputs
.datamode_out (datamode_out[1:0]), .write_out (write_out),
.ctrlmode_out (ctrlmode_out[4:0]), .datamode_out (datamode_out[1:0]),
.dstaddr_out (dstaddr_out[AW-1:0]), .ctrlmode_out (ctrlmode_out[4:0]),
.data_out (data_out[AW-1:0]), .dstaddr_out (dstaddr_out[AW-1:0]),
.srcaddr_out (srcaddr_out[AW-1:0])); .data_out (data_out[AW-1:0]),
.srcaddr_out (srcaddr_out[AW-1:0]));
endmodule // mio_if endmodule // mio_if