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Fixing nasty glitch bug on clock

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-Created phantom event simulator
-Lucky to catch it quickly
-Don't know wtf i was thinking with that circuit...
This commit is contained in:
Andreas Olofsson 2016-08-24 01:14:05 -04:00
parent f7ce7b800c
commit 4c6cdcaf74
1 changed files with 8 additions and 3 deletions
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11
src/spi/hdl/spi_master_io.v
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@ -24,7 +24,7 @@ module spi_master_io
output [63:0] rx_data, // rx data
output rx_access, // transfer done
// IO interface
output sclk, // spi clock
output reg sclk, // spi clock
output mosi, // slave input
output ss, // slave select
input miso // slave output
@ -124,9 +124,14 @@ module spi_master_io
//#################################
//# DRIVE OUTPUT CLOCK
//#################################
always @ (posedge clk or negedge nreset)
if(~nreset)
sclk <= 1'b0;
else if (period_match & (spi_state[2:0]==`SPI_DATA))
sclk <= 1'b1;
else if (phase_match & (spi_state[2:0]==`SPI_DATA))
sclk <= 1'b0;
assign sclk = clkout & (spi_state[2:0]==`SPI_DATA);
//#################################
//# TX SHIFT REGISTER
//#################################