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Fixing synthesis compilation warnings

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- Could supress warning printout, but you can't control people's synthesis scripts. Better to fix once than N times...
This commit is contained in:
Andreas Olofsson 2016-04-17 09:49:07 -04:00
parent 96e13629aa
commit 4e513cfcce
6 changed files with 30 additions and 30 deletions
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4
src/common/hdl/oh_csa32.v
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@ -17,7 +17,7 @@ module oh_csa32 #(parameter DW = 1, // data width
generate
if(ASIC)
begin
begin : asic
asic_csa32 i_csa32[DW-1:0] (.s(s[DW-1:0]),
.c(c[DW-1:0]),
.in2(in2[DW-1:0]),
@ -25,7 +25,7 @@ module oh_csa32 #(parameter DW = 1, // data width
.in0(in0[DW-1:0]));
end
else
begin
begin : generic
assign s[DW-1:0] = in0[DW-1:0] ^ in1[DW-1:0] ^ in2[DW-1:0];
assign c[DW-1:0] = (in0[DW-1:0] & in1[DW-1:0]) |
(in1[DW-1:0] & in2[DW-1:0]) |

27
src/common/hdl/oh_fifo_sync.v
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@ -11,21 +11,22 @@ module oh_fifo_sync #(parameter DW = 104, //FIFO width
parameter AW = $clog2(DEPTH) //rd_count width
)
(
input clk, // clock
input nreset, // active high async reset
input [DW-1:0] din, // data to write
input wr_en, // write fifo
input rd_en, // read fifo
output [DW-1:0] dout, // output data (next cycle)
output full, // fifo full
output prog_full, // fifo is almost full
output empty, // fifo is empty
output [AW-1:0] rd_count // valid entries in fifo
input clk, // clock
input nreset, // active high async reset
input [DW-1:0] din, // data to write
input wr_en, // write fifo
input rd_en, // read fifo
output [DW-1:0] dout, // output data (next cycle)
output full, // fifo full
output prog_full, // fifo is almost full
output empty, // fifo is empty
output reg [AW-1:0] rd_count // valid entries in fifo
);
reg [AW-1:0] wr_addr;
reg [AW-1:0] rd_addr;
reg [AW-1:0] rd_count;
reg [AW-1:0] wr_addr;
reg [AW-1:0] rd_addr;
wire fifo_read;
wire fifo_write;
assign empty = (rd_count[AW-1:0] == 0);
assign prog_full = (rd_count[AW-1:0] >= PROG_FULL);

5
src/common/hdl/oh_lat0.v
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@ -7,11 +7,10 @@
module oh_lat0 #(parameter DW = 1) // data width
( input clk, // clk, latch when clk=0
input [DW-1:0] in, // input data
output [DW-1:0] out // output data (stable/latched when clk=1)
input [DW-1:0] in, // input data
output reg [DW-1:0] out // output data (stable/latched when clk=1)
);
reg [DW-1:0] out;
always @ (clk or in)
if (!clk)
out[DW-1:0] <= in[DW-1:0];

3
src/common/hdl/oh_lat1.v
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@ -8,10 +8,9 @@
module oh_lat1 #(parameter DW = 1) // data width
( input clk, // clk, latch when clk=1
input [DW-1:0] in, // input data
output [DW-1:0] out // output data (stable/latched when clk=0)
output reg [DW-1:0] out // output data (stable/latched when clk=0)
);
reg [DW-1:0] out;
always @ (clk or in)
if (clk)
out[DW-1:0] <= in[DW-1:0];

4
src/common/hdl/oh_memory_dp.v
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@ -39,7 +39,7 @@ module oh_memory_dp # (parameter DW = 104, //memory width
generate
if(ASIC)
begin
begin : asic
oh_memory_ram #(.DW(DW),
.DEPTH(DEPTH))
i_sram (//read port
@ -55,7 +55,7 @@ module oh_memory_dp # (parameter DW = 104, //memory width
.wr_din (wr_din[DW-1:0]));
end // if (ASIC)
else
begin
begin : generic
oh_memory_ram #(.DW(DW),
.DEPTH(DEPTH))
oh_memory_ram (//read port

17
src/common/hdl/oh_memory_sp.v
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@ -5,11 +5,12 @@
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_memory_sp # (parameter DW = 104, // memory width
parameter DEPTH = 32, // memory depth
parameter PROJ = "", // project name
parameter ASIC = 0, // use ASIC lib
parameter MCW = 8 // repair/config vector width
module oh_memory_sp # (parameter DW = 104, // memory width
parameter DEPTH = 32, // memory depth
parameter PROJ = "", // project name
parameter ASIC = 0, // use ASIC lib
parameter MCW = 8, // repair/config width
parameter AW = $clog2(DEPTH) // address bus width
)
(// memory interface (single port)
input clk, // clock
@ -34,11 +35,11 @@ module oh_memory_sp # (parameter DW = 104, // memory width
input [DW-1:0] bist_din // data input
);
parameter AW = $clog2(DEPTH); // address bus width
generate
if(ASIC)
begin
begin : asic
asic_sram_sp #(.DW(DW),
.DEPTH(DEPTH),
.PROJ(PROJ),
@ -65,7 +66,7 @@ module oh_memory_sp # (parameter DW = 104, // memory width
.bist_din (bist_din[DW-1:0]));
end
else
begin
begin : generic
oh_memory_ram #(.DW(DW),
.DEPTH(DEPTH))
oh_memory_ram (//read port