Fixing synthesis compilation warnings

- Could supress warning printout, but you can't control people's synthesis scripts. Better to fix once than N times...

src/common/hdl/oh_csa32.v

@@ -17,7 +17,7 @@ module oh_csa32 #(parameter DW   = 1, // data width
 
    generate
       if(ASIC)	
-	begin
+	begin : asic
 	   asic_csa32 i_csa32[DW-1:0] (.s(s[DW-1:0]),
 				       .c(c[DW-1:0]),
 				       .in2(in2[DW-1:0]),
@@ -25,7 +25,7 @@ module oh_csa32 #(parameter DW   = 1, // data width
 				       .in0(in0[DW-1:0]));
 	end	
       else
-	begin
+	begin : generic
 	   assign s[DW-1:0] = in0[DW-1:0] ^ in1[DW-1:0] ^ in2[DW-1:0];
 	   assign c[DW-1:0] = (in0[DW-1:0] & in1[DW-1:0]) | 
 			      (in1[DW-1:0] & in2[DW-1:0]) | 

src/common/hdl/oh_fifo_sync.v

@@ -20,12 +20,13 @@ module oh_fifo_sync #(parameter DW        = 104,      //FIFO width
    output 	       full, // fifo full
    output 	       prog_full, // fifo is almost full
    output 	       empty, // fifo is empty  
-   output [AW-1:0] rd_count     // valid entries in fifo
+   output reg [AW-1:0] rd_count     // valid entries in fifo
  );
    
    reg [AW-1:0]        wr_addr;
    reg [AW-1:0]        rd_addr;
-   reg [AW-1:0]  rd_count;
+   wire 	       fifo_read;
+   wire 	       fifo_write;
    
    assign empty       = (rd_count[AW-1:0] == 0);   
    assign prog_full   = (rd_count[AW-1:0] >= PROG_FULL);   

src/common/hdl/oh_lat0.v

@@ -8,10 +8,9 @@
 module oh_lat0 #(parameter DW = 1) // data width
    ( input 	     clk, // clk, latch when clk=0
      input [DW-1:0] 	 in, // input data
-     output [DW-1:0] out  // output data (stable/latched when clk=1)
+     output reg [DW-1:0] out  // output data (stable/latched when clk=1)
      );
    
-   reg [DW-1:0]      out;
    always @ (clk or in)
      if (!clk)
        out[DW-1:0] <= in[DW-1:0];

src/common/hdl/oh_lat1.v

@@ -8,10 +8,9 @@
 module oh_lat1 #(parameter DW = 1) // data width
    ( input 	     clk, // clk, latch when clk=1
      input [DW-1:0]  in,  // input data
-     output [DW-1:0] out  // output data (stable/latched when clk=0)
+     output reg [DW-1:0] out  // output data (stable/latched when clk=0)
      );
 
-   reg [DW-1:0]      out;
    always @ (clk or in)
      if (clk)
        out[DW-1:0] <= in[DW-1:0];

src/common/hdl/oh_memory_dp.v

@@ -39,7 +39,7 @@ module oh_memory_dp # (parameter DW    = 104,      //memory width
    
    generate
       if(ASIC)
-	begin
+	begin : asic
 	   oh_memory_ram #(.DW(DW),
 			   .DEPTH(DEPTH))	     
 	   i_sram (//read port
@@ -55,7 +55,7 @@ module oh_memory_dp # (parameter DW    = 104,      //memory width
 		  .wr_din	(wr_din[DW-1:0]));
 	end // if (ASIC)
       else
-	begin
+	begin : generic
 	   oh_memory_ram #(.DW(DW),
 			   .DEPTH(DEPTH))	     
 	   oh_memory_ram (//read port

src/common/hdl/oh_memory_sp.v

@@ -9,7 +9,8 @@ module oh_memory_sp  # (parameter DW    = 104,  // memory width
 			parameter DEPTH = 32,           // memory depth
 			parameter PROJ  = "",           // project name
 			parameter ASIC  = 0,            // use ASIC lib
-			parameter MCW   = 8     // repair/config vector width
+			parameter MCW   = 8,            // repair/config width
+			parameter AW    = $clog2(DEPTH) // address bus width  
 		       ) 
    (// memory interface (single port)
     input 	    clk, // clock
@@ -34,11 +35,11 @@ module oh_memory_sp  # (parameter DW    = 104,  // memory width
     input [DW-1:0]  bist_din  // data input
     );
 
-   parameter AW      = $clog2(DEPTH);  // address bus width  
+   
   
    generate
       if(ASIC)
-	begin
+	begin : asic
 	   asic_sram_sp #(.DW(DW),
 			  .DEPTH(DEPTH),
 			  .PROJ(PROJ),
@@ -65,7 +66,7 @@ module oh_memory_sp  # (parameter DW    = 104,  // memory width
 		   .bist_din   (bist_din[DW-1:0]));
 	end
       else
-	begin
+	begin : generic
 	   oh_memory_ram #(.DW(DW),
 			   .DEPTH(DEPTH))	     
 	   oh_memory_ram (//read port