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Making simulation more "real"

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-Working with timescale (for viewer mostly)
-Now using TARGET_XILINX as default in sim
This commit is contained in:
Andreas Olofsson 2015-05-06 12:21:39 -04:00
parent a36875ac09
commit 4f487d498e
3 changed files with 25 additions and 27 deletions
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38
elink/dv/dv_elink.v
View File

@ -20,7 +20,7 @@ module dv_elink(/*AUTOARG*/
//Basic
input [CW-1:0] clk; // Core clock
input [CW-1:0] clk; // clocks
input reset; // Reset
output dut_passed; // Indicates passing test
output dut_failed; // Indicates failing test
@ -185,8 +185,8 @@ module dv_elink(/*AUTOARG*/
/*elink AUTO_TEMPLATE (.reset (reset),
// Outputs
.pll_bypass ({clkin,clkin,clkin,clkin}),
.clkin (clkin),
.sys_clk (clk[1]),
.pll_clkin (clkin),
.sys_clk (clk[0]),
.\(.*\) (@"(substring vl-cell-name 0 6)"_\1[]),
);
*/
@ -235,9 +235,8 @@ module dv_elink(/*AUTOARG*/
.timeout (elink0_timeout), // Templated
// Inputs
.reset (reset), // Templated
.clkin (clkin), // Templated
.sys_clk (clk[1]), // Templated
.pll_bypass ({clkin,clkin,clkin,clkin}), // Templated
.pll_clkin (clkin), // Templated
.sys_clk (clk[0]), // Templated
.rxwr_wait (elink0_rxwr_wait), // Templated
.rxrd_wait (elink0_rxrd_wait), // Templated
.rxrr_wait (elink0_rxrr_wait), // Templated
@ -301,9 +300,8 @@ module dv_elink(/*AUTOARG*/
.timeout (elink1_timeout), // Templated
// Inputs
.reset (reset), // Templated
.clkin (clkin), // Templated
.sys_clk (clk[1]), // Templated
.pll_bypass ({clkin,clkin,clkin,clkin}), // Templated
.pll_clkin (clkin), // Templated
.sys_clk (clk[0]), // Templated
.rxwr_wait (elink1_rxwr_wait), // Templated
.rxrd_wait (elink1_rxrd_wait), // Templated
.rxrr_wait (elink1_rxrr_wait), // Templated
@ -324,8 +322,8 @@ module dv_elink(/*AUTOARG*/
.access_out (elink2_access),
.packet_out (elink2_packet[PW-1:0]),
// Inputs
.clk_in (clk[1]),
.clk_out (clk[1]),
.clk_in (clk[0]),
.clk_out (clk[0]),
.reset (reset),
.access_in (ext_access),
.packet_in (ext_packet[PW-1:0]),
@ -350,10 +348,10 @@ module dv_elink(/*AUTOARG*/
.c0_mesh_wait_out (elink2_wait_out),
// Inputs
.reset (reset),
.c0_clk_in (clk[1]),
.c1_clk_in (clk[1]),
.c2_clk_in (clk[1]),
.c3_clk_in (clk[1]),
.c0_clk_in (clk[0]),
.c1_clk_in (clk[0]),
.c2_clk_in (clk[0]),
.c3_clk_in (clk[0]),
.rxi_data (elink0_txo_data_p[7:0]),
.rxi_lclk (elink0_txo_lclk_p),
.rxi_frame (elink0_txo_frame_p),
@ -390,7 +388,7 @@ module dv_elink(/*AUTOARG*/
*/
ememory emem (.wait_in (1'b0), //only one read at a time, set to zero for no1
.clk (clk[1]),
.clk (clk[0]),
.wait_out (emem_wait),
/*AUTOINST*/
// Outputs
@ -417,7 +415,7 @@ module dv_elink(/*AUTOARG*/
emesh_monitor #(.NAME("stimulus")) ext_monitor (.emesh_wait ((dut_rd_wait | dut_wr_wait)),//TODO:fix collisions
.clk (clk[1]),
.clk (clk[0]),
/*AUTOINST*/
// Inputs
.reset (reset),
@ -427,7 +425,7 @@ module dv_elink(/*AUTOARG*/
.emesh_packet (ext_packet[PW-1:0])); // Templated
emesh_monitor #(.NAME("dut")) dut_monitor (.emesh_wait (1'b0),
.clk (clk[1]),
.clk (clk[0]),
/*AUTOINST*/
// Inputs
.reset (reset),
@ -437,7 +435,7 @@ module dv_elink(/*AUTOARG*/
.emesh_packet (dut_packet[PW-1:0])); // Templated
emesh_monitor #(.NAME("emem")) mem_monitor (.emesh_wait (1'b0),
.clk (clk[1]),
.clk (clk[0]),
.emesh_access (emem_access),
.emesh_packet (emem_packet[PW-1:0]),
/*AUTOINST*/
@ -451,7 +449,7 @@ module dv_elink(/*AUTOARG*/
// Outputs
.txopll_bypass ({clkin,clkin,clkin,clkin}),
.clkin (clkin),
.sys_clk (clk[1]),
.sys_clk (clk[0]),
.\(.*\) (@"(substring vl-cell-name 0 6)"_\1[]),
);
*/

10
elink/dv/dv_elink_tb.v
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@ -1,3 +1,4 @@
`timescale 1ns/1ps
module dv_elink_tb();
parameter AW=32;
parameter DW=32;
@ -47,10 +48,9 @@ module dv_elink_tb();
//Forever clock
always
#1 clk[0] = ~clk[0];//clock for elink
#1 clk[0] = ~clk[0]; //fast clock
always
#50 clk[1] = ~clk[1];//clock for axi interface
//should make variable to really test all fifos
#50 clk[1] = ~clk[1]; //slow clock
wire clkstim = clk[1];
@ -140,7 +140,7 @@ always @ (posedge clkstim)
wire [PW-1:0] packet_out; // From e2p of emesh2packet.v
// End of automatics
emesh2packet e2p (/*AUTOINST*/
emesh2packet e2p (
// Outputs
.packet_out (ext_packet[PW-1:0]),
// Inputs
@ -172,7 +172,7 @@ always @ (posedge clkstim)
endmodule // dv_elink_tb
// Local Variables:
// verilog-library-directories:("." "../../common/hdl")
// verilog-library-directories:("." "../../emesh/hdl")
// End:

2
elink/dv/run.sh
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@ -7,7 +7,7 @@
TRANS=$(wc -l test.memh)
TRANS=${TRANS:0:3}
#RANDOM TEST
iverilog -f elink.cmd -DMANUAL -DTRANS=$TRANS -DTESTNAME=test.memh
iverilog -f elink.cmd -DMANUAL -DTRANS=$TRANS -DTESTNAME=test.memh -DTARGET_XILINX
#iverilog -f elink.cmd -DAUTO
#Running sim