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Making simulation more "real"
-Working with timescale (for viewer mostly) -Now using TARGET_XILINX as default in sim
This commit is contained in:
Andreas Olofsson
parent
a36875ac09
commit
4f487d498e
@ -20,7 +20,7 @@ module dv_elink(/*AUTOARG*/
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//Basic
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input [CW-1:0] clk; // Core clock
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input [CW-1:0] clk; // clocks
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input reset; // Reset
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output dut_passed; // Indicates passing test
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output dut_failed; // Indicates failing test
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@ -185,8 +185,8 @@ module dv_elink(/*AUTOARG*/
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/*elink AUTO_TEMPLATE (.reset (reset),
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// Outputs
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.pll_bypass ({clkin,clkin,clkin,clkin}),
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.clkin (clkin),
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.sys_clk (clk[1]),
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.pll_clkin (clkin),
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.sys_clk (clk[0]),
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.\(.*\) (@"(substring vl-cell-name 0 6)"_\1[]),
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);
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*/
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@ -235,9 +235,8 @@ module dv_elink(/*AUTOARG*/
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.timeout (elink0_timeout), // Templated
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// Inputs
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.reset (reset), // Templated
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.clkin (clkin), // Templated
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.sys_clk (clk[1]), // Templated
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.pll_bypass ({clkin,clkin,clkin,clkin}), // Templated
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.pll_clkin (clkin), // Templated
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.sys_clk (clk[0]), // Templated
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.rxwr_wait (elink0_rxwr_wait), // Templated
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.rxrd_wait (elink0_rxrd_wait), // Templated
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.rxrr_wait (elink0_rxrr_wait), // Templated
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@ -301,9 +300,8 @@ module dv_elink(/*AUTOARG*/
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.timeout (elink1_timeout), // Templated
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// Inputs
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.reset (reset), // Templated
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.clkin (clkin), // Templated
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.sys_clk (clk[1]), // Templated
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.pll_bypass ({clkin,clkin,clkin,clkin}), // Templated
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.pll_clkin (clkin), // Templated
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.sys_clk (clk[0]), // Templated
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.rxwr_wait (elink1_rxwr_wait), // Templated
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.rxrd_wait (elink1_rxrd_wait), // Templated
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.rxrr_wait (elink1_rxrr_wait), // Templated
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@ -324,8 +322,8 @@ module dv_elink(/*AUTOARG*/
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.access_out (elink2_access),
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.packet_out (elink2_packet[PW-1:0]),
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// Inputs
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.clk_in (clk[1]),
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.clk_out (clk[1]),
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.clk_in (clk[0]),
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.clk_out (clk[0]),
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.reset (reset),
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.access_in (ext_access),
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.packet_in (ext_packet[PW-1:0]),
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@ -350,10 +348,10 @@ module dv_elink(/*AUTOARG*/
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.c0_mesh_wait_out (elink2_wait_out),
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// Inputs
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.reset (reset),
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.c0_clk_in (clk[1]),
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.c1_clk_in (clk[1]),
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.c2_clk_in (clk[1]),
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.c3_clk_in (clk[1]),
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.c0_clk_in (clk[0]),
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.c1_clk_in (clk[0]),
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.c2_clk_in (clk[0]),
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.c3_clk_in (clk[0]),
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.rxi_data (elink0_txo_data_p[7:0]),
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.rxi_lclk (elink0_txo_lclk_p),
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.rxi_frame (elink0_txo_frame_p),
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@ -390,7 +388,7 @@ module dv_elink(/*AUTOARG*/
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*/
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ememory emem (.wait_in (1'b0), //only one read at a time, set to zero for no1
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.clk (clk[1]),
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.clk (clk[0]),
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.wait_out (emem_wait),
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/*AUTOINST*/
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// Outputs
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@ -417,7 +415,7 @@ module dv_elink(/*AUTOARG*/
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emesh_monitor #(.NAME("stimulus")) ext_monitor (.emesh_wait ((dut_rd_wait | dut_wr_wait)),//TODO:fix collisions
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.clk (clk[1]),
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.clk (clk[0]),
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/*AUTOINST*/
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// Inputs
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.reset (reset),
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@ -427,7 +425,7 @@ module dv_elink(/*AUTOARG*/
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.emesh_packet (ext_packet[PW-1:0])); // Templated
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emesh_monitor #(.NAME("dut")) dut_monitor (.emesh_wait (1'b0),
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.clk (clk[1]),
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.clk (clk[0]),
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/*AUTOINST*/
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// Inputs
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.reset (reset),
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@ -437,7 +435,7 @@ module dv_elink(/*AUTOARG*/
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.emesh_packet (dut_packet[PW-1:0])); // Templated
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emesh_monitor #(.NAME("emem")) mem_monitor (.emesh_wait (1'b0),
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.clk (clk[1]),
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.clk (clk[0]),
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.emesh_access (emem_access),
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.emesh_packet (emem_packet[PW-1:0]),
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/*AUTOINST*/
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@ -451,7 +449,7 @@ module dv_elink(/*AUTOARG*/
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// Outputs
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.txopll_bypass ({clkin,clkin,clkin,clkin}),
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.clkin (clkin),
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.sys_clk (clk[1]),
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.sys_clk (clk[0]),
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.\(.*\) (@"(substring vl-cell-name 0 6)"_\1[]),
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);
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*/
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@ -1,3 +1,4 @@
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`timescale 1ns/1ps
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module dv_elink_tb();
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parameter AW=32;
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parameter DW=32;
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@ -12,7 +13,7 @@ module dv_elink_tb();
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/* verilator lint_off STMTDLY */
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/* verilator lint_off UNOPTFLAT */
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//REGS
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reg [1:0] clk;
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reg [1:0] clk;
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reg reset;
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reg go;
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reg [1:0] datamode;
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@ -47,10 +48,9 @@ module dv_elink_tb();
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//Forever clock
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always
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#1 clk[0] = ~clk[0];//clock for elink
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#1 clk[0] = ~clk[0]; //fast clock
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always
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#50 clk[1] = ~clk[1];//clock for axi interface
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//should make variable to really test all fifos
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#50 clk[1] = ~clk[1]; //slow clock
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wire clkstim = clk[1];
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@ -140,7 +140,7 @@ always @ (posedge clkstim)
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wire [PW-1:0] packet_out; // From e2p of emesh2packet.v
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// End of automatics
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emesh2packet e2p (/*AUTOINST*/
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emesh2packet e2p (
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// Outputs
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.packet_out (ext_packet[PW-1:0]),
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// Inputs
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@ -172,7 +172,7 @@ always @ (posedge clkstim)
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endmodule // dv_elink_tb
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// Local Variables:
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// verilog-library-directories:("." "../../common/hdl")
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// verilog-library-directories:("." "../../emesh/hdl")
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// End:
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@ -7,7 +7,7 @@
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TRANS=$(wc -l test.memh)
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TRANS=${TRANS:0:3}
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#RANDOM TEST
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iverilog -f elink.cmd -DMANUAL -DTRANS=$TRANS -DTESTNAME=test.memh
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iverilog -f elink.cmd -DMANUAL -DTRANS=$TRANS -DTESTNAME=test.memh -DTARGET_XILINX
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#iverilog -f elink.cmd -DAUTO
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#Running sim
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